From 30e56dafebc6d5427d68e8fde2307b1114b6a01a Mon Sep 17 00:00:00 2001 From: Jonatan Antoni Date: Wed, 11 Oct 2023 13:04:17 +0200 Subject: [PATCH] Update compiler header. --- .github/workflows/corevalidation.yml | 18 +-- .../Core/Include/a-profile/cmsis_armclang_a.h | 123 ++++++++++++++++- CMSIS/Core/Include/a-profile/cmsis_gcc_a.h | 125 ++++++++++++++---- CMSIS/Core/Include/m-profile/cmsis_gcc_m.h | 33 ++++- .../Project/vcpkg-configuration.json | 4 +- 5 files changed, 250 insertions(+), 53 deletions(-) diff --git a/.github/workflows/corevalidation.yml b/.github/workflows/corevalidation.yml index 1c2518f72..2d91e05cb 100644 --- a/.github/workflows/corevalidation.yml +++ b/.github/workflows/corevalidation.yml @@ -58,28 +58,12 @@ jobs: vcpkg-${{ runner.os }}-${{ runner.arch }}- path: /home/runner/.vcpkg - - name: Cache LLVM/Clang 17.0.0-devdrop0 - if: matrix.compiler == 'Clang' - uses: actions/cache@v3 - with: - key: clang-17.0.0-devdrop0-${{ runner.os }}-${{ runner.arch }}-${{ github.run_id }}-${{ matrix.compiler }} - restore-keys: | - clang-17.0.0-devdrop0-${{ runner.os }}-${{ runner.arch }}- - clang-17.0.0-devdrop0 - path: /home/runner/LLVMEmbeddedToolchainForArm-17.0.0-Linux-x86_64 - - - name: Install LLVM/Clang 17.0.0-devdrop0 + - name: Install LLVM/Clang dependencies if: matrix.compiler == 'Clang' working-directory: /home/runner run: | sudo apt-get update sudo apt-get install libtinfo5 - if [[ ! -d LLVMEmbeddedToolchainForArm-17.0.0-Linux-x86_64 ]]; then - wget https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/preview-17.0.0-devdrop0/LLVMEmbeddedToolchainForArm-17.0.0-Linux-x86_64.tar.xz - tar -xf LLVMEmbeddedToolchainForArm-17.0.0-Linux-x86_64.tar.xz - fi - ./LLVMEmbeddedToolchainForArm-17.0.0-Linux-x86_64/bin/clang --version - echo "CLANG_TOOLCHAIN_17_0_0=$(pwd)/LLVMEmbeddedToolchainForArm-17.0.0-Linux-x86_64/bin" >> $GITHUB_ENV - name: Prepare vcpkg env working-directory: ./CMSIS/CoreValidation/Project diff --git a/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h b/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h index eac098c3f..c63a1b69b 100644 --- a/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h +++ b/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang_a.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.2.2 - * @date 13. November 2022 + * @version V1.2.3 + * @date 11. October 2023 ******************************************************************************/ /* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -327,6 +327,102 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) */ #define __USAT __builtin_arm_usat +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) ); +} + /* ################### Compiler specific Intrinsics ########################### */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) @@ -434,19 +530,36 @@ __STATIC_FORCEINLINE void __disable_fault_irq(void) __ASM volatile ("cpsid f" : : : "memory"); } + /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ -#define __get_FPSCR __builtin_arm_get_fpscr +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if (__ARM_FP >= 1) + return __builtin_arm_get_fpscr(); + #else + return(0U); + #endif +} + /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ -#define __set_FPSCR __builtin_arm_set_fpscr +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if (__ARM_FP >= 1) + __builtin_arm_set_fpscr(fpscr); + #else + (void)fpscr; + #endif +} + /** \brief Get CPSR Register \return CPSR Register value diff --git a/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h b/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h index 544035091..e43606c99 100644 --- a/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h +++ b/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc_a.h * @brief CMSIS compiler GCC header file - * @version V1.3.3 - * @date 13. November 2022 + * @version V1.3.4 + * @date 11. October 2023 ******************************************************************************/ /* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -444,6 +444,102 @@ __extension__ \ __RES; \ }) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @@ -499,19 +595,8 @@ __STATIC_FORCEINLINE void __disable_fault_irq(void) */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #if __has_builtin(__builtin_arm_get_fpscr) - // Re-enable using built-in when GCC has been fixed - // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + #if (__ARM_FP >= 1) return __builtin_arm_get_fpscr(); - #else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); - #endif #else return(0U); #endif @@ -525,16 +610,8 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #if __has_builtin(__builtin_arm_set_fpscr) - // Re-enable using built-in when GCC has been fixed - // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + #if (__ARM_FP >= 1) __builtin_arm_set_fpscr(fpscr); - #else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); - #endif #else (void)fpscr; #endif diff --git a/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h b/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h index 98125b10e..ba5eafe00 100644 --- a/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h +++ b/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_gcc_m.h * @brief CMSIS compiler GCC header file - * @version V6.0.0 - * @date 27. July 2023 + * @version V6.0.1 + * @date 11. October 2023 ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. @@ -345,7 +345,6 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) return (op1 >> op2) | (op1 << (32U - op2)); } - /** \brief Breakpoint \details Causes the processor to enter Debug state. @@ -1638,9 +1637,33 @@ __extension__ \ __RES; \ }) -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; +} -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { diff --git a/CMSIS/CoreValidation/Project/vcpkg-configuration.json b/CMSIS/CoreValidation/Project/vcpkg-configuration.json index e2d635c26..2c96be693 100644 --- a/CMSIS/CoreValidation/Project/vcpkg-configuration.json +++ b/CMSIS/CoreValidation/Project/vcpkg-configuration.json @@ -15,8 +15,8 @@ "microsoft:ninja": "^1.10.2", "arm:compilers/arm/armclang":"^6.20.0", "arm:compilers/arm/arm-none-eabi-gcc": "^12.2.1-0", - "arm:compilers/arm/llvm-embedded": "^16.0.0", - "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.0.0-0", + "arm:compilers/arm/llvm-embedded": "^17.0.1-0", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0", "arm:models/arm/avh": "^11.21.15" } }