diff --git a/examples/evkbmimxrt1060/bootloader/main.c b/examples/evkbmimxrt1060/bootloader/main.c index 4de1dff..37fa811 100644 --- a/examples/evkbmimxrt1060/bootloader/main.c +++ b/examples/evkbmimxrt1060/bootloader/main.c @@ -59,7 +59,6 @@ int main( void ) #endif /* Init board hardware. */ - BOARD_ConfigMPU(); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); diff --git a/examples/evkbmimxrt1060/bootloader/sblconfig.h b/examples/evkbmimxrt1060/bootloader/sblconfig.h index ad5e670..5cd2361 100644 --- a/examples/evkbmimxrt1060/bootloader/sblconfig.h +++ b/examples/evkbmimxrt1060/bootloader/sblconfig.h @@ -37,6 +37,7 @@ /* secure */ #define COMPONENT_MCUBOOT_SECURE +//#define CONFIG_BOOT_SIGNATURE_TYPE_ROM #define CONFIG_BOOT_SIGNATURE #define CONFIG_BOOT_SIGNATURE_TYPE_RSA #define CONFIG_BOOT_SIGNATURE_TYPE_RSA_LEN 2048 diff --git a/examples/evkbmimxrt1060/bootloader/signing_pub_key.c b/examples/evkbmimxrt1060/bootloader/signing_pub_key.c index dc0943f..a7ab319 100644 --- a/examples/evkbmimxrt1060/bootloader/signing_pub_key.c +++ b/examples/evkbmimxrt1060/bootloader/signing_pub_key.c @@ -43,3 +43,4 @@ const unsigned char ecdsa_pub_key[] = { 0x00 }; const unsigned int ecdsa_pub_key_len = 0; #endif /* if defined( MCUBOOT_SIGN_RSA ) */ + diff --git a/examples/evkbmimxrt1060/pubsub/demo_restrictions.c b/examples/evkbmimxrt1060/pubsub/demo_restrictions.c new file mode 100644 index 0000000..70391dc --- /dev/null +++ b/examples/evkbmimxrt1060/pubsub/demo_restrictions.c @@ -0,0 +1,362 @@ +/* + * FreeRTOS version 202012.00-LTS + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + /** + * @brief Demonstration of Memory Protection Unit functionalities. + * Demo creates two restricted tasks read-only task and and a read write task. + * To find more about create restricted task API, see: https://www.freertos.org/xTaskCreateRestricted.html. + * Read-only task has read only access to a shared memory region, while Read-Write task has both read and write + * access to it. Read-only task sets a global flag to one and then try to write to the shared memory region, which generates + * hard fault by MPU. The hard fault handler implemented in this demo handles the exception gracefully by setting the global + * flag back to zero and skipping to the next instruction in the task. The read only task verifies that flag is reset to zero to confirm + * that the memory fault was raised and handled gracefully. + */ + + /* FreeRTOS include. */ +#include "FreeRTOS.h" + +/* Task API include. */ +#include "task.h" + +/* Contains PRINTF APIs. */ +#include "fsl_debug_console.h" + +/** + * @brief Flag to enable or disable memory fault injection. + * To enable, set the flag to 1. Enabling this will cause the read-only task to write to a shared memory region + * thereby causing a hard fault. + */ +#define INJECT_TEST_MEMORY_FAULT ( 0 ) + + /** + * @brief Size of the shared memory between the restricted tasks. + */ +#define SHARED_MEMORY_SIZE 32 + + /** + * @brief Size of the memory region used by the Read only task and hard fault handler. + */ +#define MIN_REGION_SIZE 32 + + /** + * @brief Stack size of the restricted tasks. + */ +#define RESTRICTED_TASK_STACK_SIZE 128 + + /* + * @brief Macro to override printf funtion to run it in privileged mode. + * NXP PRINTF code resides somewhere in RAM that could be provided as accessible region, but it's simpler to + * just run it as privileged */ +#define MPU_PRINTF( ... ) \ + { \ + BaseType_t xRunningPrivileged = xPortRaisePrivilege(); \ + PRINTF( __VA_ARGS__ ); \ + vPortResetPrivilege( xRunningPrivileged ); \ + } + + + /* For readability. Read about Hardfault Entry in ARMv7 docs for more details */ +typedef struct +{ + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr; + uint32_t return_address; + uint32_t xPSR; +} HardFaultStack_t; + + +/** + * @brief Calls the port specific code to raise the privilege. + * + * @return pdFALSE if privilege was raised, pdTRUE otherwise. + */ +extern BaseType_t xPortRaisePrivilege(void); + +/** + * @brief Calls the port specific code to reset the privilege. + * If xRunningPrivileged is pdFALSE, calls the port specific + * code to reset the privilege, otherwise does nothing. + * + * @param[in] xRunningPrivileged Whether running in privelged mode or not. + */ +extern void vPortResetPrivilege(BaseType_t xRunningPrivileged); + +/** + * @brief Function used to dump the MPU memory regions allocated by linker script. + */ +void printRegions(void); + +/** + * @brief The Read write restricted task. + * Task loops and keeps writing to the shared memory region. Since task has both read and write access it should + * not cause a memory fault. + * + * @param[in] pvParameters Parameters to the task. + */ +static void prvRWAccessTask(void* pvParameters); + +/** + * @brief The read only task + * Task loops and reads from the shared memory region. If INJECT_TEST_MEMORY_FAULT is set to 1, task also writes to + * shared memory region. Using hard fault handler it recovers from the hard fault and prints the memory access violation + * to the console. + * + * @param[in] pvParameters Parameters to the task. + */ +static void prvROAccessTask(void* pvParameters); + +/** + * @brief Memory regions used by the linker script. + */ +extern uint32_t __privileged_functions_start__[]; +extern uint32_t __privileged_functions_end__[]; +extern uint32_t __FLASH_segment_start__[]; +extern uint32_t __FLASH_segment_end__[]; +extern uint32_t __privileged_data_start__[]; +extern uint32_t __privileged_data_end__[]; +extern uint32_t __syscalls_flash_start__[]; +extern uint32_t __syscalls_flash_end__[]; +extern uint32_t __SRAM_segment_start__[]; +extern uint32_t __SRAM_segment_end__[]; + + +/** + * @brief Shared memory area used between the restricted tasks. + */ +static uint8_t ucSharedMemory[SHARED_MEMORY_SIZE] __attribute__((aligned(SHARED_MEMORY_SIZE))); + +/** + * @brief Statically allocated stack for Read-write access restristed task. + */ +static StackType_t xRWAccessTaskStack[RESTRICTED_TASK_STACK_SIZE] __attribute__((aligned(RESTRICTED_TASK_STACK_SIZE * sizeof(StackType_t)))); + +/* + * @brief The memory region shared between Read only task and hard fault handler. + * + * This is how RO task communicates to handler that it intentionally memory faulted. + * Note, handlers run priviliged thus will have access) + * Also note, 32B is minimum valid size for region*/ +static volatile uint8_t ucROTaskFaultTracker[MIN_REGION_SIZE] __attribute__((aligned(MIN_REGION_SIZE))) = { 0 }; + +/** + * @brief Statically allocated stack for Read-only access restristed task. + */ +static StackType_t xROAccessTaskStack[RESTRICTED_TASK_STACK_SIZE] __attribute__((aligned(RESTRICTED_TASK_STACK_SIZE * sizeof(StackType_t)))); + +/* ------------------------------------------------------------------------------- */ + +void printRegions(void) +{ + uint32_t* tmp = NULL; + + tmp = __privileged_functions_start__; + tmp = __privileged_functions_end__; + tmp = __FLASH_segment_start__; + tmp = __FLASH_segment_end__; + tmp = __privileged_data_start__; + tmp = __privileged_data_end__; + + (void)tmp; + + PRINTF("\r\n"); + PRINTF("privileged functions: %08x - %08x\r\n", __privileged_functions_start__, __privileged_functions_end__); + PRINTF("privileged data: %08x - %08x\r\n", __privileged_data_start__, __privileged_data_end__); + PRINTF("system calls: %08x - %08x\r\n", __syscalls_flash_start__, __syscalls_flash_end__); + PRINTF("flash segment: %08x - %08x\r\n", __FLASH_segment_start__, __FLASH_segment_end__); + PRINTF("sram segment: %08x - %08x\r\n", __SRAM_segment_start__, __SRAM_segment_end__); + PRINTF("\r\n"); +} + +static void prvRWAccessTask(void* pvParameters) +{ + /* Unused parameters. */ + (void)pvParameters; + + ucSharedMemory[0] = 0; + + while (1) + { + ucSharedMemory[0] = 1; + MPU_PRINTF("Ran RW task\r\n"); + + vTaskDelay(pdMS_TO_TICKS(8000)); + } +} + +static void prvROAccessTask(void* pvParameters) +{ + uint8_t ucVal; + + /* Unused parameters. */ + (void)pvParameters; + ucROTaskFaultTracker[0] = 0; + + for (; ; ) + { + /* This task has RO access to ucSharedMemory and therefore it can read + * it but cannot modify it. */ + ucVal = ucSharedMemory[0]; + + /* Silent compiler warnings about unused variables. */ + (void)ucVal; + +#if ( INJECT_TEST_MEMORY_FAULT == 1 ) + ucROTaskFaultTracker[0] = 1; + + MPU_PRINTF("Triggering memory violation...\r\n"); + + /* Illegal access to generate Memory Fault. */ + ucSharedMemory[0] = 0; + + /* Ensure that the above line did generate MemFault and the fault + * handler did clear the ucROTaskFaultTracker[ 0 ]. */ + if (ucROTaskFaultTracker[0] == 0) + { + MPU_PRINTF("Access Violation handled.\r\n"); + } + else + { + MPU_PRINTF("Error: Access violation should have triggered a fault\r\n"); + } +#endif /* ifdef INJECT_TEST_MEMORY_FAULT */ + MPU_PRINTF("Ran RO task\r\n"); + + vTaskDelay(pdMS_TO_TICKS(5000)); + } +} + +void xCreateRestrictedTasks(BaseType_t xPriority) +{ + /* Create restricted tasks */ + TaskParameters_t xRWAccessTaskParameters = + { + .pvTaskCode = prvRWAccessTask, + .pcName = "RWAccess", + .usStackDepth = RESTRICTED_TASK_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = xPriority, + .puxStackBuffer = xRWAccessTaskStack, + .xRegions = + { + { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER }, + { 0, 0, 0 }, + { 0, 0, 0 }, + } + }; + + xTaskCreateRestricted(&(xRWAccessTaskParameters), NULL); + + TaskParameters_t xROAccessTaskParameters = + { + .pvTaskCode = prvROAccessTask, + .pcName = "ROAccess", + .usStackDepth = RESTRICTED_TASK_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = xPriority, + .puxStackBuffer = xROAccessTaskStack, + .xRegions = + { + { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER }, + { (void*)ucROTaskFaultTracker, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER }, + { 0, 0, 0 } + /*{ 0x20000500, 0x100, portMPU_REGION_READ_WRITE }, */ + } + }; + xTaskCreateRestricted(&(xROAccessTaskParameters), NULL); +} + + +/* ------------------------------------------------------------------------------- */ + +/** + * @brief The hard fault handler defined by the demo. + * Function takes in hardfaulted stack address, finds out the next instructions to skip to, + * resets the shared flag to zero for read-only task and then skips the stack pointer to the next + * instruction to be executed. + */ +portDONT_DISCARD void vHandleMemoryFault(uint32_t* pulFaultStackAddress) +{ + uint32_t ulPC; + uint16_t usOffendingInstruction; + + HardFaultStack_t* const xFaultStack = (HardFaultStack_t*)pulFaultStackAddress; + + /* Read program counter. */ + ulPC = xFaultStack->return_address; + + if (ucROTaskFaultTracker[0] == 1) + { + /* Read the offending instruction. */ + usOffendingInstruction = *(uint16_t*)ulPC; + + /* From ARM docs: + * If the value of bits[15:11] of the halfword being decoded is one of + * the following, the halfword is the first halfword of a 32-bit + * instruction: + * - 0b11101. + * - 0b11110. + * - 0b11111. + * Otherwise, the halfword is a 16-bit instruction. + */ + + /* Extract bits[15:11] of the offending instruction. */ + usOffendingInstruction = usOffendingInstruction & 0xF800; + usOffendingInstruction = (usOffendingInstruction >> 11); + + /* Increment to next instruction, depending on current instruction size (32-bit or 16-bit) */ + if ((usOffendingInstruction == 0x001F) || + (usOffendingInstruction == 0x001E) || + (usOffendingInstruction == 0x001D)) + { + ulPC += 4; + } + else + { + ulPC += 2; + } + + /* Indicate to RO task its expected fault was handled */ + ucROTaskFaultTracker[0] = 0; + + /* Resume execution after offending instruction from RO task */ + xFaultStack->return_address = ulPC; + + PRINTF("Expected memory violation caught by handler...\r\n", ulPC); + } + else + { + PRINTF("Memory Access Violation. Inst @ %x\r\n", ulPC); + + while (1) + { + } + } +} diff --git a/examples/evkbmimxrt1060/pubsub/demo_restrictions.h b/examples/evkbmimxrt1060/pubsub/demo_restrictions.h new file mode 100644 index 0000000..1f5cce2 --- /dev/null +++ b/examples/evkbmimxrt1060/pubsub/demo_restrictions.h @@ -0,0 +1,44 @@ +/* + * FreeRTOS version 202012.00-LTS + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @brief Header file contains APIs to demonstrate MPU functionalities. + */ + +#ifndef USER_DEMO_RESTRICTIONS_H_ +#define USER_DEMO_RESTRICTIONS_H_ + +/** + * @brief Demo function to create restricted tasks given priority. + * Function creates a read-only task and read-write task to demonstrate the MPU + * functionalities with FreeRTOS tasks. + * + * @param[in] xPriority Priority of the restricted tasks. + */ +void xCreateRestrictedTasks( BaseType_t xPriority ); + +#endif /* USER_DEMO_RESTRICTIONS_H_ */ \ No newline at end of file diff --git a/examples/evkbmimxrt1060/sesip/Demo.ld b/examples/evkbmimxrt1060/sesip/Demo.ld new file mode 100644 index 0000000..9897945 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/Demo.ld @@ -0,0 +1,47 @@ +/* + * GENERATED FILE - DO NOT EDIT + * Copyright (c) 2008-2013 Code Red Technologies Ltd, + * Copyright 2015, 2018-2019 NXP + * (c) NXP Semiconductors 2013-2023 + * Generated linker script file for MIMXRT1062xxxxA + * Created from memory.ldt by FMCreateLinkMemory + * Using Freemarker v2.3.30 + * MCUXpresso IDE v11.6.1 [Build 8255] [2022-10-03] on Jan 26, 2023, 5:09:16 PM + */ + +MEMORY +{ + /* Define each memory region */ + BOARD_FLASH (rx) : ORIGIN = 0x60040400, LENGTH = 0x1ffc00 /* 2047K bytes (alias Flash) */ + SRAM_DTC (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */ + SRAM_ITC (rwx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias RAM2) */ + SRAM_OC (rwx) : ORIGIN = 0x20200000, LENGTH = 0xc0000 /* 768K bytes (alias RAM3) */ + BOARD_SDRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 0x1e00000 /* 30M bytes (alias RAM4) */ + NCACHE_REGION (rwx) : ORIGIN = 0x81e00000, LENGTH = 0x200000 /* 2M bytes (alias RAM5) */ +} + + /* Define a symbol for the top of each memory region */ + __base_BOARD_FLASH = 0x60040400 ; /* BOARD_FLASH */ + __base_Flash = 0x60040400 ; /* Flash */ + __top_BOARD_FLASH = 0x60040400 + 0x1ffc00 ; /* 2047K bytes */ + __top_Flash = 0x60040400 + 0x1ffc00 ; /* 2047K bytes */ + __base_SRAM_DTC = 0x20000000 ; /* SRAM_DTC */ + __base_RAM = 0x20000000 ; /* RAM */ + __top_SRAM_DTC = 0x20000000 + 0x20000 ; /* 128K bytes */ + __top_RAM = 0x20000000 + 0x20000 ; /* 128K bytes */ + __base_SRAM_ITC = 0x0 ; /* SRAM_ITC */ + __base_RAM2 = 0x0 ; /* RAM2 */ + __top_SRAM_ITC = 0x0 + 0x20000 ; /* 128K bytes */ + __top_RAM2 = 0x0 + 0x20000 ; /* 128K bytes */ + __base_SRAM_OC = 0x20200000 ; /* SRAM_OC */ + __base_RAM3 = 0x20200000 ; /* RAM3 */ + __top_SRAM_OC = 0x20200000 + 0xc0000 ; /* 768K bytes */ + __top_RAM3 = 0x20200000 + 0xc0000 ; /* 768K bytes */ + __base_BOARD_SDRAM = 0x80000000 ; /* BOARD_SDRAM */ + __base_RAM4 = 0x80000000 ; /* RAM4 */ + __top_BOARD_SDRAM = 0x80000000 + 0x1e00000 ; /* 30M bytes */ + __top_RAM4 = 0x80000000 + 0x1e00000 ; /* 30M bytes */ + __base_NCACHE_REGION = 0x81e00000 ; /* NCACHE_REGION */ + __base_RAM5 = 0x81e00000 ; /* RAM5 */ + __top_NCACHE_REGION = 0x81e00000 + 0x200000 ; /* 2M bytes */ + __top_RAM5 = 0x81e00000 + 0x200000 ; /* 2M bytes */ diff --git a/examples/evkbmimxrt1060/sesip/README.md b/examples/evkbmimxrt1060/sesip/README.md new file mode 100644 index 0000000..1452200 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/README.md @@ -0,0 +1,107 @@ +## MQTT Publish Subscribe Demo + +### Introduction +This example demonstrates multiple MQTT publish subscribe task running concurrently with Over-The-Air firmware update background task, using coreMQTT agent libary to manage the thread safety for the MQTT connection.Each publish subscribe task runs in a loop to publish a message to AWS IoT MQTT broker on a topic, and receive same message back by subscribing to the publish topic. Topics are constructed per device and per task for this demo. You can view the number of messages published by each task by logging to AWS IoT console and subscribing to respective topics. +OTA firmware update task runs OTA Agent loop which polls for and subscribes to OTA job requests from AWS IoT OTA service. The OTA agent task receives firmware chunks and sends control packets over MQTT, concurrently using coreMQTT agent task for thread safety. + +### Hardware requirements + +- Mini/micro USB cable +- MIMXRT1060-EVKB board +- OM-SE050ARD Development kit +- Personal Computer with Windows platform +- Network cable RJ45 standard (Network with Internet access) + +### Toolchain Requirements + +- MCUXpresso IDE +- python3 and pip +- openssl + +### Board Setup + +1. Plug in the OM-SE050ARD development kit to arduino headers on the MIMXRT1060-EVKB board. +3. Connect the USB cable between the personal computer and open SDA USB port (J1) on the board. +2. Connect the RJ45 cable to the ethernet port. + +### Preparing the demo + +#### Setting up the bootloader project + +The demo contains firmware over the air updates functionality for which the secure bootloader is required. To setup, build and flash bootloader project see the [README](https://github.com/FreeRTOS/lab-iot-reference-nxp-rt1060/tree/main/examples/evkbmimxrt1060/bootloader/README.md). + +#### Setting up the demo project + +1. Open the MCUXpresso IDE and choose a workspace location in your filesystem. +2. Click on `File` then `Open Projects from the FileSystem`. Choose the project from folder `projects/evkmimxrt1060/pubsub`. Import the project into the workspace. +3. Build and flash the demo from the IDE. +4. The project is configured to flash the demo to an address known to the bootloader. To boot a new application image from IDE, we have to jump start the application from the debugger. To do so: + a. Launch the application as normal from the debugger IDE. The debugger goes into an endless loop after flashing the image. + b. Pause the debugger. Go to `Debugger Console` in the bottom pane and type `jump ResetISR` to jump to application starting address. From then, application execution can be continued normally. + +### Provisioning the board + +The project requires a one time setup of MQTT broker endpoint and device credentials required for connecting to AWS IoT core, and also the thing name by which the device is registered with AWS IoT. + +1. By default the project boots into a provision mode at startup where all the configuration can be setup. The provisioning mode can be controlled using the flag `appmainPROVISIONING_MODE` in `examples/evkbmimxrt1060/pubsub/app_main.c`. +2. The provisioning mode waits for user input commands from a CLI task. +3. Connect to the USB port using a serial terminal of the choice. +4. Run the following command to get the pre-provisioned X.509 certificate from secure element: +``` +pki get cert sss:F0000001 +``` +`sss:F0000001` is the slot where the certificate is stored in secure element. + +5. Copy the PEM certificate from console and register the certificate with AWS IoT without a CA using doc [here](https://docs.aws.amazon.com/iot/latest/developerguide/manual-cert-registration.html#manual-cert-registration-console-noca). + +6. Get the AWS IoT MQTT broker endpoint from `Settings` tab in AWS IoT console. Provision the endpoint by executing the following command: +``` +conf set mqtt_endpoint +``` +7. Create a new thing, device policy in AWS as mentioned in the doc [here](https://docs.aws.amazon.com/iot/latest/developerguide/create-iot-resources.html). Attach the certificate registered in step 5 with the thing name. Provision the new thing name to the device: +``` +conf set thing_name +``` +8. Once the configurations are setup turn off the provisioning mode by setting `appmainPROVISIONING_MODE` to `0` and then recompiling and flashing the image onto the board. + +### Runnning the publish subscribe demo + +The board should be successfully provisioned at this time. Provisioning mode should be turned off by seting `appmainPROVISIONING_MODE` to `0` in `examples/evkbmimxrt1060/pubsub/app_main.c`. Demo on startup, establishes a TLS connection with AWS IoT MQTT broker and runs the publish subscribe demo tasks using coreMQTT agent. By default two pubsub task are created. You can adjust the number of tasks created by setting the config `appmainMQTT_NUM_PUBSUB_TASKS` in `examples/evkbmimxrt1060/pubsub/app_main.c` to respective value. + +### Perform Firmware Over-The-Air Updates with AWS IoT + +The demo leverages OTA client library and AWS IoT OTA service for code signing and secure download of firmware updates. Safe and secure boot process along with root of trust verification is performed using opensource MCUBoot secondary bootloader. As a pre-requisite you should have built and flash the bootloader project from this repository. + +#### Setup +This is a one time setup required for performing OTA firmware updates. + +1. Setup AWS IoT OTA service resources as mentioned in pre-requisites doc [here](https://docs.aws.amazon.com/freertos/latest/userguide/ota-prereqs.html). +2. Create ECDSA credentials to perform code signing verification by the OTA library. You can refer to the doc [here](https://docs.aws.amazon.com/freertos/latest/userguide/ota-code-sign-cert-win.html) on how to create the credentials and register a new code signing profile in your AWS account. +3. Provision the code signining public key to the board using the steps below. + 1. Get the ECDSA public key from the code signing credentials generated in step 2: + ``` + openssl ec -in ecdsasigner.key -pubout -outform PEM -out ecdsasigner-pub-key.pem + ``` + 2. Switch to device provisioning mode by setting `appmainPROVISIONING_MODE` to `1`, recompiling and downloading the firmware. + 3. On the terminal CLI prompt, run the following command: + ``` + pki set pub_key sss:00223344 + ``` + 4. CLI waits to input the public key. Copy the PEM public key created in above step and paste it to serial terminal. Press `Enter`. + 5. On successful provisioning, the CLI should print `OK`. At this point you can switch back to device normal mode by turning off `appmainPROVISIONING_MODE` flag. + +#### Creating a new firmware update job + +1. Go to `examples/common/ota/ota_update.c` and increment the version number `APP_VERSION_MAJOR` for the new image. +2. Build the new image. +3. Sign the new binary image using MCUBoot key-pair generated as part of setting up the bootloader project. From the repository root folder execute following command: +``` +python3 Middleware/mcuboot/scripts/imgtool.py sign -k examples/evkbmimxrt1060/bootloader/keys/ --align 4 --header-size 0x400 --pad-header --slot-size 0x200000 --max-sectors 800 --version "1.0" projects/evkmimxrt1060/pubsub/Debug/aws_iot_pubsub.bin aws_iot_pubsub_signed.bin +``` +This should create a new signed MCUboot image named `aws_iot_pubsub_signed.bin` + +4. Create a firmware update job using the signed image following the steps [here](https://docs.aws.amazon.com/freertos/latest/userguide/ota-console-workflow.html). +5. Once the job is create successfully, the demo should start downloading the firmware chunks. The process can be monitored using logs from the console. + +#### Verification and Bootup of new Image +Once all the firmware image chunks are downloaded and the signature is validated, the demo resets by itself. MCUBoot loader verifies the new image using the signing public key created as part of bootloader project. Once the image is verified, the bootloader swaps the image and boots up the new image. The new image on booting up verifies the image version with AWS IoT and marks the job as completed successfully. diff --git a/examples/evkbmimxrt1060/sesip/app_main.c b/examples/evkbmimxrt1060/sesip/app_main.c new file mode 100644 index 0000000..6a3d7e0 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/app_main.c @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + */ + + +/** + * @brief Contains the application main function which spawns different demo tasks + * included in the project. + */ + +#include "FreeRTOS.h" +#include "task.h" + +/** + * @brief Flag which enables OTA update task in background along with other demo tasks. + * OTA update task polls regularly for firmware update jobs or acts on a new firmware update + * available notification from OTA service. + */ +#define appmainINCLUDE_OTA_UPDATE_TASK ( 1 ) + +/** + * @brief Flag to enable or disable provisioning mode for the demo. + * Enabling the flags starts a CLI task, so that user can perform provisioning of the device through + * a serial terminal. Provisioning involves running commands to fetch or set the PKI and configuration + * information for the device to connect to broker and perform OTA updates. Disabling the flag results + * in disabling the CLI task and execution of the demo tasks in normal device operation mode. + */ +#define appmainPROVISIONING_MODE ( 1 ) + +/** + * @brief Subscribe Publish demo tasks configuration. + * Subscribe publish demo task shows the basic functionality of connecting to an MQTT broker, subscribing + * to a topic, publishing messages to a topic and reporting the incoming messages on subscribed topic. + * Number of subscribe publish demo tasks to be spawned is configurable. + */ +#define appmainMQTT_NUM_PUBSUB_TASKS ( 2 ) +#define appmainMQTT_PUBSUB_TASK_STACK_SIZE ( 2048 ) +#define appmainMQTT_PUBSUB_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/** + * @brief Stack size and priority for OTA Update task. + */ +#define appmainMQTT_OTA_UPDATE_TASK_STACK_SIZE ( 4096 ) +#define appmainMQTT_OTA_UPDATE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/** + * @brief Stack size and priority for MQTT agent task. + * Stack size is capped to an adequate value based on requirements from MbedTLS stack + * for establishing a TLS connection. Task priority of MQTT agent is set to a priority + * higher than other MQTT application tasks, so that the agent can drain the queue + * as work is being produced. + */ +#define appmainMQTT_AGENT_TASK_STACK_SIZE ( 6144 ) +#define appmainMQTT_AGENT_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) + +/** + * @brief Stack size and priority for CLI task. + */ +#define appmainCLI_TASK_STACK_SIZE ( 6144 ) +#define appmainCLI_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +extern void vSimpleSubscribePublishTask( void * pvParameters ); + +extern void vOTAUpdateTask( void * pvParam ); + +extern void vCLITask( void * pvParam ); + +extern BaseType_t xStartSimplePubSubTasks( uint32_t ulNumPubsubTasks, + configSTACK_DEPTH_TYPE uxStackSize, + UBaseType_t uxPriority ); + +int app_main( void ) +{ + BaseType_t xResult = pdFAIL; + + xResult = KVStore_init(); + + if( xResult == pdFAIL ) + { + configPRINTF( ( "Failed to initialize key value configuration store.\r\n" ) ); + } + +#if ( appmainPROVISIONING_MODE == 1 ) + { + if( xResult == pdPASS ) + { + xResult = xTaskCreate( vCLITask, + "CLI", + appmainCLI_TASK_STACK_SIZE, + NULL, + appmainCLI_TASK_PRIORITY, + NULL ); + } + } +#else /* if ( appmainPROVISIONING_MODE == 1 ) */ + { + if( xResult == pdPASS ) + { + xResult = xMQTTAgentInit( appmainMQTT_AGENT_TASK_STACK_SIZE, appmainMQTT_AGENT_TASK_PRIORITY ); + } + +#if ( appmainINCLUDE_OTA_UPDATE_TASK == 1 ) + { + if( xResult == pdPASS ) + { + xResult = xTaskCreate( vOTAUpdateTask, + "OTA", + appmainMQTT_OTA_UPDATE_TASK_STACK_SIZE, + NULL, + appmainMQTT_OTA_UPDATE_TASK_PRIORITY, + NULL ); + } + } +#endif /* if ( appmainINCLUDE_OTA_AGENT == 1 ) */ + + if( xResult == pdPASS ) + { + xResult = xStartSimplePubSubTasks( appmainMQTT_NUM_PUBSUB_TASKS, + appmainMQTT_PUBSUB_TASK_STACK_SIZE, + appmainMQTT_PUBSUB_TASK_PRIORITY ); + } + } +#endif /* if ( appmainPROVISIONING_MODE == 1 ) */ + + return pdPASS; +} diff --git a/examples/evkbmimxrt1060/sesip/board/board.c b/examples/evkbmimxrt1060/sesip/board/board.c new file mode 100644 index 0000000..ed6a2d6 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/board.c @@ -0,0 +1,416 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "board.h" +#if defined( SDK_I2C_BASED_COMPONENT_USED ) && SDK_I2C_BASED_COMPONENT_USED +#include "fsl_lpi2c.h" +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get debug console frequency. */ +uint32_t BOARD_DebugConsoleSrcFreq( void ) +{ + uint32_t freq; + + /* To make it simple, we assume default PLL and divider settings, and the only variable + * from application is use PLL3 source or OSC source */ + if( CLOCK_GetMux( kCLOCK_UartMux ) == 0 ) /* PLL3 div6 80M */ + { + freq = ( CLOCK_GetPllFreq( kCLOCK_PllUsb1 ) / 6U ) / ( CLOCK_GetDiv( kCLOCK_UartDiv ) + 1U ); + } + else + { + freq = CLOCK_GetOscFreq() / ( CLOCK_GetDiv( kCLOCK_UartDiv ) + 1U ); + } + + return freq; +} + +/* Initialize debug console. */ +void BOARD_InitDebugConsole( void ) +{ + uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq(); + + DbgConsole_Init( BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq ); +} + +#if defined( SDK_I2C_BASED_COMPONENT_USED ) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_LPI2C_Init( LPI2C_Type * base, + uint32_t clkSrc_Hz ) +{ + lpi2c_master_config_t lpi2cConfig = { 0 }; + + /* + * lpi2cConfig.debugEnable = false; + * lpi2cConfig.ignoreAck = false; + * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; + * lpi2cConfig.baudRate_Hz = 100000U; + * lpi2cConfig.busIdleTimeout_ns = 0; + * lpi2cConfig.pinLowTimeout_ns = 0; + * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; + * lpi2cConfig.sclGlitchFilterWidth_ns = 0; + */ + LPI2C_MasterGetDefaultConfig( &lpi2cConfig ); + LPI2C_MasterInit( base, &lpi2cConfig, clkSrc_Hz ); +} + +status_t BOARD_LPI2C_Send( LPI2C_Type * base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t * txBuff, + uint8_t txBuffSize ) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = txBuff; + xfer.dataSize = txBuffSize; + + return LPI2C_MasterTransferBlocking( base, &xfer ); +} + +status_t BOARD_LPI2C_Receive( LPI2C_Type * base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t * rxBuff, + uint8_t rxBuffSize ) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Read; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + return LPI2C_MasterTransferBlocking( base, &xfer ); +} + +status_t BOARD_LPI2C_SendSCCB( LPI2C_Type * base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t * txBuff, + uint8_t txBuffSize ) +{ + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = txBuff; + xfer.dataSize = txBuffSize; + + return LPI2C_MasterTransferBlocking( base, &xfer ); +} + +status_t BOARD_LPI2C_ReceiveSCCB( LPI2C_Type * base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t * rxBuff, + uint8_t rxBuffSize ) +{ + status_t status; + lpi2c_master_transfer_t xfer; + + xfer.flags = kLPI2C_TransferDefaultFlag; + xfer.slaveAddress = deviceAddress; + xfer.direction = kLPI2C_Write; + xfer.subaddress = subAddress; + xfer.subaddressSize = subAddressSize; + xfer.data = NULL; + xfer.dataSize = 0; + + status = LPI2C_MasterTransferBlocking( base, &xfer ); + + if( kStatus_Success == status ) + { + xfer.subaddressSize = 0; + xfer.direction = kLPI2C_Read; + xfer.data = rxBuff; + xfer.dataSize = rxBuffSize; + + status = LPI2C_MasterTransferBlocking( base, &xfer ); + } + + return status; +} + +void BOARD_Accel_I2C_Init( void ) +{ + BOARD_LPI2C_Init( BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ ); +} + +status_t BOARD_Accel_I2C_Send( uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint32_t txBuff ) +{ + uint8_t data = ( uint8_t ) txBuff; + + return BOARD_LPI2C_Send( BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1 ); +} + +status_t BOARD_Accel_I2C_Receive( uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t * rxBuff, + uint8_t rxBuffSize ) +{ + return BOARD_LPI2C_Receive( BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize ); +} + +void BOARD_Codec_I2C_Init( void ) +{ + BOARD_LPI2C_Init( BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ ); +} + +status_t BOARD_Codec_I2C_Send( uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + const uint8_t * txBuff, + uint8_t txBuffSize ) +{ + return BOARD_LPI2C_Send( BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, ( uint8_t * ) txBuff, + txBuffSize ); +} + +status_t BOARD_Codec_I2C_Receive( uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t * rxBuff, + uint8_t rxBuffSize ) +{ + return BOARD_LPI2C_Receive( BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize ); +} + +void BOARD_Camera_I2C_Init( void ) +{ + CLOCK_SetMux( kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT ); + CLOCK_SetDiv( kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER ); + BOARD_LPI2C_Init( BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ ); +} + +status_t BOARD_Camera_I2C_Send( uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + const uint8_t * txBuff, + uint8_t txBuffSize ) +{ + return BOARD_LPI2C_Send( BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, ( uint8_t * ) txBuff, + txBuffSize ); +} + +status_t BOARD_Camera_I2C_Receive( uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t * rxBuff, + uint8_t rxBuffSize ) +{ + return BOARD_LPI2C_Receive( BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, + rxBuffSize ); +} + +status_t BOARD_Camera_I2C_SendSCCB( uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + const uint8_t * txBuff, + uint8_t txBuffSize ) +{ + return BOARD_LPI2C_SendSCCB( BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, ( uint8_t * ) txBuff, + txBuffSize ); +} + +status_t BOARD_Camera_I2C_ReceiveSCCB( uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t * rxBuff, + uint8_t rxBuffSize ) +{ + return BOARD_LPI2C_ReceiveSCCB( BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, + rxBuffSize ); +} +#endif /* SDK_I2C_BASED_COMPONENT_USED */ + +/* MPU configuration. */ +void BOARD_ConfigMPU( void ) +{ +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = ( uint32_t ) Image$$RW_m_ncache$$Base; + uint32_t size = ( ( uint32_t ) Image$$RW_m_ncache_unused$$Base == nonCacheStart ) ? + 0 : + ( ( uint32_t ) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart ); +#elif defined( __MCUXPRESSO ) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = ( uint32_t ) ( &__base_NCACHE_REGION ); + uint32_t size = ( uint32_t ) ( &__top_NCACHE_REGION ) - nonCacheStart; +#elif defined( __ICCARM__ ) || defined( __GNUC__ ) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = ( uint32_t ) __NCACHE_REGION_START; + uint32_t size = ( uint32_t ) __NCACHE_REGION_SIZE; +#endif /* if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) */ + volatile uint32_t i = 0; + + /* Disable I cache and D cache */ + if( SCB_CCR_IC_Msk == ( SCB_CCR_IC_Msk & SCB->CCR ) ) + { + SCB_DisableICache(); + } + + if( SCB_CCR_DC_Msk == ( SCB_CCR_DC_Msk & SCB->CCR ) ) + { + SCB_DisableDCache(); + } + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read allocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read allocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outter cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * mpu_armv7.h. + */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + * + */ + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR( 0, 0x00000000U ); + MPU->RASR = ARM_MPU_RASR( 1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB ); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR( 1, 0x80000000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB ); + + /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR( 2, 0x60000000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB ); + +#if defined( XIP_EXTERNAL_FLASH ) && ( XIP_EXTERNAL_FLASH == 1 ) + /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR( 3, 0x60000000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB ); +#endif + + /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR( 4, 0x00000000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB ); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR( 5, 0x00000000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB ); + + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR( 6, 0x20000000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB ); + + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR( 7, 0x20200000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB ); + + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR( 8, 0x20280000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB ); + + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR( 9, 0x80000000U ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB ); + + while( ( size >> i ) > 0x1U ) + { + i++; + } + + if( i != 0 ) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert( !( nonCacheStart % size ) ); + assert( size == ( uint32_t ) ( 1 << i ) ); + assert( i >= 5 ); + + /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR( 10, nonCacheStart ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1 ); + } + + /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR( 11, 0x40000000 ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB ); + + /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR( 12, 0x42000000 ); + MPU->RASR = ARM_MPU_RASR( 0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB ); + + /* Enable MPU */ + ARM_MPU_Enable( MPU_CTRL_PRIVDEFENA_Msk ); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} diff --git a/examples/evkbmimxrt1060/sesip/board/board.h b/examples/evkbmimxrt1060/sesip/board/board.h new file mode 100644 index 0000000..89e7464 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/board.h @@ -0,0 +1,218 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMXRT1060-EVK" + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR ( uint32_t ) LPUART1 +#define BOARD_DEBUG_UART_INSTANCE 1U + +#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() + +#define BOARD_UART_IRQ LPUART1_IRQn +#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE ( 115200U ) +#endif /* BOARD_DEBUG_UART_BAUDRATE */ + +/*! @brief The USER_LED used for board */ +#define LOGIC_LED_ON ( 0U ) +#define LOGIC_LED_OFF ( 1U ) +#ifndef BOARD_USER_LED_GPIO +#define BOARD_USER_LED_GPIO GPIO1 +#endif +#ifndef BOARD_USER_LED_GPIO_PIN +#define BOARD_USER_LED_GPIO_PIN ( 9U ) +#endif + +#define USER_LED_INIT( output ) \ + GPIO_PinWrite( BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output ); \ + BOARD_USER_LED_GPIO->GDIR |= ( 1U << BOARD_USER_LED_GPIO_PIN ) /*!< Enable target USER_LED */ +#define USER_LED_ON() \ + GPIO_PortClear( BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN ) /*!< Turn off target USER_LED */ +#define USER_LED_OFF() GPIO_PortSet( BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN ) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq( 24000000U ); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk( 0 ); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc( kCLOCK_XtalOsc ); + /* Set Oscillator ready counter value. */ + CCM->CCR = ( CCM->CCR & ( ~CCM_CCR_OSCNT_MASK ) ) | CCM_CCR_OSCNT( 127 ); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux( kCLOCK_PeriphClk2Mux, 1 ); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux( kCLOCK_PeriphMux, 1 ); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = ( DCDC->REG3 & ( ~DCDC_REG3_TRG_MASK ) ) | DCDC_REG3_TRG( 0x13 ); + + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while( DCDC_REG0_STS_DC_OK_MASK != ( DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0 ) ) + { + } + + /* Set AHB_PODF. */ + CLOCK_SetDiv( kCLOCK_AhbDiv, 0 ); + /* Disable IPG clock gate. */ + CLOCK_DisableClock( kCLOCK_Adc1 ); + CLOCK_DisableClock( kCLOCK_Adc2 ); + CLOCK_DisableClock( kCLOCK_Xbar1 ); + CLOCK_DisableClock( kCLOCK_Xbar2 ); + CLOCK_DisableClock( kCLOCK_Xbar3 ); + /* Set IPG_PODF. */ + CLOCK_SetDiv( kCLOCK_IpgDiv, 3 ); + /* Set ARM_PODF. */ + CLOCK_SetDiv( kCLOCK_ArmDiv, 1 ); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv( kCLOCK_PeriphClk2Div, 0 ); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock( kCLOCK_Gpt1 ); + CLOCK_DisableClock( kCLOCK_Gpt1S ); + CLOCK_DisableClock( kCLOCK_Gpt2 ); + CLOCK_DisableClock( kCLOCK_Gpt2S ); + CLOCK_DisableClock( kCLOCK_Pit ); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv( kCLOCK_PerclkDiv, 1 ); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock( kCLOCK_Usdhc1 ); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv( kCLOCK_Usdhc1Div, 1 ); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux( kCLOCK_Usdhc1Mux, 0 ); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock( kCLOCK_Usdhc2 ); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv( kCLOCK_Usdhc2Div, 1 ); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux( kCLOCK_Usdhc2Mux, 0 ); + + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock( kCLOCK_Semc ); + /* Set SEMC_PODF. */ + CLOCK_SetDiv( kCLOCK_SemcDiv, 7 ); + /* Set Semc alt clock source. */ + CLOCK_SetMux( kCLOCK_SemcAltMux, 0 ); + /* Set Semc clock source. */ + CLOCK_SetMux( kCLOCK_SemcMux, 0 ); +#endif + + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !( defined( XIP_EXTERNAL_FLASH ) && ( XIP_EXTERNAL_FLASH == 1 ) ) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock( kCLOCK_FlexSpi ); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv( kCLOCK_FlexspiDiv, 1 ); + /* Set Flexspi clock source. */ + CLOCK_SetMux( kCLOCK_FlexspiMux, 3 ); +#endif + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock( kCLOCK_FlexSpi2 ); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv( kCLOCK_Flexspi2Div, 1 ); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux( kCLOCK_Flexspi2Mux, 1 ); + /* Disable CSI clock gate. */ + CLOCK_DisableClock( kCLOCK_Csi ); + /* Set CSI_PODF. */ + CLOCK_SetDiv( kCLOCK_CsiDiv, 1 ); + /* Set Csi clock source. */ + CLOCK_SetMux( kCLOCK_CsiMux, 0 ); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock( kCLOCK_Lpspi1 ); + CLOCK_DisableClock( kCLOCK_Lpspi2 ); + CLOCK_DisableClock( kCLOCK_Lpspi3 ); + CLOCK_DisableClock( kCLOCK_Lpspi4 ); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv( kCLOCK_LpspiDiv, 4 ); + /* Set Lpspi clock source. */ + CLOCK_SetMux( kCLOCK_LpspiMux, 2 ); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock( kCLOCK_Trace ); + /* Set TRACE_PODF. */ + CLOCK_SetDiv( kCLOCK_TraceDiv, 3 ); + /* Set Trace clock source. */ + CLOCK_SetMux( kCLOCK_TraceMux, 0 ); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock( kCLOCK_Sai1 ); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv( kCLOCK_Sai1PreDiv, 3 ); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_Sai1Div, 1 ); + /* Set Sai1 clock source. */ + CLOCK_SetMux( kCLOCK_Sai1Mux, 0 ); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock( kCLOCK_Sai2 ); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv( kCLOCK_Sai2PreDiv, 3 ); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_Sai2Div, 1 ); + /* Set Sai2 clock source. */ + CLOCK_SetMux( kCLOCK_Sai2Mux, 0 ); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock( kCLOCK_Sai3 ); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv( kCLOCK_Sai3PreDiv, 3 ); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_Sai3Div, 1 ); + /* Set Sai3 clock source. */ + CLOCK_SetMux( kCLOCK_Sai3Mux, 0 ); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock( kCLOCK_Lpi2c1 ); + CLOCK_DisableClock( kCLOCK_Lpi2c2 ); + CLOCK_DisableClock( kCLOCK_Lpi2c3 ); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_Lpi2cDiv, 0 ); + /* Set Lpi2c clock source. */ + CLOCK_SetMux( kCLOCK_Lpi2cMux, 0 ); + /* Disable CAN clock gate. */ + CLOCK_DisableClock( kCLOCK_Can1 ); + CLOCK_DisableClock( kCLOCK_Can2 ); + CLOCK_DisableClock( kCLOCK_Can3 ); + CLOCK_DisableClock( kCLOCK_Can1S ); + CLOCK_DisableClock( kCLOCK_Can2S ); + CLOCK_DisableClock( kCLOCK_Can3S ); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_CanDiv, 1 ); + /* Set Can clock source. */ + CLOCK_SetMux( kCLOCK_CanMux, 2 ); + /* Disable UART clock gate. */ + CLOCK_DisableClock( kCLOCK_Lpuart1 ); + CLOCK_DisableClock( kCLOCK_Lpuart2 ); + CLOCK_DisableClock( kCLOCK_Lpuart3 ); + CLOCK_DisableClock( kCLOCK_Lpuart4 ); + CLOCK_DisableClock( kCLOCK_Lpuart5 ); + CLOCK_DisableClock( kCLOCK_Lpuart6 ); + CLOCK_DisableClock( kCLOCK_Lpuart7 ); + CLOCK_DisableClock( kCLOCK_Lpuart8 ); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_UartDiv, 0 ); + /* Set Uart clock source. */ + CLOCK_SetMux( kCLOCK_UartMux, 0 ); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock( kCLOCK_LcdPixel ); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv( kCLOCK_LcdifPreDiv, 1 ); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_LcdifDiv, 3 ); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux( kCLOCK_LcdifPreMux, 5 ); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock( kCLOCK_Spdif ); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv( kCLOCK_Spdif0PreDiv, 1 ); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_Spdif0Div, 7 ); + /* Set Spdif clock source. */ + CLOCK_SetMux( kCLOCK_SpdifMux, 3 ); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock( kCLOCK_Flexio1 ); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv( kCLOCK_Flexio1PreDiv, 1 ); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_Flexio1Div, 7 ); + /* Set Flexio1 clock source. */ + CLOCK_SetMux( kCLOCK_Flexio1Mux, 3 ); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock( kCLOCK_Flexio2 ); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv( kCLOCK_Flexio2PreDiv, 1 ); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv( kCLOCK_Flexio2Div, 7 ); + /* Set Flexio2 clock source. */ + CLOCK_SetMux( kCLOCK_Flexio2Mux, 3 ); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux( kCLOCK_Pll3SwMux, 0 ); + /* Init ARM PLL. */ + CLOCK_InitArmPll( &armPllConfig_BOARD_BootClockRUN ); + + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined( XIP_BOOT_HEADER_DCD_ENABLE ) && ( XIP_BOOT_HEADER_DCD_ENABLE == 1 ) +#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll( &sysPllConfig_BOARD_BootClockRUN ); + /* Init System pfd0. */ + CLOCK_InitSysPfd( kCLOCK_Pfd0, 27 ); + /* Init System pfd1. */ + CLOCK_InitSysPfd( kCLOCK_Pfd1, 16 ); + /* Init System pfd2. */ + CLOCK_InitSysPfd( kCLOCK_Pfd2, 24 ); + /* Init System pfd3. */ + CLOCK_InitSysPfd( kCLOCK_Pfd3, 16 ); +#endif /* ifndef SKIP_SYSCLK_INIT */ + + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !( defined( XIP_EXTERNAL_FLASH ) && ( XIP_EXTERNAL_FLASH == 1 ) ) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll( &usb1PllConfig_BOARD_BootClockRUN ); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd( kCLOCK_Pfd0, 33 ); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd( kCLOCK_Pfd1, 16 ); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd( kCLOCK_Pfd2, 17 ); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd( kCLOCK_Pfd3, 19 ); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif /* if !( defined( XIP_EXTERNAL_FLASH ) && ( XIP_EXTERNAL_FLASH == 1 ) ) */ + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass( CCM_ANALOG, kCLOCK_PllAudio, 1 ); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* Init Video PLL. */ + uint32_t pllVideo; + /* Disable Video PLL output before initial Video PLL. */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = ( CCM_ANALOG->PLL_VIDEO & ( ~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK ) ) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC( 0 ); + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A( 0 ); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B( 1 ); + pllVideo = ( CCM_ANALOG->PLL_VIDEO & ( ~( CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK ) ) ) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT( 31 ); + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT( 1 ); + CCM_ANALOG->MISC2 = ( CCM_ANALOG->MISC2 & ( ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK ) ) | CCM_ANALOG_MISC2_VIDEO_DIV( 3 ); + CCM_ANALOG->PLL_VIDEO = pllVideo; + + while( ( CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK ) == 0 ) + { + } + + /* Disable bypass for Video PLL. */ + CLOCK_SetPllBypass( CCM_ANALOG, kCLOCK_PllVideo, 0 ); + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass( CCM_ANALOG, kCLOCK_PllEnet, 1 ); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = ( CCM_ANALOG->PLL_ENET & ( ~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK ) ) | CCM_ANALOG_PLL_ENET_DIV_SELECT( 1 ); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = ( CCM_ANALOG->PLL_ENET & ( ~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK ) ) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT( 0 ); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass( CCM_ANALOG, kCLOCK_PllUsb2, 1 ); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux( kCLOCK_PrePeriphMux, 3 ); + /* Set periph clock source. */ + CLOCK_SetMux( kCLOCK_PeriphMux, 0 ); + /* Set periph clock2 clock source. */ + CLOCK_SetMux( kCLOCK_PeriphClk2Mux, 0 ); + /* Set per clock source. */ + CLOCK_SetMux( kCLOCK_PerclkMux, 0 ); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = ( CCM_ANALOG->MISC1 & ( ~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK ) ) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL( 0 ); + /* Set clock out1 divider. */ + CCM->CCOSR = ( CCM->CCOSR & ( ~CCM_CCOSR_CLKO1_DIV_MASK ) ) | CCM_CCOSR_CLKO1_DIV( 0 ); + /* Set clock out1 source. */ + CCM->CCOSR = ( CCM->CCOSR & ( ~CCM_CCOSR_CLKO1_SEL_MASK ) ) | CCM_CCOSR_CLKO1_SEL( 1 ); + /* Set clock out2 divider. */ + CCM->CCOSR = ( CCM->CCOSR & ( ~CCM_CCOSR_CLKO2_DIV_MASK ) ) | CCM_CCOSR_CLKO2_DIV( 0 ); + /* Set clock out2 source. */ + CCM->CCOSR = ( CCM->CCOSR & ( ~CCM_CCOSR_CLKO2_SEL_MASK ) ) | CCM_CCOSR_CLKO2_SEL( 18 ); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource( IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0 ); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource( IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0 ); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource( IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0 ); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource( IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0 ); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource( IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0 ); + /* Set MQS configuration. */ + IOMUXC_MQSConfig( IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0 ); + /* Set ENET1 Tx clock source. */ + IOMUXC_EnableMode( IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false ); + /* Set ENET2 Tx clock source. */ +#if defined( FSL_IOMUXC_DRIVER_VERSION ) && ( FSL_IOMUXC_DRIVER_VERSION != ( MAKE_VERSION( 2, 0, 0 ) ) ) + IOMUXC_EnableMode( IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false ); +#else + IOMUXC_EnableMode( IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false ); +#endif + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/examples/evkbmimxrt1060/sesip/board/clock_config.h b/examples/evkbmimxrt1060/sesip/board/clock_config.h new file mode 100644 index 0000000..0c64930 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/clock_config.h @@ -0,0 +1,137 @@ +/* + * Copyright 2018-2020 ,2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +/* *INDENT-OFF* */ +#if defined( __cplusplus ) +extern "C" { +#endif /* __cplusplus*/ +/* *INDENT-ON* */ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks( void ); + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) +} +#endif /* __cplusplus*/ +/* *INDENT-ON* */ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ + +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; + +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; + +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; + +/*! @brief Video PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +/* *INDENT-OFF* */ +#if defined( __cplusplus ) +extern "C" { +#endif /* __cplusplus*/ +/* *INDENT-ON* */ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN( void ); + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) +} +#endif /* __cplusplus*/ +/* *INDENT-ON* */ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/examples/evkbmimxrt1060/sesip/board/dcd.c b/examples/evkbmimxrt1060/sesip/board/dcd.c new file mode 100644 index 0000000..2971b6e --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/dcd.c @@ -0,0 +1,316 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined( XIP_BOOT_HEADER_ENABLE ) && ( XIP_BOOT_HEADER_ENABLE == 1 ) +#if defined( XIP_BOOT_HEADER_DCD_ENABLE ) && ( XIP_BOOT_HEADER_DCD_ENABLE == 1 ) +#if defined( __CC_ARM ) || defined( __ARMCC_VERSION ) || defined( __GNUC__ ) +__attribute__( ( section( ".boot_hdr.dcd_data" ), used ) ) +#elif defined( __ICCARM__ ) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* + * !!GlobalInfo + * product: DCDx V2.0 + * processor: MIMXRT1062xxxxA + * package_id: MIMXRT1062DVL6A + * mcu_data: ksdk2_0 + * processor_version: 0.0.0 + * board: MIMXRT1060-EVK + * output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = +{ + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04,0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC,0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40,0x0F, 0xC0, 0x68,0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40,0x0F, 0xC0, 0x6C,0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40,0x0F, 0xC0, 0x70,0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40,0x0F, 0xC0, 0x74,0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40,0x0F, 0xC0, 0x78,0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40,0x0F, 0xC0, 0x7C,0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40,0x0F, 0xC0, 0x80,0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40,0x0D, 0x80, 0x30,0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */ + 0x40,0x0D, 0x81, 0x00,0x00, 0x1D, 0x00, 0x00, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40,0x0F, 0xC0, 0x14,0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x14,0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x18,0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x1C,0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x20,0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x24,0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x28,0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x2C,0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x30,0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x34,0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x38,0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x3C,0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x40,0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x44,0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x48,0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x4C,0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x50,0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x54,0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x58,0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x5C,0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x60,0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x64,0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x68,0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x6C,0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x70,0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x74,0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x78,0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x7C,0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x80,0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x84,0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x88,0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x8C,0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x90,0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x94,0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x98,0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0x9C,0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0xA0,0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0xA4,0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0xA8,0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40,0x1F, 0x80, 0xAC,0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40,0x1F, 0x80, 0xB0,0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x04,0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x08,0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x0C,0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x10,0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x14,0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x18,0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x1C,0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x20,0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x24,0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x28,0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x2C,0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x30,0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x34,0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x38,0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x3C,0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x40,0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x44,0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x48,0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x4C,0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x50,0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x54,0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x58,0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x5C,0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x60,0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x64,0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x68,0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x6C,0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x70,0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x74,0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x78,0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x7C,0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x80,0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x84,0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x88,0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x8C,0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x90,0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x94,0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x98,0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0x9C,0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40,0x1F, 0x82, 0xA0,0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40,0x2F, 0x00, 0x00,0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40,0x2F, 0x00, 0x08,0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40,0x2F, 0x00, 0x0C,0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40,0x2F, 0x00, 0x10,0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40,0x2F, 0x00, 0x14,0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40,0x2F, 0x00, 0x18,0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40,0x2F, 0x00, 0x1C,0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40,0x2F, 0x00, 0x20,0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40,0x2F, 0x00, 0x24,0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40,0x2F, 0x00, 0x28,0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40,0x2F, 0x00, 0x2C,0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40,0x2F, 0x00, 0x30,0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40,0x2F, 0x00, 0x04,0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40,0x2F, 0x00, 0x40,0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40,0x2F, 0x00, 0x44,0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40,0x2F, 0x00, 0x48,0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40,0x2F, 0x00, 0x4C,0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40,0x2F, 0x00, 0x80,0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40,0x2F, 0x00, 0x84,0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40,0x2F, 0x00, 0x94,0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40,0x2F, 0x00, 0x98,0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40,0x2F, 0x00, 0x90,0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40,0x2F, 0x00, 0x9C,0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF,0x00, 0x0C, 0x1C,0x40, 0x2F, 0x00, 0x3C,0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC,0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40,0x2F, 0x00, 0x90,0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40,0x2F, 0x00, 0x9C,0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF,0x00, 0x0C, 0x1C,0x40, 0x2F, 0x00, 0x3C,0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC,0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40,0x2F, 0x00, 0x90,0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40,0x2F, 0x00, 0x9C,0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF,0x00, 0x0C, 0x1C,0x40, 0x2F, 0x00, 0x3C,0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC,0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40,0x2F, 0x00, 0xA0,0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40,0x2F, 0x00, 0x90,0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40,0x2F, 0x00, 0x9C,0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF,0x00, 0x0C, 0x1C,0x40, 0x2F, 0x00, 0x3C,0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC,0x00, 0x0C, 0x04,0x40, 0x2F, 0x00, 0x4C,0x50, 0x21, 0x0A, 0x09 +}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else /* if defined( XIP_BOOT_HEADER_DCD_ENABLE ) && ( XIP_BOOT_HEADER_DCD_ENABLE == 1 ) */ +const uint8_t dcd_data[] = { 0x00 }; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/examples/evkbmimxrt1060/sesip/board/dcd.h b/examples/evkbmimxrt1060/sesip/board/dcd.h new file mode 100644 index 0000000..1274b43 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION ( MAKE_VERSION( 2, 0, 1 ) ) +/*@}*/ + +/************************************* +* DCD Data +*************************************/ +#define DCD_TAG_HEADER ( 0xD2 ) +#define DCD_VERSION ( 0x41 ) +#define DCD_TAG_HEADER_SHIFT ( 24 ) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/examples/evkbmimxrt1060/sesip/board/flash_partitioning.h b/examples/evkbmimxrt1060/sesip/board/flash_partitioning.h new file mode 100644 index 0000000..2a5285b --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/flash_partitioning.h @@ -0,0 +1,55 @@ +/* + * FreeRTOS version 202107.00-LTS + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://aws.amazon.com/freertos + * http://www.FreeRTOS.org + */ + + +/** + * @brief Header file containing platform abstraction layer APIS for OTA update. + */ + +#ifndef FLASH_PARTITIONING_H +#define FLASH_PARTITIONING_H + +/** Flash device type enabled */ +#define ISSI_IS25WPxxxA + +/* Total Flash Size */ +#define COMPONENT_FLASHIAP_SIZE 8388608 + +/* MCU Flash layout. */ +#define BOOT_FLASH_BASE 0x60000000 +#define BOOT_FLASH_ACT_APP 0x60040000 +#define BOOT_FLASH_CAND_APP 0x60240000 + + +/* Offsets for each image slots used for OTA. */ +#define FLASH_AREA_IMAGE_1_OFFSET ( BOOT_FLASH_ACT_APP - BOOT_FLASH_BASE ) /*MCUboot occupies 512KB */ +#define FLASH_AREA_IMAGE_1_SIZE ( BOOT_FLASH_CAND_APP - BOOT_FLASH_ACT_APP ) /*image1 slot occupies 2MB */ +#define FLASH_AREA_IMAGE_2_OFFSET ( FLASH_AREA_IMAGE_1_OFFSET + FLASH_AREA_IMAGE_1_SIZE ) +#define FLASH_AREA_IMAGE_2_SIZE FLASH_AREA_IMAGE_1_SIZE /*image2 slot occupies 2MB */ +#define FLASH_AREA_IMAGE_3_OFFSET ( FLASH_AREA_IMAGE_2_OFFSET + FLASH_AREA_IMAGE_2_SIZE ) +#define FLASH_AREA_IMAGE_3_SIZE 0x80000 /* scratch slot occupies 512KB */ + + +#endif /* FLASH_PARTITIONING_H */ diff --git a/examples/evkbmimxrt1060/sesip/board/flexspi_nor_flash_ops.c b/examples/evkbmimxrt1060/sesip/board/flexspi_nor_flash_ops.c new file mode 100644 index 0000000..87e8754 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/flexspi_nor_flash_ops.c @@ -0,0 +1,669 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "flexspi_nor_flash_ops.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define FLASH_BUSY_STATUS_POL 1 +#define FLASH_BUSY_STATUS_OFFSET 0 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + *****************************************************************************/ + +extern const uint32_t customLUT[ CUSTOM_LUT_LENGTH ]; + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined( ISSI_AT25SFxxxA ) || defined( ISSI_IS25LPxxxA ) || defined( ISSI_IS25WPxxxA ) || defined( WINBOND_W25QxxxJV ) +static status_t flexspi_nor_write_enable( FLEXSPI_Type * base, + uint32_t baseAddr ) +{ + flexspi_transfer_t flashXfer; + status_t status; + + /* Write enable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + return status; +} + +static status_t flexspi_nor_wait_bus_busy( FLEXSPI_Type * base ) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue; + status_t status; + flexspi_transfer_t flashXfer; + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + flashXfer.data = &readValue; + flashXfer.dataSize = 1; + + do + { + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + if( FLASH_BUSY_STATUS_POL ) + { + if( readValue & ( 1U << FLASH_BUSY_STATUS_OFFSET ) ) + { + isBusy = true; + } + else + { + isBusy = false; + } + } + else + { + if( readValue & ( 1U << FLASH_BUSY_STATUS_OFFSET ) ) + { + isBusy = false; + } + else + { + isBusy = true; + } + } + } while( isBusy ); + + return status; +} + +status_t flexspi_nor_flash_erase_sector( FLEXSPI_Type * base, + uint32_t address ) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write enable */ + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base ); + + /* Do software reset. */ + FLEXSPI_SoftwareReset( base ); + + return status; +} + +status_t flexspi_nor_flash_page_program( FLEXSPI_Type * base, + uint32_t dstAddr, + const uint32_t * src, + size_t len ) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write enable */ + status = flexspi_nor_write_enable( base, dstAddr ); + + if( status != kStatus_Success ) + { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = dstAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; + flashXfer.data = ( uint32_t * ) src; + flashXfer.dataSize = len /*FLASH_PAGE_SIZE*/; + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base ); + + /* Do software reset. */ +#if defined( FSL_FEATURE_SOC_OTFAD_COUNT ) + base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK; + base->AHBCR &= ~( FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK ); +#else + FLEXSPI_SoftwareReset( base ); +#endif + + return status; +} + +#elif defined( Macronix_MX25UM51345G ) || defined( Macronix_MX25UM51345G_2nd ) +status_t flexspi_nor_write_enable( FLEXSPI_Type * base, + uint32_t baseAddr, + bool enableOctal ) +{ + flexspi_transfer_t flashXfer; + status_t status; + + /* Write neable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + + if( enableOctal ) + { + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_OPI; + } + else + { + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + } + + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + return status; +} + +status_t flexspi_nor_wait_bus_busy( FLEXSPI_Type * base, + bool enableOctal ) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue; + status_t status; + flexspi_transfer_t flashXfer; + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + + if( enableOctal ) + { + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS_OPI; + } + else + { + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUS; + } + + flashXfer.data = &readValue; + flashXfer.dataSize = 1; + + do + { + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + if( FLASH_BUSY_STATUS_POL ) + { + if( readValue & ( 1U << FLASH_BUSY_STATUS_OFFSET ) ) + { + isBusy = true; + } + else + { + isBusy = false; + } + } + else + { + if( readValue & ( 1U << FLASH_BUSY_STATUS_OFFSET ) ) + { + isBusy = false; + } + else + { + isBusy = true; + } + } + } while( isBusy ); + + return status; +} + +status_t flexspi_nor_enable_octal_mode( FLEXSPI_Type * base ) +{ + flexspi_transfer_t flashXfer; + status_t status; + uint32_t writeValue = FLASH_ENABLE_OCTAL_CMD; + + /* Write neable */ + status = flexspi_nor_write_enable( base, 0, false ); + + if( status != kStatus_Success ) + { + return status; + } + + /* Enable quad mode. */ + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ENTEROPI; + flashXfer.data = &writeValue; + flashXfer.dataSize = 1; + + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base, true ); + + return status; +} + +status_t flexspi_nor_flash_erase_sector( FLEXSPI_Type * base, + uint32_t address ) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write neable */ + status = flexspi_nor_write_enable( base, 0, true ); + + if( status != kStatus_Success ) + { + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base, true ); + + /* Do software reset. */ + FLEXSPI_SoftwareReset( base ); + + return status; +} + +status_t flexspi_nor_flash_program( FLEXSPI_Type * base, + uint32_t dstAddr, + const uint32_t * src, + uint32_t length ) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write neable */ + status = flexspi_nor_write_enable( base, dstAddr, true ); + + if( status != kStatus_Success ) + { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = dstAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM; + flashXfer.data = ( uint32_t * ) src; + flashXfer.dataSize = length; + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base, true ); + + /* Do software reset. */ + FLEXSPI_SoftwareReset( base ); + + return status; +} + +#elif defined( Cypress_S26KSxxxS ) +static status_t flexspi_nor_write_enable( FLEXSPI_Type * base, + uint32_t baseAddr ) +{ + flexspi_transfer_t flashXfer; + status_t status; + + /* Write neable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + return status; +} + +static status_t flexspi_nor_wait_bus_busy( FLEXSPI_Type * base ) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue; + status_t status; + flexspi_transfer_t flashXfer; + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS; + flashXfer.data = &readValue; + flashXfer.dataSize = 2; + + do + { + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + if( readValue & 0x8000 ) + { + isBusy = false; + } + else + { + isBusy = true; + } + + if( readValue & 0x3200 ) + { + status = kStatus_Fail; + break; + } + } while( isBusy ); + + return status; +} + + +status_t flexspi_nor_hyperbus_read( FLEXSPI_Type * base, + uint32_t addr, + uint32_t * buffer, + uint32_t bytes ) +{ + flexspi_transfer_t flashXfer; + status_t status; + + flashXfer.deviceAddress = addr * 2; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA; + flashXfer.data = buffer; + flashXfer.dataSize = bytes; + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + return status; +} + +status_t flexspi_nor_flash_erase_sector( FLEXSPI_Type * base, + uint32_t address ) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write enable */ + status = flexspi_nor_write_enable( base, address ); + + if( status != kStatus_Success ) + { + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 4; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base ); + + /* Do software reset. */ + FLEXSPI_SoftwareReset( EXAMPLE_FLEXSPI ); + + return status; +} + +status_t flexspi_nor_flash_page_program( FLEXSPI_Type * base, + uint32_t address, + const uint32_t * src, + size_t len ) +{ + status_t status; + flexspi_transfer_t flashXfer; + + flexspi_clock_set(); + + /* Write neable */ + status = flexspi_nor_write_enable( base, address ); + + if( status != kStatus_Success ) + { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM; + flashXfer.data = ( uint32_t * ) src; + flashXfer.dataSize = len /*FLASH_PAGE_SIZE*/; + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base ); + + flexspi_clock_update(); + + return status; +} +#endif /* ISSI_AT25SFxxxA ISSI_IS25LPxxxA ISSI_IS25WPxxxA WINBOND_W25QxxxJV */ + + +/* Make sure the data address is 4 bytes aligned */ +static uint32_t flash_program_buffer[ 64 ]; +status_t sfw_flash_write( uint32_t dstAddr, + const void * src, + size_t len ) +{ + status_t status; + uint8_t page_off = 0; + const uint8_t * src_addr = ( const uint8_t * ) src; + uint16_t write_size = 0; + + if( ( ( dstAddr + len ) & FLEXSPI_BASE_ADDRESS_MASK ) > ( FLASH_SIZE_KB * 0x400 ) ) + { + return -1; + } + + for( ; len > 0; ) + { + page_off = dstAddr % FLASH_PAGE_SIZE; /* An offset value in a page */ + + if( ( page_off + len ) <= FLASH_PAGE_SIZE ) /* Write the last page */ + { + write_size = len; + } + else + { + write_size = FLASH_PAGE_SIZE - page_off; + } + + memcpy( flash_program_buffer, src_addr, write_size ); + status = flexspi_nor_flash_page_program( EXAMPLE_FLEXSPI, dstAddr, flash_program_buffer, write_size ); + + if( status != kStatus_Success ) + { + return -1; + } + + src_addr += write_size; + dstAddr += write_size; + len -= write_size; + } + + return 0; +} + +status_t sfw_flash_read( uint32_t dstAddr, + void * buf, + size_t len ) +{ + uint32_t addr = dstAddr | EXAMPLE_FLEXSPI_AMBA_BASE; + + +/* DCACHE_CleanInvalidateByRange(area->fa_off + off, len); */ + memcpy( buf, ( void * ) addr, len ); + + return 0; +} + +status_t sfw_flash_erase( uint32_t address, + size_t len ) +{ + status_t status; + + if( ( address % SECTOR_SIZE ) || ( len % SECTOR_SIZE ) ) + { + return -1; + } + + for( ; len > 0; len -= SECTOR_SIZE ) + { + /* Erase sectors. */ + status = flexspi_nor_flash_erase_sector( EXAMPLE_FLEXSPI, address ); + + if( status != kStatus_Success ) + { + return -1; + } + + address += SECTOR_SIZE; + } + + return 0; +} + +status_t sfw_flash_init( void ) +{ + /* Update LUT table. */ + FLEXSPI_UpdateLUT( EXAMPLE_FLEXSPI, 0, &customLUT[ 0 ], CUSTOM_LUT_LENGTH ); + + /* Do software reset. */ + FLEXSPI_SoftwareReset( EXAMPLE_FLEXSPI ); + + return kStatus_Success; +} + +status_t sfw_flash_read_ipc( uint32_t address, + uint8_t * buffer, + uint32_t length ) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Prepare page program command */ + flashXfer.deviceAddress = address & ( ~EXAMPLE_FLEXSPI_AMBA_BASE ); + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD; + flashXfer.data = ( uint32_t * ) ( void * ) buffer; + flashXfer.dataSize = length; + status = FLEXSPI_TransferBlocking( EXAMPLE_FLEXSPI, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( EXAMPLE_FLEXSPI ); + + return status; +} diff --git a/examples/evkbmimxrt1060/sesip/board/flexspi_nor_flash_ops.h b/examples/evkbmimxrt1060/sesip/board/flexspi_nor_flash_ops.h new file mode 100644 index 0000000..76fa090 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/flexspi_nor_flash_ops.h @@ -0,0 +1,79 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FLEXSPI_FLASH_CONFIG_H_ +#define _FLEXSPI_FLASH_CONFIG_H_ + +#include +#include "fsl_flexspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*${macro:start}*/ +#define EXAMPLE_FLEXSPI FLEXSPI +#define FLASH_SIZE_KB ( COMPONENT_FLASHIAP_SIZE / 1024 ) /* 0x2000= 64Mb/KByte */ +#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE +#define FLASH_PAGE_SIZE ( 256 ) +#define SECTOR_SIZE ( 0x1000 ) /* 4K */ +#define FLEXSPI_BASE_ADDRESS_MASK ( FLASH_SIZE_KB * 0x400 - 1 ) + +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0 /* set it to index0 to align with xip settings */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2 +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4 +#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5 +#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12 + +#define CUSTOM_LUT_LENGTH 60 +#define FLASH_BUSY_STATUS_POL 1 +#define FLASH_BUSY_STATUS_OFFSET 0 + +/*${macro:end}*/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*${prototype:start}*/ +void BOARD_InitHardware( void ); +static inline void flexspi_clock_init( void ) +{ +#if defined( XIP_EXTERNAL_FLASH ) && ( XIP_EXTERNAL_FLASH == 1 ) + CLOCK_SetMux( kCLOCK_FlexspiMux, 0x2 ); /* Choose PLL2 PFD2 clock as flexspi source clock. 396M */ + CLOCK_SetDiv( kCLOCK_FlexspiDiv, 2 ); /* flexspi clock 133M. */ +#else + const clock_usb_pll_config_t g_ccmConfigUsbPll = { .loopDivider = 0U }; + CLOCK_InitUsb1Pll( &g_ccmConfigUsbPll ); + CLOCK_InitUsb1Pfd( kCLOCK_Pfd0, 24 ); /* Set PLL3 PFD0 clock 360MHZ. */ + CLOCK_SetMux( kCLOCK_FlexspiMux, 0x3 ); /* Choose PLL3 PFD0 clock as flexspi source clock. */ + CLOCK_SetDiv( kCLOCK_FlexspiDiv, 2 ); /* flexspi clock 120M. */ +#endif +} + +status_t sfw_flash_erase( uint32_t address, + size_t len ); +status_t sfw_flash_write( uint32_t dstAddr, + const void * src, + size_t len ); +status_t sfw_flash_read( uint32_t dstAddr, + void * buf, + size_t len ); +status_t sfw_flash_init( void ); +status_t sfw_flash_read_ipc( uint32_t address, + uint8_t * buffer, + uint32_t length ); +status_t flexspi_nor_flash_erase_sector( FLEXSPI_Type * base, + uint32_t address ); +status_t flexspi_nor_flash_page_program( FLEXSPI_Type * base, + uint32_t dstAddr, + const uint32_t * src, + size_t len ); + +/*${prototype:end}*/ + +#endif /* _FLEXSPI_FLASH_H_ */ diff --git a/examples/evkbmimxrt1060/sesip/board/mflash_drv.c b/examples/evkbmimxrt1060/sesip/board/mflash_drv.c new file mode 100644 index 0000000..4006471 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/mflash_drv.c @@ -0,0 +1,691 @@ +/* + * Copyright 2018-2021 NXP + * + * SPDX + * License-Identifier: BSD-3-Clause + */ + +#include + +#include "fsl_flexspi.h" +#include "fsl_cache.h" +#include "pin_mux.h" + +#include "mflash_drv.h" +#include "flexspi_nor_flash_ops.h" + + +#ifndef XIP_EXTERNAL_FLASH + +#define FLASH_SIZE 0x8000 + +flexspi_device_config_t deviceconfig = +{ + .flexspiRootClk = 100000000, + .flashSize = FLASH_SIZE, + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 3, + .CSSetupTime = 3, + .dataValidTime = 0, + .columnspace = 0, + .enableWordAddress = 0, + .AWRSeqIndex = 0, + .AWRSeqNumber = 0, + .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD, + .ARDSeqNumber = 1, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .AHBWriteWaitInterval = 0, +}; +#endif /* ifndef XIP_EXTERNAL_FLASH */ + +/* Custom LUT Table for ISSI_IS25WPxxxA used in RT1060. */ +static uint32_t customLUT[ CUSTOM_LUT_LENGTH ] = +{ + [ 4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD ] = + FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18 ), + [ 4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1 ] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04 ), + + /* Erase Sector */ + [ 4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR ] = + FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xD7, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18 ), + + /* Erase whole chip */ + [ 4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP ] = + FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0 ), + + /* Page Program - quad mode or Octal mode */ + [ 4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD ] = + FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18 ), + [ 4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1 ] = + FLEXSPI_LUT_SEQ( kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x01 /*0x04*/, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0 ), + + /* Read status register */ + [ 4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG ] = + FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04 ), + + /* Write Enable */ + [ 4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE ] = + FLEXSPI_LUT_SEQ( kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0 ) +}; + +static status_t flexspi_nor_wait_bus_busy( FLEXSPI_Type * base ) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue; + status_t status; + flexspi_transfer_t flashXfer; + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + flashXfer.data = &readValue; + flashXfer.dataSize = 1; + + do + { + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + if( FLASH_BUSY_STATUS_POL ) + { + if( readValue & ( 1U << FLASH_BUSY_STATUS_OFFSET ) ) + { + isBusy = true; + } + else + { + isBusy = false; + } + } + else + { + if( readValue & ( 1U << FLASH_BUSY_STATUS_OFFSET ) ) + { + isBusy = false; + } + else + { + isBusy = true; + } + } + } while( isBusy ); + + return status; +} + +static status_t flexspi_nor_write_enable( FLEXSPI_Type * base, + uint32_t address ) +{ + flexspi_transfer_t flashXfer; + status_t status; + + /* Write neable */ + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + return status; +} + +status_t flexspi_nor_enable_quad_mode( FLEXSPI_Type * base ) +{ + flexspi_transfer_t flashXfer; + status_t status; + uint32_t writeValue = 0x40; + + /* Write neable */ + status = flexspi_nor_write_enable( base, 0 ); + + if( status != kStatus_Success ) + { + return status; + } + + /* Enable quad mode. */ + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG; + flashXfer.data = &writeValue; + flashXfer.dataSize = 1; + + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base ); + + return status; +} + +static status_t flexspi_nor_flash_sector_erase( FLEXSPI_Type * base, + uint32_t address ) +{ + status_t status; + flexspi_transfer_t flashXfer; + + /* Write enable */ + status = flexspi_nor_write_enable( base, address ); + + if( status != kStatus_Success ) + { + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + if( status != kStatus_Success ) + { + return status; + } + + status = flexspi_nor_wait_bus_busy( base ); + + return status; +} + + +status_t flexspi_nor_read_data( FLEXSPI_Type * base, + uint32_t startAddress, + uint32_t * buffer, + uint32_t length ) +{ + status_t status; + flexspi_transfer_t flashXfer; + uint32_t readAddress = startAddress; + + /* Read page. */ + flashXfer.deviceAddress = readAddress; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD; + flashXfer.data = buffer; + flashXfer.dataSize = length; + + status = FLEXSPI_TransferBlocking( base, &flashXfer ); + + return status; +} + +/* Initialize flash peripheral, + * cannot be invoked directly, requires calling wrapper in non XIP memory */ +static int32_t mflash_drv_init_internal( void ) +{ + /* NOTE: Multithread access is not supported for SRAM target. + * XIP target MUST be protected by disabling global interrupts + * since all ISR (and API that is used inside) is placed at XIP. + * It is necessary to place at least "mflash_drv.o", "fsl_flexspi.o" to SRAM */ + /* disable interrupts when running from XIP */ + uint32_t primask = __get_PRIMASK(); + + __asm( "cpsid i" ); + + status_t status = kStatus_Success; + +#ifndef XIP_EXTERNAL_FLASH + flexspi_config_t config; + + /* Get FLEXSPI default settings and configure the flexspi. */ + FLEXSPI_GetDefaultConfig( &config ); + + /* Set AHB buffer size for reading data through AHB bus. */ + config.ahbConfig.enableAHBPrefetch = true; + config.ahbConfig.enableAHBBufferable = true; + config.ahbConfig.enableAHBCachable = true; + config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad; + FLEXSPI_Init( MFLASH_FLEXSPI, &config ); + + /* AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation */ + MFLASH_FLEXSPI->AHBCR |= FLEXSPI_AHBCR_READADDROPT_MASK; + + /* Configure flash settings according to serial flash feature. */ + FLEXSPI_SetFlashConfig( MFLASH_FLEXSPI, &deviceconfig, kFLEXSPI_PortA1 ); +#endif /* ifndef XIP_EXTERNAL_FLASH */ + + /* Update LUT table. */ + FLEXSPI_UpdateLUT( MFLASH_FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH ); + + /*FLEXSPI_SoftwareReset(MFLASH_FLEXSPI); */ + + +#ifndef XIP_EXTERNAL_FLASH + /* Enter quad mode. */ + status = flexspi_nor_enable_quad_mode( MFLASH_FLEXSPI ); +#endif + + if( primask == 0 ) + { + __asm( "cpsie i" ); + } + + return status; +} + +/* API - initialize 'mflash' */ +int32_t mflash_drv_init( void ) +{ + /* Necessary to have double wrapper call in non_xip memory */ + return mflash_drv_init_internal(); +} + +/* Internal - erase single sector */ +static int32_t mflash_drv_sector_erase_internal( uint32_t sector_addr ) +{ + status_t status; + uint32_t primask = __get_PRIMASK(); + + __asm( "cpsid i" ); + + status = flexspi_nor_flash_sector_erase( MFLASH_FLEXSPI, sector_addr ); + + /* Do software reset. */ + FLEXSPI_SoftwareReset( MFLASH_FLEXSPI ); + + DCACHE_InvalidateByRange( MFLASH_BASE_ADDRESS + sector_addr, MFLASH_SECTOR_SIZE ); + + if( primask == 0 ) + { + __asm( "cpsie i" ); + } + + /* Flush pipeline to allow pending interrupts take place + * before starting next loop */ + __ISB(); + + return status; +} + +/* Calling wrapper for 'mflash_drv_sector_erase_internal'. + * Erase one sector starting at 'sector_addr' - must be sector aligned. + */ +int32_t mflash_drv_sector_erase( uint32_t sector_addr ) +{ + if( 0 == mflash_drv_is_sector_aligned( sector_addr ) ) + { + return kStatus_InvalidArgument; + } + + return mflash_drv_sector_erase_internal( sector_addr ); +} + +/* Internal - write single page */ +static int32_t mflash_drv_page_program_internal( uint32_t page_addr, + uint32_t * data ) +{ + uint32_t primask = __get_PRIMASK(); + + __asm( "cpsid i" ); + + status_t status; + + status = flexspi_nor_flash_page_program( MFLASH_FLEXSPI, page_addr, data, MFLASH_PAGE_SIZE ); + + /* Do software reset. */ + FLEXSPI_SoftwareReset( MFLASH_FLEXSPI ); + + DCACHE_InvalidateByRange( MFLASH_BASE_ADDRESS + page_addr, MFLASH_PAGE_SIZE ); + + if( primask == 0 ) + { + __asm( "cpsie i" ); + } + + /* Flush pipeline to allow pending interrupts take place + * before starting next loop */ + __ISB(); + + return status; +} + +/* Calling wrapper for 'mflash_drv_page_program_internal'. + * Write 'data' to 'page_addr' - must be page aligned. + * NOTE: Don't try to store constant data that are located in XIP !! + */ +int32_t mflash_drv_page_program( uint32_t page_addr, + uint32_t * data ) +{ + if( 0 == mflash_drv_is_page_aligned( page_addr ) ) + { + return kStatus_InvalidArgument; + } + + return mflash_drv_page_program_internal( page_addr, data ); +} + +/* Internal - read data */ +static int32_t mflash_drv_read_internal( uint32_t addr, + uint32_t * buffer, + uint32_t len ) +{ + uint32_t primask = __get_PRIMASK(); + + __asm( "cpsid i" ); + + status_t status; + + status = flexspi_nor_read_data( MFLASH_FLEXSPI, addr, buffer, len ); + + /* Do software reset. */ + FLEXSPI_SoftwareReset( MFLASH_FLEXSPI ); + + if( primask == 0 ) + { + __asm( "cpsie i" ); + } + + /* Flush pipeline to allow pending interrupts take place + * before starting next loop */ + __ISB(); + + return status; +} + +/* Calling wrapper for 'mflash_drv_read_internal'. */ +int32_t mflash_drv_read( uint32_t addr, + uint32_t * buffer, + uint32_t len ) +{ + /* Check alignment */ + if( ( ( uint32_t ) buffer % 4 ) || ( len % 4 ) ) + { + return kStatus_InvalidArgument; + } + + return mflash_drv_read_internal( addr, buffer, len ); +} + +/* Returns pointer (AHB address) to memory area where the specified region of FLASH is mapped, NULL on failure (could + * not map continuous block) */ +void * mflash_drv_phys2log( uint32_t addr, + uint32_t len ) +{ + /* take FLEXSPI remapping into account */ + uint32_t remap_offset = IOMUXC_GPR->GPR32 & 0xFFFFF000; + uint32_t remap_start = IOMUXC_GPR->GPR30 & 0xFFFFF000; + uint32_t remap_end = IOMUXC_GPR->GPR31 & 0xFFFFF000; + + /* calculate the bus address where the requested FLASH region is expected to be available */ + uint32_t bus_addr = addr + MFLASH_BASE_ADDRESS; + + if( ( remap_offset == 0 ) || ( remap_end <= remap_start ) ) + { + /* remapping is not active */ + return ( void * ) bus_addr; + } + + if( ( remap_start >= bus_addr + len ) || ( remap_end <= bus_addr ) ) + { + /* remapping window does not collide with bus addresses normally assigned for requested range of FLASH */ + return ( void * ) bus_addr; + } + + if( ( remap_start + remap_offset <= bus_addr ) && ( remap_end + remap_offset >= bus_addr + len ) ) + { + /* remapping window covers the whole requested range of FLASH, return address adjusted by negative offset */ + return ( void * ) ( bus_addr - remap_offset ); + } + + /* the bus address region normally assigned for requested range of FLASH is partially or completely shadowed by + * remapping, fail */ + return NULL; +} + +/* Returns address of physical memory where the area accessible by given pointer is actually stored, UINT32_MAX on + * failure (could not map as continuous block) */ +uint32_t mflash_drv_log2phys( void * ptr, + uint32_t len ) +{ + /* take FLEXSPI remapping into account */ + uint32_t remap_offset = IOMUXC_GPR->GPR32 & 0xFFFFF000; + uint32_t remap_start = IOMUXC_GPR->GPR30 & 0xFFFFF000; + uint32_t remap_end = IOMUXC_GPR->GPR31 & 0xFFFFF000; + + /* calculate the bus address where the requested FLASH region is expected to be available */ + uint32_t bus_addr = ( uint32_t ) ptr; + + if( bus_addr < MFLASH_BASE_ADDRESS ) + { + /* the pointer points outside of the flash memory area */ + return UINT32_MAX; + } + + if( ( remap_offset == 0 ) || ( remap_end <= remap_start ) ) + { + /* remapping is not active */ + return( bus_addr - MFLASH_BASE_ADDRESS ); + } + + if( ( remap_start >= bus_addr + len ) || ( remap_end <= bus_addr ) ) + { + /* remapping window does not affect the requested memory area */ + return( bus_addr - MFLASH_BASE_ADDRESS ); + } + + if( ( remap_start <= bus_addr ) && ( remap_end >= bus_addr + len ) ) + { + /* remapping window covers the whole address range, return address adjusted by offset */ + return( bus_addr + remap_offset - MFLASH_BASE_ADDRESS ); + } + + /* the bus address region partially collides with the remapping window, hence the range is not mapped to continuous + * block in the FLASH, fail */ + return UINT32_MAX; +} + +/* Temporary sector shadow buffer. Use uint32_t type to force 4B alignment and + * improve copy operation */ +static uint32_t g_flashm_sector[ MFLASH_SECTOR_SIZE / sizeof( uint32_t ) ]; + +/* Internal - write data of 'data_len' to single sector 'sector_addr', starting from 'sect_off' */ +static int32_t mflash_drv_sector_update( uint32_t sector_addr, + uint32_t sect_off, + const uint8_t * data, + uint32_t data_len ) +{ + int sector_erase_req = 0; + uint32_t page_program_map = 0; /* Current implementation is limited to 32 pages per sector */ + + /* Address not aligned to sector boundary */ + if( false == mflash_drv_is_sector_aligned( sector_addr ) ) + { + return -1; + } + + /* Offset + length exceeed sector size */ + if( sect_off + data_len > MFLASH_SECTOR_SIZE ) + { + return -1; + } + + if( 0 != mflash_drv_read( sector_addr, &g_flashm_sector[ 0 ], sizeof( g_flashm_sector ) ) ) + { + return -2; + } + + /* Diff the data to determine pages to be programed */ + for( uint32_t i = 0; i < data_len; i++ ) + { + uint8_t cur_value = ( ( uint8_t * ) ( g_flashm_sector ) )[ sect_off + i ]; + uint8_t new_value = data[ i ]; + + if( ( cur_value | new_value ) != cur_value ) + { + /* A bit needs to be flipped from 0 to 1, the whole sector has to be erased */ + sector_erase_req = 1; + break; + } + + if( cur_value != new_value ) + { + /* There is a change, the page has to be programmed for sure */ + page_program_map |= 1 << ( ( sect_off + i ) / MFLASH_PAGE_SIZE ); + } + } + +#if !defined( MFLASH_INC_WRITES ) || !MFLASH_INC_WRITES + /* Perform blank check page by page until decision for sector erase is made or we reach last page of the sector */ + for( int page_idx = 0; ( 0 == sector_erase_req ) && page_idx < MFLASH_SECTOR_SIZE / MFLASH_PAGE_SIZE; page_idx++ ) + { + /* Check only pages which need to be programed */ + if( page_program_map & ( 1 << page_idx ) ) + { + int page_word_start = page_idx * ( MFLASH_PAGE_SIZE / sizeof( g_flashm_sector[ 0 ] ) ); + int page_word_end = page_word_start + ( MFLASH_PAGE_SIZE / sizeof( g_flashm_sector[ 0 ] ) ); + + for( int i = page_word_start; i < page_word_end; i++ ) + { + if( g_flashm_sector[ i ] != 0xFFFFFFFF ) + { + /* Mark sector to be erased and quit */ + sector_erase_req = 1; + break; + } + } + } + } +#endif /* if !defined( MFLASH_INC_WRITES ) || !MFLASH_INC_WRITES */ + + /* Copy data to be programmed byte by byte to shadow buffer at proper position */ + for( uint32_t i = 0; i < data_len; i++ ) + { + ( ( uint8_t * ) g_flashm_sector )[ sect_off + i ] = data[ i ]; + } + + /* If sector is to be erased, update page program map according to non-blank areas in the shadow buffer */ + if( 0 != sector_erase_req ) + { + for( int page_idx = 0; page_idx < MFLASH_SECTOR_SIZE / MFLASH_PAGE_SIZE; page_idx++ ) + { + int page_word_start = page_idx * ( MFLASH_PAGE_SIZE / sizeof( g_flashm_sector[ 0 ] ) ); + int page_word_end = page_word_start + ( MFLASH_PAGE_SIZE / sizeof( g_flashm_sector[ 0 ] ) ); + + for( int i = page_word_start; i < page_word_end; i++ ) + { + if( g_flashm_sector[ i ] != 0xFFFFFFFF ) + { + /* Mark the page for programming and go for next one */ + page_program_map |= ( 1 << page_idx ); + break; + } + } + } + } + + /* Erase the sector if required */ + if( 0 != sector_erase_req ) + { + if( 0 != mflash_drv_sector_erase( sector_addr ) ) + { + return -2; + } + } + + /* Program the required pages */ + for( int page_idx = 0; page_idx < MFLASH_SECTOR_SIZE / MFLASH_PAGE_SIZE; page_idx++ ) + { + if( page_program_map & ( 1 << page_idx ) ) + { + if( 0 != + mflash_drv_page_program( sector_addr + page_idx * MFLASH_PAGE_SIZE, + g_flashm_sector + page_idx * ( MFLASH_PAGE_SIZE / sizeof( g_flashm_sector[ 0 ] ) ) ) ) + { + return -3; + } + } + } + + /* mflash_drv_read_mode(); */ + return 0; +} + +/* Write data to flash, cannot be invoked directly, requires calling wrapper in non XIP memory */ +int32_t mflash_drv_write_internal( uint32_t addr, + const uint8_t * data, + uint32_t data_len ) +{ + /* Interval <0, sector_size) */ + uint32_t to_write = 0; + /* Interval (data_len, 0> */ + uint32_t to_remain = data_len; + /* Physical address in external FLASH device */ + + int32_t result = 0; + + for( + /* Calculate address of first sector */ + uint32_t sect_a = ( addr / MFLASH_SECTOR_SIZE ) * MFLASH_SECTOR_SIZE, + /* and first sector offset */ + sect_of = addr % MFLASH_SECTOR_SIZE, + /* and set first data offset to 0*/ + data_of = 0; + /* Continue until sector address exceed target address + data_length */ + sect_a < addr + data_len; + /* Move to next sector */ + sect_a += MFLASH_SECTOR_SIZE, + /* and move pointer to data */ + data_of += to_write ) + { + /* If remaining data is exceed 'sector_size', write 'sector_size' length */ + if( to_remain > MFLASH_SECTOR_SIZE - sect_of ) + { + to_write = MFLASH_SECTOR_SIZE - sect_of; + to_remain = to_remain - to_write; + } + /* else write remaining data length */ + else + { + to_write = to_remain; + to_remain = 0; + } + + /* Write at 'sect_a' sector, starting at 'sect_of' using '&data[data_of]' of length 'to_write' */ + result = mflash_drv_sector_update( sect_a, sect_of, data + data_of, to_write ); + + if( 0 != result ) + { + return -1; + } + + /* Only first sector is allowed to have an offset */ + sect_of = 0; + } + + return 0; +} + +/* Calling wrapper for 'mflash_drv_write_internal'. + * Write 'data' of 'data_len' to 'any_addr' - which doesn't have to be sector aligned. + * NOTE: Don't try to store constant data that are located in XIP !! + */ +int32_t mflash_drv_write( uint32_t addr, + const uint8_t * data, + uint32_t data_len ) +{ + volatile int32_t result; + + result = mflash_drv_write_internal( addr, data, data_len ); + return result; +} diff --git a/examples/evkbmimxrt1060/sesip/board/mflash_drv.h b/examples/evkbmimxrt1060/sesip/board/mflash_drv.h new file mode 100644 index 0000000..668b083 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/mflash_drv.h @@ -0,0 +1,41 @@ +/* + * Copyright 2018-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MFLASH_DRV_H__ +#define __MFLASH_DRV_H__ + +#include "mflash_common.h" + +/* Flash constants */ +#ifndef MFLASH_SECTOR_SIZE +#define MFLASH_SECTOR_SIZE ( 0x1000 ) +#endif + +#ifndef MFLASH_PAGE_SIZE +#define MFLASH_PAGE_SIZE ( 256 ) +#endif + +#ifndef MFLASH_FLEXSPI +#define MFLASH_FLEXSPI ( FLEXSPI ) +#endif + +#ifndef MFLASH_BASE_ADDRESS +#define MFLASH_BASE_ADDRESS ( FlexSPI_AMBA_BASE ) +#endif + +/* Allow incremental writes without erase (enabled by default). + * This method cannot be used in certain cases, e.g. when page checksums are used + */ +#ifndef MFLASH_INC_WRITE +#define MFLASH_INC_WRITE 1 +#endif + + +int32_t mflash_drv_write( uint32_t addr, + const uint8_t * data, + uint32_t data_len ); + +#endif /* ifndef __MFLASH_DRV_H__ */ diff --git a/examples/evkbmimxrt1060/sesip/board/pin_mux.c b/examples/evkbmimxrt1060/sesip/board/pin_mux.c new file mode 100644 index 0000000..52b413f --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/pin_mux.c @@ -0,0 +1,360 @@ +/* Copyright 2018-2020 NXP + * + * This software is owned or controlled by NXP and may only be used + * strictly in accordance with the applicable license terms. By expressly + * accepting such terms or by downloading, installing, activating and/or + * otherwise using the software, you are agreeing that you have read, and + * that you agree to comply with and are bound by, such license terms. If + * you do not agree to be bound by the applicable license terms, then you + * may not retain, install, activate or otherwise use the software. + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* + * !!GlobalInfo + * product: Pins v4.1 + * processor: MIMXRT1062xxxxA + * package_id: MIMXRT1062DVL6A + * mcu_data: ksdk2_0 + * processor_version: 0.0.11 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + + + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins( void ) +{ + EnetPins(); + I2CPins(); + spiPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* + * I2CPins: + * - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} + * - pin_list: + * - {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, slew_rate: Fast, software_input_on: Enable, open_drain: Enable, drive_strength: R0_7, + * pull_up_down_config: Pull_Up_22K_Ohm} + * - {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, slew_rate: Fast, software_input_on: Enable, open_drain: Enable, drive_strength: R0_7, + * pull_keeper_select: Keeper, pull_up_down_config: Pull_Up_22K_Ohm} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : I2CPins + * Description : Configures pin routing and optionally pin electrical features for I2C + * + * END ****************************************************************************************************************/ +void I2CPins( void ) +{ + CLOCK_EnableClock( kCLOCK_Iomuxc ); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */ + 0xD8B0u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/7 + * Speed Field: medium(100MHz) + * Open Drain Enable Field: Open Drain Enabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 22K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */ + 0xD8B0u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/7 + * Speed Field: medium(100MHz) + * Open Drain Enable Field: Open Drain Enabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 22K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ +} + + +void EnetPins( void ) +{ + CLOCK_EnableClock( kCLOCK_Iomuxc ); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U ); /* Software Input On Field: Input Path is determined by functionality */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u ); /* Slew Rate Field: Slow Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: medium(100MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u ); /* Slew Rate Field: Slow Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: medium(100MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: low(50MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Disabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ + 0xB829u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/5 + * Speed Field: low(50MHz) + * Open Drain Enable Field: Open Drain Enabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Pull + * Pull Up / Down Config. Field: 100K Ohm Pull Up + * Hyst. Enable Field: Hysteresis Disabled */ +} + +void spiPins( void ) +{ + CLOCK_EnableClock( kCLOCK_Iomuxc ); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, /* GPIO_SD_B1_05 is configured as FLEXSPIA_DQS */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_SD_B1_05 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, /* GPIO_SD_B1_06 is configured as FLEXSPIA_SS0_B */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_SD_B1_06 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, /* GPIO_SD_B1_07 is configured as FLEXSPIA_SCLK */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_SD_B1_07 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, /* GPIO_SD_B1_08 is configured as FLEXSPIA_DATA00 */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_SD_B1_08 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, /* GPIO_SD_B1_09 is configured as FLEXSPIA_DATA01 */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_SD_B1_09 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, /* GPIO_SD_B1_10 is configured as FLEXSPIA_DATA02 */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_SD_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, /* GPIO_SD_B1_11 is configured as FLEXSPIA_DATA03 */ + 1U ); /* Software Input On Field: Force input path of pad GPIO_SD_B1_11 */ + + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, /* GPIO_SD_B1_05 PAD functional properties : */ + 0x10F1u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, /* GPIO_SD_B1_06 PAD functional properties : */ + 0x10F1u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, /* GPIO_SD_B1_07 PAD functional properties : */ + 0x10F1u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, /* GPIO_SD_B1_08 PAD functional properties : */ + 0x10F1u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, /* GPIO_SD_B1_09 PAD functional properties : */ + 0x10F1u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, /* GPIO_SD_B1_10 PAD functional properties : */ + 0x10F1u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, /* GPIO_SD_B1_11 PAD functional properties : */ + 0x10F1u ); /* Slew Rate Field: Fast Slew Rate + * Drive Strength Field: R0/6 + * Speed Field: max(200MHz) + * Open Drain Enable Field: Open Drain Disabled + * Pull / Keep Enable Field: Pull/Keeper Enabled + * Pull / Keep Select Field: Keeper + * Pull Up / Down Config. Field: 100K Ohm Pull Down + * Hyst. Enable Field: Hysteresis Disabled */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/examples/evkbmimxrt1060/sesip/board/pin_mux.h b/examples/evkbmimxrt1060/sesip/board/pin_mux.h new file mode 100644 index 0000000..e891009 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/board/pin_mux.h @@ -0,0 +1,74 @@ +/* Copyright 2018-2019 NXP + * + * This software is owned or controlled by NXP and may only be used + * strictly in accordance with the applicable license terms. By expressly + * accepting such terms or by downloading, installing, activating and/or + * otherwise using the software, you are agreeing that you have read, and + * that you agree to comply with and are bound by, such license terms. If + * you do not agree to be bound by the applicable license terms, then you + * may not retain, install, activate or otherwise use the software. + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ +/* *INDENT-OFF* */ +#if defined( __cplusplus ) +extern "C" { +#endif +/* *INDENT-ON* */ + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins( void ); + + +/*! + * @brief Configures pin routing and optionally pin electrical features for I2C + * + */ +void I2CPins( void ); +void EnetPins( void ); +void spiPins( void ); + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) +} +#endif +/* *INDENT-ON* */ + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/examples/evkbmimxrt1060/sesip/demo_restrictions.c b/examples/evkbmimxrt1060/sesip/demo_restrictions.c new file mode 100644 index 0000000..e69de29 diff --git a/examples/evkbmimxrt1060/sesip/include/FreeRTOSConfig.h b/examples/evkbmimxrt1060/sesip/include/FreeRTOSConfig.h new file mode 100644 index 0000000..eabd876 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/include/FreeRTOSConfig.h @@ -0,0 +1,225 @@ +/* + * FreeRTOS Kernel V10.4.3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- +* Application specific definitions. +* +* These definitions should be adjusted for your particular hardware and +* application requirements. +* +* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE +* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. +* +* See http://www.freertos.org/a00110.html. +*----------------------------------------------------------*/ + +/* Ensure stdint is only used by the compiler, and not the assembler. */ +#if defined( __ICCARM__ ) || defined( __ARMCC_VERSION ) || defined( __GNUC__ ) +extern uint32_t SystemCoreClock; +extern void print_string( const char * string ); +extern void vLoggingPrintf( const char * pcFormat, + ... ); +#endif + + +#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0 +#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 +#define configTOTAL_MPU_REGIONS 16 + +#define configSUPPORT_STATIC_ALLOCATION 1 + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_TICKLESS_IDLE 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 1 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMAX_PRIORITIES ( 9 ) +#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 90 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 80 * 1024 ) ) /* 100 Kbytes. */ +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH ( 4096 ) + +#define configCOMMAND_INT_MAX_OUTPUT_SIZE ( 512 ) + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 + + +/* Normal assert() semantics without relying on the provision of an assert.h + * header file. */ +#define configASSERT( x ) \ + if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ; ; ) {; } \ + } + +/* Map the FreeRTOS printf() to the logging task printf. */ +extern void vLoggingPrintf( const char * pcFormat, + ... ); +#define configPRINTF( x ) vLoggingPrintf x + +/* Non-format version thread-safe print. */ +extern void vLoggingPrint( const char * pcMessage ); +#define configPRINT( X ) vLoggingPrint( X ) + +/* Map the logging task's printf to the board specific output function. */ +extern int DbgConsole_Printf( const char * fmt_s, + ... ); +#define configPRINT_STRING DbgConsole_Printf + +/* Sets the length of the buffers into which logging messages are written - so + * also defines the maximum length of each log message. */ +#define configLOGGING_MAX_MESSAGE_LENGTH 512 + +/* Set to 1 to prepend each log message with a message number, the task name, + * and a time stamp. */ +#define configLOGGING_INCLUDE_TIME_AND_TASK_NAME 1 + +/* Demo specific macros that allow the application writer to insert code to be + * executed immediately before the MCU's STOP low power mode is entered and exited + * respectively. These macros are in addition to the standard + * configPRE_SLEEP_PROCESSING() and configPOST_SLEEP_PROCESSING() macros, which are + * called pre and post the low power SLEEP mode being entered and exited. These + * macros can be used to turn turn off and on IO, clocks, the Flash etc. to obtain + * the lowest power possible while the tick is off. */ +#if defined( __ICCARM__ ) || defined( __CC_ARM ) || defined( __ARMCC_VERSION ) || defined( __GNUC__ ) +void vMainPreStopProcessing( void ); +void vMainPostStopProcessing( void ); +#endif /* defined(__ICCARM__) || defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) */ + +#define configPRE_STOP_PROCESSING vMainPreStopProcessing +#define configPOST_STOP_PROCESSING vMainPostStopProcessing + + +/* IMPORTANT: This define MUST be commented when used with STM32Cube firmware, + * to prevent overwriting SysTick_Handler defined within STM32Cube HAL. */ +/* #define xPortSysTickHandler SysTick_Handler */ + +/********************************************* + * FreeRTOS specific demos + ********************************************/ + +/* The address of an echo server that will be used by the two demo echo client + * tasks. + * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_Echo_Clients.html + * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/UDP_Echo_Clients.html */ +#define configECHO_SERVER_ADDR0 192 +#define configECHO_SERVER_ADDR1 168 +#define configECHO_SERVER_ADDR2 2 +#define configECHO_SERVER_ADDR3 6 +#define configTCP_ECHO_CLIENT_PORT 7 + +/* Prevent the assembler seeing code it doesn't understand. */ +#ifdef __ICCARM__ +/* Logging task definitions. */ +extern void vMainUARTPrintString( char * pcString ); + +extern int iMainRand32( void ); + +/* Pseudo random number generator, just used by demos so does not have to be + * secure. Do not use the standard C library rand() function as it can cause + * unexpected behaviour, such as calls to malloc(). */ +#define configRAND32() iMainRand32() +#endif + + + +#if defined( __ICCARM__ ) || defined( __CC_ARM ) || defined( __GNUC__ ) +/* Clock manager provides in this variable system core clock frequency */ +#include +extern uint32_t SystemCoreClock; +#endif + +/* Interrupt nesting behaviour configuration. Cortex-M specific. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 4 /* 15 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" + * function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ( ( 1U << ( configPRIO_BITS ) ) - 1 ) + +/* The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL + * INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER + * PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +* to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS + * standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/examples/evkbmimxrt1060/sesip/include/demo_config.h b/examples/evkbmimxrt1060/sesip/include/demo_config.h new file mode 100644 index 0000000..d5dd76b --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/include/demo_config.h @@ -0,0 +1,285 @@ +/* + * FreeRTOS V202111.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEMO_CONFIG_H +#define DEMO_CONFIG_H + +/* FreeRTOS include. */ +#include "FreeRTOS.h" + +/**************************************************/ +/******* DO NOT CHANGE the following order ********/ +/**************************************************/ + +/* Include logging header files and define logging macros in the following order: + * 1. Include the header file "logging_levels.h". + * 2. Define the LIBRARY_LOG_NAME and LIBRARY_LOG_LEVEL macros depending on + * the logging configuration for DEMO. + * 3. Include the header file "logging_stack.h", if logging is enabled for DEMO. + */ + +#include "logging_levels.h" + +/* Logging configuration for the Demo. */ +#ifndef LIBRARY_LOG_NAME +#define LIBRARY_LOG_NAME "MQTTDemo" +#endif + +#ifndef LIBRARY_LOG_LEVEL +#define LIBRARY_LOG_LEVEL LOG_INFO +#endif + +#include "logging.h" + +/************ End of logging configuration ****************/ + +/** + * @brief The MQTT client identifier used in this example. Each client identifier + * must be unique; so edit as required to ensure that no two clients connecting to + * the same broker use the same client identifier. + * + *!!! Please note a #defined constant is used for convenience of demonstration + *!!! only. Production devices can use something unique to the device that can + *!!! be read by software, such as a production serial number, instead of a + *!!! hard coded constant. + * + * #define democonfigCLIENT_IDENTIFIER "insert here." + */ +#define democonfigCLIENT_IDENTIFIER "NXP_RT_1060" + +/** + * @brief Endpoint of the MQTT broker to connect to. + * + * This demo application can be run with any MQTT broker, that supports mutual + * authentication. + * + * For AWS IoT MQTT broker, this is the Thing's REST API Endpoint. + * + * @note Your AWS IoT Core endpoint can be found in the AWS IoT console under + * Settings/Custom Endpoint, or using the describe-endpoint REST API (with + * AWS CLI command line tool). + * + * @note If you would like to setup an MQTT broker for running this demo, + * please see `mqtt_broker_setup.txt`. + * + * #define democonfigMQTT_BROKER_ENDPOINT "...insert here..." + */ +#define democonfigMQTT_BROKER_ENDPOINT "a31zvyed820ljz-ats.iot.us-east-1.amazonaws.com" + +/** + * @brief The port to use for the demo. + * + * In general, port 8883 is for secured MQTT connections. + * + * @note Port 443 requires use of the ALPN TLS extension with the ALPN protocol + * name. Using ALPN with this demo would require additional changes, including + * setting the `pAlpnProtos` member of the `NetworkCredentials_t` struct before + * forming the TLS connection. When using port 8883, ALPN is not required. + * + * #define democonfigMQTT_BROKER_PORT ( insert here. ) + */ +#define democonfigMQTT_BROKER_PORT 8883 + +/** + * @brief Server's root CA certificate. + * + * For AWS IoT MQTT broker, this certificate is used to identify the AWS IoT + * server and is publicly available. Refer to the AWS documentation available + * in the link below. + * https://docs.aws.amazon.com/iot/latest/developerguide/server-authentication.html#server-authentication-certs + * + * @note This certificate should be PEM-encoded. + * + * Must include the PEM header and footer: + * "-----BEGIN CERTIFICATE-----\n"\ + * "...base64 data...\n"\ + * "-----END CERTIFICATE-----\n" + * + * + */ +#define democonfigROOT_CA_PEM \ + "-----BEGIN CERTIFICATE-----\n" \ + "MIIDQTCCAimgAwIBAgITBmyfz5m/jAo54vB4ikPmljZbyjANBgkqhkiG9w0BAQsF\n" \ + "ADA5MQswCQYDVQQGEwJVUzEPMA0GA1UEChMGQW1hem9uMRkwFwYDVQQDExBBbWF6\n" \ + "b24gUm9vdCBDQSAxMB4XDTE1MDUyNjAwMDAwMFoXDTM4MDExNzAwMDAwMFowOTEL\n" \ + "MAkGA1UEBhMCVVMxDzANBgNVBAoTBkFtYXpvbjEZMBcGA1UEAxMQQW1hem9uIFJv\n" \ + "b3QgQ0EgMTCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBALJ4gHHKeNXj\n" \ + "ca9HgFB0fW7Y14h29Jlo91ghYPl0hAEvrAIthtOgQ3pOsqTQNroBvo3bSMgHFzZM\n" \ + "9O6II8c+6zf1tRn4SWiw3te5djgdYZ6k/oI2peVKVuRF4fn9tBb6dNqcmzU5L/qw\n" \ + "IFAGbHrQgLKm+a/sRxmPUDgH3KKHOVj4utWp+UhnMJbulHheb4mjUcAwhmahRWa6\n" \ + "VOujw5H5SNz/0egwLX0tdHA114gk957EWW67c4cX8jJGKLhD+rcdqsq08p8kDi1L\n" \ + "93FcXmn/6pUCyziKrlA4b9v7LWIbxcceVOF34GfID5yHI9Y/QCB/IIDEgEw+OyQm\n" \ + "jgSubJrIqg0CAwEAAaNCMEAwDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMC\n" \ + "AYYwHQYDVR0OBBYEFIQYzIU07LwMlJQuCFmcx7IQTgoIMA0GCSqGSIb3DQEBCwUA\n" \ + "A4IBAQCY8jdaQZChGsV2USggNiMOruYou6r4lK5IpDB/G/wkjUu0yKGX9rbxenDI\n" \ + "U5PMCCjjmCXPI6T53iHTfIUJrU6adTrCC2qJeHZERxhlbI1Bjjt/msv0tadQ1wUs\n" \ + "N+gDS63pYaACbvXy8MWy7Vu33PqUXHeeE6V/Uq2V8viTO96LXFvKWlJbYK8U90vv\n" \ + "o/ufQJVtMVT8QtPHRh8jrdkPSHCa2XV4cdFyQzR1bldZwgJcJmApzyMZFo6IQ6XU\n" \ + "5MsI+yMRQ+hDKXJioaldXgjUkK642M4UwtBV8ob2xJNDd2ZhwLnoQdeXeGADbkpy\n" \ + "rqXRfboQnoZsG4q5WTP468SQvvG5\n" \ + "-----END CERTIFICATE-----\n" \ + "-----BEGIN CERTIFICATE-----\n" \ + "MIIE0zCCA7ugAwIBAgIQGNrRniZ96LtKIVjNzGs7SjANBgkqhkiG9w0BAQUFADCB\n" \ + "yjELMAkGA1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQL\n" \ + "ExZWZXJpU2lnbiBUcnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNiBWZXJp\n" \ + "U2lnbiwgSW5jLiAtIEZvciBhdXRob3JpemVkIHVzZSBvbmx5MUUwQwYDVQQDEzxW\n" \ + "ZXJpU2lnbiBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5IENlcnRpZmljYXRpb24gQXV0\n" \ + "aG9yaXR5IC0gRzUwHhcNMDYxMTA4MDAwMDAwWhcNMzYwNzE2MjM1OTU5WjCByjEL\n" \ + "MAkGA1UEBhMCVVMxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZW\n" \ + "ZXJpU2lnbiBUcnVzdCBOZXR3b3JrMTowOAYDVQQLEzEoYykgMjAwNiBWZXJpU2ln\n" \ + "biwgSW5jLiAtIEZvciBhdXRob3JpemVkIHVzZSBvbmx5MUUwQwYDVQQDEzxWZXJp\n" \ + "U2lnbiBDbGFzcyAzIFB1YmxpYyBQcmltYXJ5IENlcnRpZmljYXRpb24gQXV0aG9y\n" \ + "aXR5IC0gRzUwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCvJAgIKXo1\n" \ + "nmAMqudLO07cfLw8RRy7K+D+KQL5VwijZIUVJ/XxrcgxiV0i6CqqpkKzj/i5Vbex\n" \ + "t0uz/o9+B1fs70PbZmIVYc9gDaTY3vjgw2IIPVQT60nKWVSFJuUrjxuf6/WhkcIz\n" \ + "SdhDY2pSS9KP6HBRTdGJaXvHcPaz3BJ023tdS1bTlr8Vd6Gw9KIl8q8ckmcY5fQG\n" \ + "BO+QueQA5N06tRn/Arr0PO7gi+s3i+z016zy9vA9r911kTMZHRxAy3QkGSGT2RT+\n" \ + "rCpSx4/VBEnkjWNHiDxpg8v+R70rfk/Fla4OndTRQ8Bnc+MUCH7lP59zuDMKz10/\n" \ + "NIeWiu5T6CUVAgMBAAGjgbIwga8wDwYDVR0TAQH/BAUwAwEB/zAOBgNVHQ8BAf8E\n" \ + "BAMCAQYwbQYIKwYBBQUHAQwEYTBfoV2gWzBZMFcwVRYJaW1hZ2UvZ2lmMCEwHzAH\n" \ + "BgUrDgMCGgQUj+XTGoasjY5rw8+AatRIGCx7GS4wJRYjaHR0cDovL2xvZ28udmVy\n" \ + "aXNpZ24uY29tL3ZzbG9nby5naWYwHQYDVR0OBBYEFH/TZafC3ey78DAJ80M5+gKv\n" \ + "MzEzMA0GCSqGSIb3DQEBBQUAA4IBAQCTJEowX2LP2BqYLz3q3JktvXf2pXkiOOzE\n" \ + "p6B4Eq1iDkVwZMXnl2YtmAl+X6/WzChl8gGqCBpH3vn5fJJaCGkgDdk+bW48DW7Y\n" \ + "5gaRQBi5+MHt39tBquCWIMnNZBU4gcmU7qKEKQsTb47bDN0lAtukixlE0kF6BWlK\n" \ + "WE9gyn6CagsCqiUXObXbf+eEZSqVir2G3l6BFoMtEMze/aiCKm0oHw0LxOXnGiYZ\n" \ + "4fQRbxC1lfznQgUy286dUV4otp6F01vvpX1FQHKOtw5rDgb7MzVIcbidJ4vEZV8N\n" \ + "hnacRHr2lVz2XTIIM6RUthg/aFzyQkqFOFSDX9HoLPKsEdao7WNq\n" \ + "-----END CERTIFICATE-----\n" + +#define democonfigROOT_CA_PEM_ECC_256 \ + "-----BEGIN CERTIFICATE-----\n" \ + "MIIBtjCCAVugAwIBAgITBmyf1XSXNmY/Owua2eiedgPySjAKBggqhkjOPQQDAjA5\n" \ + "MQswCQYDVQQGEwJVUzEPMA0GA1UEChMGQW1hem9uMRkwFwYDVQQDExBBbWF6b24g\n" \ + "Um9vdCBDQSAzMB4XDTE1MDUyNjAwMDAwMFoXDTQwMDUyNjAwMDAwMFowOTELMAkG\n" \ + "A1UEBhMCVVMxDzANBgNVBAoTBkFtYXpvbjEZMBcGA1UEAxMQQW1hem9uIFJvb3Qg\n" \ + "Q0EgMzBZMBMGByqGSM49AgEGCCqGSM49AwEHA0IABCmXp8ZBf8ANm+gBG1bG8lKl\n" \ + "ui2yEujSLtf6ycXYqm0fc4E7O5hrOXwzpcVOho6AF2hiRVd9RFgdszflZwjrZt6j\n" \ + "QjBAMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQDAgGGMB0GA1UdDgQWBBSr\n" \ + "ttvXBp43rDCGB5Fwx5zEGbF4wDAKBggqhkjOPQQDAgNJADBGAiEA4IWSoxe3jfkr\n" \ + "BqWTrBqYaGFy+uGh0PsceGCmQ5nFuMQCIQCcAu/xlJyzlvnrxir4tiz+OpAUFteM\n" \ + "YyRIHN8wfdVoOw==\n" \ + "-----END CERTIFICATE-----\n" + +/** + * @brief An option to disable Server Name Indication. + * + * @note When using a local Mosquitto server setup, SNI needs to be disabled + * for an MQTT broker that only has an IP address but no hostname. However, + * SNI should be enabled whenever possible. + */ +#define democonfigDISABLE_SNI ( pdFALSE ) + +/** + * @brief Configuration that indicates if the demo connection is made to the AWS IoT Core MQTT broker. + * + * If username/password based authentication is used, the demo will use appropriate TLS ALPN and + * SNI configurations as required for the Custom Authentication feature of AWS IoT. + * For more information, refer to the following documentation: + * https://docs.aws.amazon.com/iot/latest/developerguide/custom-auth.html#custom-auth-mqtt + * + * #define democonfigUSE_AWS_IOT_CORE_BROKER ( 1 ) + */ +#define democonfigUSE_AWS_IOT_CORE_BROKER ( 1 ) + +/** + * @brief The username value for authenticating client to the MQTT broker when + * username/password based client authentication is used. + * + * For AWS IoT MQTT broker, refer to the AWS IoT documentation below for + * details regarding client authentication with a username and password. + * https://docs.aws.amazon.com/iot/latest/developerguide/custom-authentication.html + * An authorizer setup needs to be done, as mentioned in the above link, to use + * username/password based client authentication. + * + * #define democonfigCLIENT_USERNAME "...insert here..." + */ + +/** + * @brief The password value for authenticating client to the MQTT broker when + * username/password based client authentication is used. + * + * For AWS IoT MQTT broker, refer to the AWS IoT documentation below for + * details regarding client authentication with a username and password. + * https://docs.aws.amazon.com/iot/latest/developerguide/custom-authentication.html + * An authorizer setup needs to be done, as mentioned in the above link, to use + * username/password based client authentication. + * + * #define democonfigCLIENT_PASSWORD "...insert here..." + */ + +/** + * @brief The name of the operating system that the application is running on. + * The current value is given as an example. Please update for your specific + * operating system. + */ +#define democonfigOS_NAME "FreeRTOS" + +/** + * @brief The version of the operating system that the application is running + * on. The current value is given as an example. Please update for your specific + * operating system version. + */ +#define democonfigOS_VERSION tskKERNEL_VERSION_NUMBER + +/** + * @brief The name of the hardware platform the application is running on. The + * current value is given as an example. Please update for your specific + * hardware platform. + */ +#define democonfigHARDWARE_PLATFORM_NAME "NXPRT1060" + +/** + * @brief The name of the MQTT library used and its version, following an "@" + * symbol. + */ +#include "core_mqtt.h" /* Include coreMQTT header for MQTT_LIBRARY_VERSION macro. */ +#define democonfigMQTT_LIB "core-mqtt@"MQTT_LIBRARY_VERSION + +/** + * @brief The MQTT metrics string expected by AWS IoT. + */ +#define AWS_IOT_METRICS_STRING \ + "?SDK=" democonfigOS_NAME "&Version=" democonfigOS_VERSION \ + "&Platform=" democonfigHARDWARE_PLATFORM_NAME "&MQTTLib=" democonfigMQTT_LIB + +/** + * @brief Set the stack size of the main demo task. + * + * In the Windows port, this stack only holds a structure. The actual + * stack is created by an operating system thread. + */ +#define democonfigDEMO_STACKSIZE configMINIMAL_STACK_SIZE + +/** + * @brief Set the stack size of the main demo task. + * + * In the Windows port, this stack only holds a structure. The actual + * stack is created by an operating system thread. + */ +#define democonfigDEMO_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +#endif /* DEMO_CONFIG_H */ diff --git a/examples/evkbmimxrt1060/sesip/include/freertos_tasks_c_additions.h b/examples/evkbmimxrt1060/sesip/include/freertos_tasks_c_additions.h new file mode 100644 index 0000000..59f84da --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/include/freertos_tasks_c_additions.h @@ -0,0 +1,126 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* freertos_tasks_c_additions.h Rev. 1.3 */ +#ifndef FREERTOS_TASKS_C_ADDITIONS_H +#define FREERTOS_TASKS_C_ADDITIONS_H + +#include + +#if ( configUSE_TRACE_FACILITY == 0 ) +#error "configUSE_TRACE_FACILITY must be enabled" +#endif + +#define FREERTOS_DEBUG_CONFIG_MAJOR_VERSION 1 +#define FREERTOS_DEBUG_CONFIG_MINOR_VERSION 3 + +/* NOTE!! + * Default to a FreeRTOS version which didn't include these macros. FreeRTOS + * v7.5.3 is used here. + */ +#ifndef tskKERNEL_VERSION_BUILD +#define tskKERNEL_VERSION_BUILD 3 +#endif +#ifndef tskKERNEL_VERSION_MINOR +#define tskKERNEL_VERSION_MINOR 5 +#endif +#ifndef tskKERNEL_VERSION_MAJOR +#define tskKERNEL_VERSION_MAJOR 7 +#endif + +/* NOTE!! + * The configFRTOS_MEMORY_SCHEME macro describes the heap scheme using a value + * 1 - 5 which corresponds to the following schemes: + * + * heap_1 - the very simplest, does not permit memory to be freed + * heap_2 - permits memory to be freed, but not does coalescence adjacent free + * blocks. + * heap_3 - simply wraps the standard malloc() and free() for thread safety + * heap_4 - coalesces adjacent free blocks to avoid fragmentation. Includes + * absolute address placement option + * heap_5 - as per heap_4, with the ability to span the heap across + * multiple nonOadjacent memory areas + */ +#ifndef configFRTOS_MEMORY_SCHEME +#define configFRTOS_MEMORY_SCHEME 3 /* thread safe malloc */ +#endif + +#if ( ( configFRTOS_MEMORY_SCHEME > 5 ) || ( configFRTOS_MEMORY_SCHEME < 1 ) ) +#error "Invalid configFRTOS_MEMORY_SCHEME setting!" +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ + +extern const uint8_t FreeRTOSDebugConfig[]; + +/* NOTES!! + * IAR documentation is confusing. It suggests the data must be statically + * linked, and the #pragma placed immediately before the symbol definition. + * The IAR supplied examples violate both "rules", so this is a best guess. + */ + +#if ( tskKERNEL_VERSION_MAJOR >= 10 ) && ( tskKERNEL_VERSION_MINOR >= 2 ) +#if defined( __GNUC__ ) +char * const portArch_Name __attribute__( ( section( ".rodata" ) ) ) = portARCH_NAME; +#elif defined( __CC_ARM ) || defined( __ARMCC_VERSION ) +char * const portArch_Name __attribute__( ( used ) ) = portARCH_NAME; +#elif defined( __IAR_SYSTEMS_ICC__ ) +char * const portArch_Name = portARCH_NAME; +#pragma required=portArch_Name +#endif +#else +char * const portArch_Name = NULL; +#endif // tskKERNEL_VERSION_MAJOR + +#if defined( __GNUC__ ) +const uint8_t FreeRTOSDebugConfig[] __attribute__( ( section( ".rodata" ) ) ) = +#elif defined( __CC_ARM ) || defined( __ARMCC_VERSION ) +const uint8_t FreeRTOSDebugConfig[] __attribute__( ( used ) ) = +#elif defined( __IAR_SYSTEMS_ICC__ ) +#pragma required=FreeRTOSDebugConfig +const uint8_t FreeRTOSDebugConfig[] = +#endif +{ + FREERTOS_DEBUG_CONFIG_MAJOR_VERSION, + FREERTOS_DEBUG_CONFIG_MINOR_VERSION, + tskKERNEL_VERSION_MAJOR, + tskKERNEL_VERSION_MINOR, + tskKERNEL_VERSION_BUILD, + configFRTOS_MEMORY_SCHEME, + offsetof( struct tskTaskControlBlock, pxTopOfStack ), +#if ( tskKERNEL_VERSION_MAJOR > 8 ) + offsetof( struct tskTaskControlBlock, xStateListItem ), +#else + offsetof( struct tskTaskControlBlock, xGenericListItem ), +#endif + offsetof( struct tskTaskControlBlock, xEventListItem ), + offsetof( struct tskTaskControlBlock, pxStack ), + offsetof( struct tskTaskControlBlock, pcTaskName ), + offsetof( struct tskTaskControlBlock, uxTCBNumber ), + offsetof( struct tskTaskControlBlock, uxTaskNumber ), + configMAX_TASK_NAME_LEN, + configMAX_PRIORITIES, + configENABLE_MPU, + configENABLE_FPU, + configENABLE_TRUSTZONE, + configRUN_FREERTOS_SECURE_ONLY, + 0, /* 32-bit align */ + 0, 0, 0, 0 /* padding */ +} + +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ + +#endif // FREERTOS_TASKS_C_ADDITIONS_H diff --git a/examples/evkbmimxrt1060/sesip/include/fsl_sss_ftr.h b/examples/evkbmimxrt1060/sesip/include/fsl_sss_ftr.h new file mode 100644 index 0000000..af34cf1 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/include/fsl_sss_ftr.h @@ -0,0 +1,716 @@ +/* + * + * Copyright 2018-2020 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef SSS_APIS_INC_FSL_SSS_FTR_H_ +#define SSS_APIS_INC_FSL_SSS_FTR_H_ + +/* ************************************************************************** */ +/* Defines */ +/* ************************************************************************** */ + +/* clang-format off */ + + +/* # CMake Features : Start */ + + +/** Applet : The Secure Element Applet + * + * You can compile host library for different Applets listed below. + * Please note, some of these Applets may be for NXP Internal use only. + */ + +/** Compiling without any Applet Support */ +#define SSS_HAVE_APPLET_NONE 0 + +/** A71CH (ECC) */ +#define SSS_HAVE_APPLET_A71CH 0 + +/** A71CL (RSA) */ +#define SSS_HAVE_APPLET_A71CL 0 + +/** Similar to A71CH */ +#define SSS_HAVE_APPLET_A71CH_SIM 0 + +/** SE050 Type A (ECC) */ +#define SSS_HAVE_APPLET_SE05X_A 0 + +/** SE050 Type B (RSA) */ +#define SSS_HAVE_APPLET_SE05X_B 0 + +/** SE050 (Super set of A + B) */ +#define SSS_HAVE_APPLET_SE05X_C 1 + +/** SE050 (Similar to A71CL) */ +#define SSS_HAVE_APPLET_SE05X_L 0 + +/** SE051UWB (Similar to SE05x) */ +#define SSS_HAVE_APPLET_SE051_UWB 0 + +/** AUTH */ +#define SSS_HAVE_APPLET_AUTH 0 + +/** NXP Internal testing Applet */ +#define SSS_HAVE_APPLET_LOOPBACK 0 + +#if ( ( 0 \ + + SSS_HAVE_APPLET_NONE \ + + SSS_HAVE_APPLET_A71CH \ + + SSS_HAVE_APPLET_A71CL \ + + SSS_HAVE_APPLET_A71CH_SIM \ + + SSS_HAVE_APPLET_SE05X_A \ + + SSS_HAVE_APPLET_SE05X_B \ + + SSS_HAVE_APPLET_SE05X_C \ + + SSS_HAVE_APPLET_SE05X_L \ + + SSS_HAVE_APPLET_SE051_UWB \ + + SSS_HAVE_APPLET_AUTH \ + + SSS_HAVE_APPLET_LOOPBACK \ + ) > 1 ) +#error "Enable only one of 'Applet'" +#endif /* if ( ( 0 + SSS_HAVE_APPLET_NONE + SSS_HAVE_APPLET_A71CH + SSS_HAVE_APPLET_A71CL + SSS_HAVE_APPLET_A71CH_SIM + SSS_HAVE_APPLET_SE05X_A + SSS_HAVE_APPLET_SE05X_B + SSS_HAVE_APPLET_SE05X_C + SSS_HAVE_APPLET_SE05X_L + SSS_HAVE_APPLET_SE051_UWB + SSS_HAVE_APPLET_AUTH + SSS_HAVE_APPLET_LOOPBACK ) > 1 ) */ + + +#if ( ( 0 \ + + SSS_HAVE_APPLET_NONE \ + + SSS_HAVE_APPLET_A71CH \ + + SSS_HAVE_APPLET_A71CL \ + + SSS_HAVE_APPLET_A71CH_SIM \ + + SSS_HAVE_APPLET_SE05X_A \ + + SSS_HAVE_APPLET_SE05X_B \ + + SSS_HAVE_APPLET_SE05X_C \ + + SSS_HAVE_APPLET_SE05X_L \ + + SSS_HAVE_APPLET_SE051_UWB \ + + SSS_HAVE_APPLET_AUTH \ + + SSS_HAVE_APPLET_LOOPBACK \ + ) == 0 ) +#error "Enable at-least one of 'Applet'" +#endif /* if ( ( 0 + SSS_HAVE_APPLET_NONE + SSS_HAVE_APPLET_A71CH + SSS_HAVE_APPLET_A71CL + SSS_HAVE_APPLET_A71CH_SIM + SSS_HAVE_APPLET_SE05X_A + SSS_HAVE_APPLET_SE05X_B + SSS_HAVE_APPLET_SE05X_C + SSS_HAVE_APPLET_SE05X_L + SSS_HAVE_APPLET_SE051_UWB + SSS_HAVE_APPLET_AUTH + SSS_HAVE_APPLET_LOOPBACK ) == 0 ) */ + + + +/** SE05X_Ver : SE05X Applet version. + * + * Selection of Applet version 03_XX enables SE050 features. + * Selection of Applet version 06_00 enables SE051 features. + * + */ + +/** SE050 */ +#define SSS_HAVE_SE05X_VER_03_XX 1 + +/** SE051 */ +#define SSS_HAVE_SE05X_VER_06_00 0 + +#if ( ( 0 \ + + SSS_HAVE_SE05X_VER_03_XX \ + + SSS_HAVE_SE05X_VER_06_00 \ + ) > 1 ) +#error "Enable only one of 'SE05X_Ver'" +#endif + + +#if ( ( 0 \ + + SSS_HAVE_SE05X_VER_03_XX \ + + SSS_HAVE_SE05X_VER_06_00 \ + ) == 0 ) +#error "Enable at-least one of 'SE05X_Ver'" +#endif + + + +/** HostCrypto : Counterpart Crypto on Host + * + * What is being used as a cryptographic library on the host. + * As of now only OpenSSL / mbedTLS is supported + */ + +/** Use mbedTLS as host crypto */ +#define SSS_HAVE_HOSTCRYPTO_MBEDTLS 0 + +/** Use mbed-crypto as host crypto + * Required for ARM-PSA / TF-M */ +#define SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO 0 + +/** Use OpenSSL as host crypto */ +#define SSS_HAVE_HOSTCRYPTO_OPENSSL 0 + +/** User Implementation of Host Crypto + * e.g. Files at ``sss/src/user/crypto`` have low level AES/CMAC primitives. + * The files at ``sss/src/user`` use those primitives. + * This becomes an example for users with their own AES Implementation + * This then becomes integration without mbedTLS/OpenSSL for SCP03 / AESKey. + * + * .. note:: ECKey abstraction is not implemented/available yet. */ +#define SSS_HAVE_HOSTCRYPTO_USER 0 + +/** NO Host Crypto + * Note, this is unsecure and only provided for experimentation + * on platforms that do not have an mbedTLS PORT + * Many :ref:`sssftr-control` have to be disabled to have a valid build. */ +#define SSS_HAVE_HOSTCRYPTO_NONE 0 + +#if ( ( 0 \ + + SSS_HAVE_HOSTCRYPTO_MBEDTLS \ + + SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO \ + + SSS_HAVE_HOSTCRYPTO_OPENSSL \ + + SSS_HAVE_HOSTCRYPTO_USER \ + + SSS_HAVE_HOSTCRYPTO_NONE \ + ) > 1 ) +#error "Enable only one of 'HostCrypto'" +#endif + + +#if ( ( 0 \ + + SSS_HAVE_HOSTCRYPTO_MBEDTLS \ + + SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO \ + + SSS_HAVE_HOSTCRYPTO_OPENSSL \ + + SSS_HAVE_HOSTCRYPTO_USER \ + + SSS_HAVE_HOSTCRYPTO_NONE \ + ) == 0 ) +#error "Enable at-least one of 'HostCrypto'" +#endif + + + +/** mbedTLS_ALT : ALT Engine implementation for mbedTLS + * + * When set to None, mbedTLS would not use ALT Implementation to connect to / use Secure Element. + * This needs to be set to SSS for Cloud Demos over SSS APIs + */ + +/** Use SSS Layer ALT implementation */ +#define SSS_HAVE_MBEDTLS_ALT_SSS 1 + +/** Legacy implementation */ +#define SSS_HAVE_MBEDTLS_ALT_A71CH 0 + +/** Not using any mbedTLS_ALT + * + * When this is selected, cloud demos can not work with mbedTLS */ +#define SSS_HAVE_MBEDTLS_ALT_NONE 0 + +#if ( ( 0 \ + + SSS_HAVE_MBEDTLS_ALT_SSS \ + + SSS_HAVE_MBEDTLS_ALT_A71CH \ + + SSS_HAVE_MBEDTLS_ALT_NONE \ + ) > 1 ) +#error "Enable only one of 'mbedTLS_ALT'" +#endif + + +#if ( ( 0 \ + + SSS_HAVE_MBEDTLS_ALT_SSS \ + + SSS_HAVE_MBEDTLS_ALT_A71CH \ + + SSS_HAVE_MBEDTLS_ALT_NONE \ + ) == 0 ) +#error "Enable at-least one of 'mbedTLS_ALT'" +#endif + + + +/** SCP : Secure Channel Protocol + * + * In case we enable secure channel to Secure Element, which interface to be used. + */ + +/** */ +#define SSS_HAVE_SCP_NONE 0 + +/** Use SSS Layer for SCP. Used for SE050 family. */ +#define SSS_HAVE_SCP_SCP03_SSS 1 + +/** Use Host Crypto Layer for SCP03. Legacy implementation. Used for older demos of A71CH Family. */ +#define SSS_HAVE_SCP_SCP03_HOSTCRYPTO 0 + +#if ( ( 0 \ + + SSS_HAVE_SCP_NONE \ + + SSS_HAVE_SCP_SCP03_SSS \ + + SSS_HAVE_SCP_SCP03_HOSTCRYPTO \ + ) > 1 ) +#error "Enable only one of 'SCP'" +#endif + + +#if ( ( 0 \ + + SSS_HAVE_SCP_NONE \ + + SSS_HAVE_SCP_SCP03_SSS \ + + SSS_HAVE_SCP_SCP03_HOSTCRYPTO \ + ) == 0 ) +#error "Enable at-least one of 'SCP'" +#endif + + + +/** FIPS : Enable or disable FIPS + * + * This selection mostly impacts tests, and generally not the actual Middleware + */ + +/** NO FIPS */ +#define SSS_HAVE_FIPS_NONE 1 + +/** SE050 IC FIPS */ +#define SSS_HAVE_FIPS_SE050 0 + +/** FIPS 140-2 */ +#define SSS_HAVE_FIPS_140_2 0 + +/** FIPS 140-3 */ +#define SSS_HAVE_FIPS_140_3 0 + +#if ( ( 0 \ + + SSS_HAVE_FIPS_NONE \ + + SSS_HAVE_FIPS_SE050 \ + + SSS_HAVE_FIPS_140_2 \ + + SSS_HAVE_FIPS_140_3 \ + ) > 1 ) +#error "Enable only one of 'FIPS'" +#endif + + +#if ( ( 0 \ + + SSS_HAVE_FIPS_NONE \ + + SSS_HAVE_FIPS_SE050 \ + + SSS_HAVE_FIPS_140_2 \ + + SSS_HAVE_FIPS_140_3 \ + ) == 0 ) +#error "Enable at-least one of 'FIPS'" +#endif + + + +/** SBL : Enable/Disable SBL Bootable support + * + * This option is to enable/disable boot from SBL by switching linker address + */ + +/** Not SBL bootable */ +#define SSS_HAVE_SBL_NONE 1 + +/** SE050 based LPC55S SBL bootable */ +#define SSS_HAVE_SBL_SBL_LPC55S 0 + +#if ( ( 0 \ + + SSS_HAVE_SBL_NONE \ + + SSS_HAVE_SBL_SBL_LPC55S \ + ) > 1 ) +#error "Enable only one of 'SBL'" +#endif + + +#if ( ( 0 \ + + SSS_HAVE_SBL_NONE \ + + SSS_HAVE_SBL_SBL_LPC55S \ + ) == 0 ) +#error "Enable at-least one of 'SBL'" +#endif + + + +/** SE05X_Auth : SE050 Authentication + * + * This settings is used by examples to connect using various options + * to authenticate with the Applet. + * The SE05X_Auth options can be changed for KSDK Demos and Examples. + * To change SE05X_Auth option follow below steps. + * Set flag ``SSS_HAVE_SCP_SCP03_SSS`` to 1 and Reset flag ``SSS_HAVE_SCP_NONE`` to 0. + * To change SE05X_Auth option other than ``None`` and ``PlatfSCP03``, + * execute se05x_Delete_and_test_provision.exe in order to provision the Authentication Key. + * To change SE05X_Auth option to ``ECKey`` or ``ECKey_PlatfSCP03``, + * Set additional flag ``SSS_HAVE_HOSTCRYPTO_ANY`` to 1. + */ + +/** Use the default session (i.e. session less) login */ +#define SSS_HAVE_SE05X_AUTH_NONE 1 + +/** Do User Authentication with UserID */ +#define SSS_HAVE_SE05X_AUTH_USERID 0 + +/** Use Platform SCP for connection to SE */ +#define SSS_HAVE_SE05X_AUTH_PLATFSCP03 0 + +/** Do User Authentication with AES Key + * Earlier this was called AppletSCP03 */ +#define SSS_HAVE_SE05X_AUTH_AESKEY 0 + +/** Do User Authentication with EC Key + * Earlier this was called FastSCP */ +#define SSS_HAVE_SE05X_AUTH_ECKEY 0 + +/** UserID and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 0 + +/** AESKey and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 0 + +/** ECKey and PlatfSCP03 */ +#define SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 0 + +#if ( ( 0 \ + + SSS_HAVE_SE05X_AUTH_NONE \ + + SSS_HAVE_SE05X_AUTH_USERID \ + + SSS_HAVE_SE05X_AUTH_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY \ + + SSS_HAVE_SE05X_AUTH_ECKEY \ + + SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 \ + ) > 1 ) +#error "Enable only one of 'SE05X_Auth'" +#endif /* if ( ( 0 + SSS_HAVE_SE05X_AUTH_NONE + SSS_HAVE_SE05X_AUTH_USERID + SSS_HAVE_SE05X_AUTH_PLATFSCP03 + SSS_HAVE_SE05X_AUTH_AESKEY + SSS_HAVE_SE05X_AUTH_ECKEY + SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 + SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 + SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 ) > 1 ) */ + + +#if ( ( 0 \ + + SSS_HAVE_SE05X_AUTH_NONE \ + + SSS_HAVE_SE05X_AUTH_USERID \ + + SSS_HAVE_SE05X_AUTH_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY \ + + SSS_HAVE_SE05X_AUTH_ECKEY \ + + SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 \ + + SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 \ + ) == 0 ) +#error "Enable at-least one of 'SE05X_Auth'" +#endif /* if ( ( 0 + SSS_HAVE_SE05X_AUTH_NONE + SSS_HAVE_SE05X_AUTH_USERID + SSS_HAVE_SE05X_AUTH_PLATFSCP03 + SSS_HAVE_SE05X_AUTH_AESKEY + SSS_HAVE_SE05X_AUTH_ECKEY + SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 + SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 + SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 ) == 0 ) */ + + + +/** A71CH_AUTH : A71CH Authentication + * + * This settings is used by SSS-API based examples to connect using either plain or authenticated to the A71CH. + */ + +/** Plain communication, not authenticated or encrypted */ +#define SSS_HAVE_A71CH_AUTH_NONE 1 + +/** SCP03 enabled */ +#define SSS_HAVE_A71CH_AUTH_SCP03 0 + +#if ( ( 0 \ + + SSS_HAVE_A71CH_AUTH_NONE \ + + SSS_HAVE_A71CH_AUTH_SCP03 \ + ) > 1 ) +#error "Enable only one of 'A71CH_AUTH'" +#endif + + +#if ( ( 0 \ + + SSS_HAVE_A71CH_AUTH_NONE \ + + SSS_HAVE_A71CH_AUTH_SCP03 \ + ) == 0 ) +#error "Enable at-least one of 'A71CH_AUTH'" +#endif + + +/* ====================================================================== * +* == Feature selection/values ========================================== * +* ====================================================================== */ + + +/** SE05X Secure Element : Symmetric AES */ +#define SSSFTR_SE05X_AES 1 + +/** SE05X Secure Element : Elliptic Curve Cryptography */ +#define SSSFTR_SE05X_ECC 1 + +/** SE05X Secure Element : RSA */ +#define SSSFTR_SE05X_RSA 1 + +/** SE05X Secure Element : KEY operations : SET Key */ +#define SSSFTR_SE05X_KEY_SET 1 + +/** SE05X Secure Element : KEY operations : GET Key */ +#define SSSFTR_SE05X_KEY_GET 1 + +/** SE05X Secure Element : Authenticate via ECKey */ +#define SSSFTR_SE05X_AuthECKey 1 + +/** SE05X Secure Element : Allow creation of user/authenticated session. + * + * If the intended deployment only uses Platform SCP + * Or it is a pure session less integration, this can + * save some code size. */ +#define SSSFTR_SE05X_AuthSession 1 + +/** SE05X Secure Element : Allow creation/deletion of Crypto Objects + * + * If disabled, new Crytpo Objects are neither created and + * old/existing Crypto Objects are not deleted. + * It is assumed that during provisioning phase, the required + * Crypto Objects are pre-created or they are never going to + * be needed. */ +#define SSSFTR_SE05X_CREATE_DELETE_CRYPTOOBJ 1 + +/** Software : Symmetric AES */ +#define SSSFTR_SW_AES 1 + +/** Software : Elliptic Curve Cryptography */ +#define SSSFTR_SW_ECC 1 + +/** Software : RSA */ +#define SSSFTR_SW_RSA 1 + +/** Software : KEY operations : SET Key */ +#define SSSFTR_SW_KEY_SET 1 + +/** Software : KEY operations : GET Key */ +#define SSSFTR_SW_KEY_GET 1 + +/** Software : Used as a test counterpart + * + * e.g. Major part of the mebdTLS SSS layer is purely used for + * testing of Secure Element implementation, and can be avoided + * fully during many production scenarios. */ +#define SSSFTR_SW_TESTCOUNTERPART 0 + +/* ====================================================================== * +* == Computed Options ================================================== * +* ====================================================================== */ + +/** Symmetric AES */ +#define SSSFTR_AES ( SSSFTR_SE05X_AES + SSSFTR_SW_AES ) +/** Elliptic Curve Cryptography */ +#define SSSFTR_ECC ( SSSFTR_SE05X_ECC + SSSFTR_SW_ECC ) +/** RSA */ +#define SSSFTR_RSA ( SSSFTR_SE05X_RSA + SSSFTR_SW_RSA ) +/** KEY operations : SET Key */ +#define SSSFTR_KEY_SET ( SSSFTR_SE05X_KEY_SET + SSSFTR_SW_KEY_SET ) +/** KEY operations : GET Key */ +#define SSSFTR_KEY_GET ( SSSFTR_SE05X_KEY_GET + SSSFTR_SW_KEY_GET ) +/** KEY operations */ +#define SSSFTR_KEY ( SSSFTR_KEY_SET + SSSFTR_KEY_GET ) +/** KEY operations */ +#define SSSFTR_SE05X_KEY ( SSSFTR_SE05X_KEY_SET + SSSFTR_SE05X_KEY_GET ) +/** KEY operations */ +#define SSSFTR_SW_KEY ( SSSFTR_SW_KEY_SET + SSSFTR_SW_KEY_GET ) + + +#define SSS_HAVE_APPLET \ + ( SSS_HAVE_APPLET_A71CH | SSS_HAVE_APPLET_A71CL | SSS_HAVE_APPLET_A71CH_SIM | SSS_HAVE_APPLET_SE05X_A | SSS_HAVE_APPLET_SE05X_B | SSS_HAVE_APPLET_SE05X_C | SSS_HAVE_APPLET_SE05X_L | SSS_HAVE_APPLET_SE051_UWB | SSS_HAVE_APPLET_AUTH | SSS_HAVE_APPLET_LOOPBACK ) + +#define SSS_HAVE_APPLET_SE05X_IOT \ + ( SSS_HAVE_APPLET_SE05X_A | SSS_HAVE_APPLET_SE05X_B | SSS_HAVE_APPLET_SE05X_C | SSS_HAVE_APPLET_SE051_UWB | SSS_HAVE_APPLET_AUTH ) + +#define SSS_HAVE_MBEDTLS_ALT \ + ( SSS_HAVE_MBEDTLS_ALT_SSS | SSS_HAVE_MBEDTLS_ALT_A71CH ) + +#define SSS_HAVE_HOSTCRYPTO_ANY \ + ( SSS_HAVE_HOSTCRYPTO_MBEDTLS | SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO | SSS_HAVE_HOSTCRYPTO_OPENSSL | SSS_HAVE_HOSTCRYPTO_USER ) + +#define SSS_HAVE_FIPS \ + ( SSS_HAVE_FIPS_SE050 | SSS_HAVE_FIPS_140_2 | SSS_HAVE_FIPS_140_3 ) + + +/* Version checks GTE - Greater Than Or Equal To */ +#if SSS_HAVE_APPLET_SE05X_IOT +#if SSS_HAVE_SE05X_VER_06_00 +#define SSS_HAVE_SE05X_VER_GTE_06_00 1 +#define SSS_HAVE_SE05X_VER_GTE_03_XX 1 +#endif /* SSS_HAVE_SE05X_VER_06_00 */ +#if SSS_HAVE_SE05X_VER_03_XX +#define SSS_HAVE_SE05X_VER_GTE_06_00 0 +#define SSS_HAVE_SE05X_VER_GTE_03_XX 1 +#endif /* SSS_HAVE_SE05X_VER_03_XX */ +#else //SSS_HAVE_APPLET_SE05X_IOT +#define SSS_HAVE_SE05X_VER_GTE_03_XX 0 +#define SSS_HAVE_SE05X_VER_GTE_06_00 0 +#endif // SSS_HAVE_APPLET_SE05X_IOT +/** Deprecated items. Used here for backwards compatibility. */ + +#define WithApplet_SE05X ( SSS_HAVE_APPLET_SE05X_IOT ) +#define WithApplet_SE050_A ( SSS_HAVE_APPLET_SE05X_A ) +#define WithApplet_SE050_B ( SSS_HAVE_APPLET_SE05X_B ) +#define WithApplet_SE050_C ( SSS_HAVE_APPLET_SE05X_C ) +#define SSS_HAVE_SE050_A ( SSS_HAVE_APPLET_SE05X_A ) +#define SSS_HAVE_SE050_B ( SSS_HAVE_APPLET_SE05X_B ) +#define SSS_HAVE_SE050_C ( SSS_HAVE_APPLET_SE05X_C ) +#define SSS_HAVE_SE05X ( SSS_HAVE_APPLET_SE05X_IOT ) +#define SSS_HAVE_SE ( SSS_HAVE_APPLET ) +#define SSS_HAVE_LOOPBACK ( SSS_HAVE_APPLET_LOOPBACK ) +#define SSS_HAVE_ALT ( SSS_HAVE_MBEDTLS_ALT ) +#define WithApplet_None ( SSS_HAVE_APPLET_NONE ) +#define SSS_HAVE_None ( SSS_HAVE_APPLET_NONE ) +#define WithApplet_A71CH ( SSS_HAVE_APPLET_A71CH ) +#define SSS_HAVE_A71CH ( SSS_HAVE_APPLET_A71CH ) +#define WithApplet_A71CL ( SSS_HAVE_APPLET_A71CL ) +#define SSS_HAVE_A71CL ( SSS_HAVE_APPLET_A71CL ) +#define WithApplet_A71CH_SIM ( SSS_HAVE_APPLET_A71CH_SIM ) +#define SSS_HAVE_A71CH_SIM ( SSS_HAVE_APPLET_A71CH_SIM ) +#define WithApplet_SE05X_A ( SSS_HAVE_APPLET_SE05X_A ) +#define SSS_HAVE_SE05X_A ( SSS_HAVE_APPLET_SE05X_A ) +#define WithApplet_SE05X_B ( SSS_HAVE_APPLET_SE05X_B ) +#define SSS_HAVE_SE05X_B ( SSS_HAVE_APPLET_SE05X_B ) +#define WithApplet_SE05X_C ( SSS_HAVE_APPLET_SE05X_C ) +#define SSS_HAVE_SE05X_C ( SSS_HAVE_APPLET_SE05X_C ) +#define WithApplet_SE05X_L ( SSS_HAVE_APPLET_SE05X_L ) +#define SSS_HAVE_SE05X_L ( SSS_HAVE_APPLET_SE05X_L ) +#define WithApplet_SE051_UWB ( SSS_HAVE_APPLET_SE051_UWB ) +#define SSS_HAVE_SE051_UWB ( SSS_HAVE_APPLET_SE051_UWB ) +#define WithApplet_AUTH ( SSS_HAVE_APPLET_AUTH ) +#define SSS_HAVE_AUTH ( SSS_HAVE_APPLET_AUTH ) +#define WithApplet_LoopBack ( SSS_HAVE_APPLET_LOOPBACK ) +#define SSS_HAVE_LoopBack ( SSS_HAVE_APPLET_LOOPBACK ) +#define SSS_HAVE_MBEDTLS ( SSS_HAVE_HOSTCRYPTO_MBEDTLS ) +#define SSS_HAVE_MBEDCRYPTO ( SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO ) +#define SSS_HAVE_OPENSSL ( SSS_HAVE_HOSTCRYPTO_OPENSSL ) +#define SSS_HAVE_USER ( SSS_HAVE_HOSTCRYPTO_USER ) +#define SSS_HAVE_NONE ( SSS_HAVE_HOSTCRYPTO_NONE ) +#define SSS_HAVE_ALT_SSS ( SSS_HAVE_MBEDTLS_ALT_SSS ) +#define SSS_HAVE_ALT_A71CH ( SSS_HAVE_MBEDTLS_ALT_A71CH ) +#define SSS_HAVE_ALT_NONE ( SSS_HAVE_MBEDTLS_ALT_NONE ) +#define SSS_HAVE_SE05X_Auth_None ( SSS_HAVE_SE05X_AUTH_NONE ) +#define SSS_HAVE_SE05X_Auth_UserID ( SSS_HAVE_SE05X_AUTH_USERID ) +#define SSS_HAVE_SE05X_Auth_PlatfSCP03 ( SSS_HAVE_SE05X_AUTH_PLATFSCP03 ) +#define SSS_HAVE_SE05X_Auth_AESKey ( SSS_HAVE_SE05X_AUTH_AESKEY ) +#define SSS_HAVE_SE05X_Auth_ECKey ( SSS_HAVE_SE05X_AUTH_ECKEY ) +#define SSS_HAVE_SE05X_Auth_UserID_PlatfSCP03 ( SSS_HAVE_SE05X_AUTH_USERID_PLATFSCP03 ) +#define SSS_HAVE_SE05X_Auth_AESKey_PlatfSCP03 ( SSS_HAVE_SE05X_AUTH_AESKEY_PLATFSCP03 ) +#define SSS_HAVE_SE05X_Auth_ECKey_PlatfSCP03 ( SSS_HAVE_SE05X_AUTH_ECKEY_PLATFSCP03 ) + +/* # CMake Features : END */ + +/* ========= Miscellaneous values : START =================== */ + +/* ECC Mode is available */ +#define SSS_HAVE_ECC 1 + +/* RSA is available */ +#define SSS_HAVE_RSA 1 + +/* TPM BARRETO_NAEHRIG Curve is enabled */ +#define SSS_HAVE_TPM_BN 1 + +/* Edwards Curve is enabled */ +#define SSS_HAVE_EC_ED 1 + +/* Montgomery Curve is enabled */ +#define SSS_HAVE_EC_MONT 1 + +/* MIFARE DESFire is enabled */ +#define SSS_HAVE_MIFARE_DESFIRE 1 + +/* PBKDF2 is enabled */ +#define SSS_HAVE_PBKDF2 1 + +/* TLS handshake support on SE is enabled */ +#define SSS_HAVE_TLS_HANDSHAKE 1 + +/* Import Export Key is enabled */ +#define SSS_HAVE_IMPORT 1 + +/* With NXP NFC Reader Library */ +#define SSS_HAVE_NXPNFCRDLIB 0 + +#define SSS_HAVE_A71XX \ + ( SSS_HAVE_APPLET_A71CH | SSS_HAVE_APPLET_A71CH_SIM ) + +#define SSS_HAVE_SSCP ( SSS_HAVE_A71XX ) + +/* For backwards compatibility */ +#define SSS_HAVE_TESTCOUNTERPART ( SSSFTR_SW_TESTCOUNTERPART ) + +/* ========= Miscellaneous values : END ===================== */ + +/* ========= Calculated values : START ====================== */ + +/* Should we expose, SSS APIs */ +#define SSS_HAVE_SSS \ + ( 0 \ + + SSS_HAVE_SSCP \ + + SSS_HAVE_APPLET_SE05X_IOT \ + + SSS_HAVE_HOSTCRYPTO_OPENSSL \ + + SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO \ + + SSS_HAVE_HOSTCRYPTO_MBEDTLS \ + + SSS_HAVE_HOSTCRYPTO_USER \ + ) + +/* MBEDCRYPTO is superset of MBEDTLS and exposing that way */ +#if SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO +#undef SSS_HAVE_MBEDTLS +#undef SSS_HAVE_HOSTCRYPTO_MBEDTLS + +#define SSS_HAVE_MBEDTLS 1 +#define SSS_HAVE_HOSTCRYPTO_MBEDTLS 1 +#endif // SSS_HAVE_HOSTCRYPTO_MBEDCRYPTO + +#if SSS_HAVE_HOSTCRYPTO_NONE +#undef SSSFTR_SE05X_AuthSession +#define SSSFTR_SE05X_AuthSession 0 +#endif + +/* Montgomery curves is not supported in SE05X_A*/ +#if SSS_HAVE_APPLET_SE05X_A +#undef SSS_HAVE_EC_MONT +#define SSS_HAVE_EC_MONT 0 +/* ED is not supported in SE050_A */ +#if SSS_HAVE_SE05X_VER_03_XX +#undef SSS_HAVE_EC_ED +#define SSS_HAVE_EC_ED 0 +#endif +#endif + +#if SSS_HAVE_RSA +#define SSS_HAVE_RSA_4K 1 +#if SSS_HAVE_APPLET_SE051_UWB +#undef SSS_HAVE_RSA_4K +#define SSS_HAVE_RSA_4K 0 +#endif +#endif + +#if SSS_HAVE_ECC +#define SSS_HAVE_EC_NIST_192 1 +#define SSS_HAVE_EC_NIST_224 1 +#define SSS_HAVE_EC_NIST_256 1 +#define SSS_HAVE_EC_NIST_384 1 +#define SSS_HAVE_EC_NIST_521 1 +#define SSS_HAVE_EC_BP 1 +#define SSS_HAVE_EC_NIST_K 1 +#define SSS_HAVE_ECDAA 1 +#define SSS_HAVE_EDDSA 1 +#if SSS_HAVE_APPLET_SE05X_A +#undef SSS_HAVE_ECDAA +#undef SSS_HAVE_EDDSA +#define SSS_HAVE_ECDAA 0 +#define SSS_HAVE_EDDSA 0 +#endif +#if SSS_HAVE_APPLET_AUTH +#undef SSS_HAVE_EC_NIST_192 +#undef SSS_HAVE_EC_NIST_224 +#undef SSS_HAVE_EC_NIST_521 +#undef SSS_HAVE_EC_BP +#undef SSS_HAVE_EC_NIST_K +#undef SSS_HAVE_ECDAA +#undef SSS_HAVE_EDDSA +#define SSS_HAVE_EC_NIST_192 0 +#define SSS_HAVE_EC_NIST_224 0 +#define SSS_HAVE_EC_NIST_521 0 +#define SSS_HAVE_EC_BP 0 +#define SSS_HAVE_EC_NIST_K 0 +#define SSS_HAVE_ECDAA 0 +#define SSS_HAVE_EDDSA 0 +#endif /* if SSS_HAVE_APPLET_AUTH */ +#endif /* if SSS_HAVE_ECC */ + +#if SSS_HAVE_APPLET +#define SSS_HAVE_HASH_1 1 +#define SSS_HAVE_HASH_224 1 +#define SSS_HAVE_HASH_512 1 +#if SSS_HAVE_APPLET_AUTH +#undef SSS_HAVE_HASH_1 +#undef SSS_HAVE_HASH_224 +#undef SSS_HAVE_HASH_512 +#define SSS_HAVE_HASH_1 0 +#define SSS_HAVE_HASH_224 0 +#define SSS_HAVE_HASH_512 0 +#endif +#endif /* if SSS_HAVE_APPLET */ + + +/* ========= Calculated values : END ======================== */ + +/* clang-format on */ + +#endif /* SSS_APIS_INC_FSL_SSS_FTR_H_ */ diff --git a/examples/evkbmimxrt1060/sesip/linkscripts/bss.ldt b/examples/evkbmimxrt1060/sesip/linkscripts/bss.ldt new file mode 100644 index 0000000..b1e41f4 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/linkscripts/bss.ldt @@ -0,0 +1,3 @@ + <#if memory.name=="SRAM_OC"> + *(.bss*) + diff --git a/examples/evkbmimxrt1060/sesip/linkscripts/data.ldt b/examples/evkbmimxrt1060/sesip/linkscripts/data.ldt new file mode 100644 index 0000000..1288826 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/linkscripts/data.ldt @@ -0,0 +1,6 @@ + <#if memory.name=="SRAM_ITC"> + *mflash_drv.o(.text .text* .rodata .rodata*) + *fsl_flexspi.o(.text .text* .rodata .rodata*) + *ota_pal.o(.text .text* .rodata .rodata*) + *flexspi_nor_flash_ops.o(.text .text* .rodata .rodata*) + diff --git a/examples/evkbmimxrt1060/sesip/linkscripts/main_text.ldt b/examples/evkbmimxrt1060/sesip/linkscripts/main_text.ldt new file mode 100644 index 0000000..b25f306 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/linkscripts/main_text.ldt @@ -0,0 +1 @@ + *(EXCLUDE_FILE(*mflash_drv.o *fsl_flexspi.o *ota_pal.o *flexspi_nor_flash_ops.o) .text*) \ No newline at end of file diff --git a/examples/evkbmimxrt1060/sesip/log.log b/examples/evkbmimxrt1060/sesip/log.log new file mode 100644 index 0000000..24a0c1c --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/log.log @@ -0,0 +1,12 @@ +12:47:53 **** Incremental Build of configuration Debug for project bootloader **** +make -r -j8 all +make[1]: Nothing to be done for 'main-build'. +Performing post-build steps +arm-none-eabi-size "bootloader.axf" ; arm-none-eabi-objcopy -v -O binary "bootloader.axf" "bootloader.bin" ; # checksum -p MIMXRT1062xxxxA -d "bootloader.bin" + text data bss dec hex filename + 54900 548 30948 86396 1517c bootloader.axf +copy from `bootloader.axf' [elf32-littlearm] to `bootloader.bin' [binary] + + +12:47:54 Build Finished. 0 errors, 0 warnings. (took 1s.8ms) + diff --git a/examples/evkbmimxrt1060/sesip/main.c b/examples/evkbmimxrt1060/sesip/main.c new file mode 100644 index 0000000..a074ff1 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/main.c @@ -0,0 +1,246 @@ +/* + * Lab-Project-coreMQTT-Agent 201215 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + */ + +/* FreeRTOS kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +/* Freescale includes. */ +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "board.h" + +#include "fsl_gpio.h" +#include "fsl_iomuxc.h" + +#include "nxLog_App.h" +#include "mflash_drv.h" + +//#include "ex_sss_boot.h" + +#include "mflash_file.h" + +#include "demo_restricted_task.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define hello_task_PRIORITY ( configMAX_PRIORITIES - 1 ) + +/******************************************************************************* + * Code + ******************************************************************************/ +void BOARD_InitModuleClock( void ) +{ + const clock_enet_pll_config_t config = { .enableClkOutput = true, .enableClkOutput25M = false, .loopDivider = 1 }; + + CLOCK_InitEnetPll( &config ); +} + +void delay( void ) +{ + volatile uint32_t i = 0; + + for( i = 0; i < 1000000; ++i ) + { + __asm( "NOP" ); /* delay */ + } +} + + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Application entry point. + */ +int main( void ) +{ + gpio_pin_config_t gpio_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode }; + + /* Init board hardware. */ + BOARD_InitBootPins(); + BOARD_InitBootClocks(); + BOARD_InitDebugConsole(); + BOARD_InitModuleClock(); + SCB_DisableDCache(); + + IOMUXC_EnableMode( IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true ); + + GPIO_PinInit( GPIO1, 9, &gpio_config ); + GPIO_PinInit( GPIO1, 10, &gpio_config ); + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput( GPIO1, 10, 1 ); + GPIO_WritePinOutput( GPIO1, 9, 0 ); + delay(); + GPIO_WritePinOutput( GPIO1, 9, 1 ); + + if( mflash_drv_init() != 0 ) + { + PRINTF( ( "\r\nFailed to initialize flash driver.\r\n" ) ); + + while( 1 ) + { + /* Empty while. */ + } + } + + vTaskStartScheduler(); + + /* Should not reach here. */ + for( ; ; ) + { + } +} + +/** + * @brief Hook which gets called on startup of the system. + * + * This function will in turn create two restricted tasks + * and print out the memory regions in the configured system. + */ +void vApplicationDaemonTaskStartupHook( void ) +{ + /* Create read-only and a read-write task. */ + xCreateRestrictedTasks( hello_task_PRIORITY ); + + /* Print the memory regions once. */ + printRegions(); +} + +/** + * @brief Loop forever if stack overflow is detected. + * + * If configCHECK_FOR_STACK_OVERFLOW is set to 1, + * this hook provides a location for applications to + * define a response to a stack overflow. + * + * Use this hook to help identify that a stack overflow + * has occurred. + * + */ +void vApplicationStackOverflowHook( TaskHandle_t xTask, + char * pcTaskName ) +{ + PRINTF( "ERROR: stack overflow on task %s.\r\n", pcTaskName ); + + portDISABLE_INTERRUPTS(); + + /* Unused Parameters */ + ( void ) xTask; + ( void ) pcTaskName; + + /* Loop forever */ + for( ; ; ) + { + __asm( "NOP" ); + } +} + +/** + * @brief Warn user if pvPortMalloc fails. + * + * Called if a call to pvPortMalloc() fails because there is insufficient + * free memory available in the FreeRTOS heap. pvPortMalloc() is called + * internally by FreeRTOS API functions that create tasks, queues, software + * timers, and semaphores. The size of the FreeRTOS heap is set by the + * configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. + * + */ +void vApplicationMallocFailedHook() +{ + PRINTF( "ERROR: Malloc failed to allocate memory\r\n" ); + taskDISABLE_INTERRUPTS(); + + /* Loop forever */ + for( ; ; ) + { + } +} + +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) +{ + /* If the buffers to be provided to the Idle task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle + * task's state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/** + * @brief This is to provide the memory that is used by the RTOS daemon/time task. + * + * If configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetTimerTaskMemory() to provide the memory that is + * used by the RTOS daemon/time task. + */ +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ + /* If the buffers to be provided to the Timer task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( configTIMER_TASK_STACK_DEPTH * sizeof( StackType_t ) ) ) ); + + /* Pass out a pointer to the StaticTask_t structure in which the Idle + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} +/*-----------------------------------------------------------*/ diff --git a/examples/evkbmimxrt1060/sesip/memfault_handler.c b/examples/evkbmimxrt1060/sesip/memfault_handler.c new file mode 100644 index 0000000..f38e039 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/memfault_handler.c @@ -0,0 +1,62 @@ +/* + * FreeRTOS version 202012.00-LTS + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + /** + * @brief File shows a sample implementation of memory fault handler. + */ + + /** + * @brief Memory fault handler invoked by the MPU unit for illegal access to a previleged memory. + * This overrides the default platform MemManage_Handler and calls the demo defined hard fault + * handler in user/demo_restrictions.c file. + */ +void MemManage_Handler(void) __attribute__((naked)); +/*-----------------------------------------------------------*/ +#include "FreeRTOS.h" +extern void vHandleMemoryFault( uint32_t * pulFaultStackAddress ); + +/** + * @brief Handler for memory faults. + * The handler jumps to vHandleMemoryFault function to actually + * handle the fault. + */ +void MemManage_Handler(void) +{ + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, .handler_address_const \n" + " bx r1 \n" + " \n" + " .ALIGN 4 \n" + " .handler_address_const: .word vHandleMemoryFault \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/examples/evkbmimxrt1060/sesip/semihost_hardfault.c b/examples/evkbmimxrt1060/sesip/semihost_hardfault.c new file mode 100644 index 0000000..7f87426 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/semihost_hardfault.c @@ -0,0 +1,98 @@ +/* **************************************************************************** */ +/* semihost_hardfault.c */ +/* - Provides hard fault handler to allow semihosting code not */ +/* to hang application when debugger not connected. */ +/* */ +/* **************************************************************************** */ +/* Copyright 2017-2021 NXP */ +/* All rights reserved. */ +/* */ +/* NXP Confidential. This software is owned or controlled by NXP and may only be */ +/* used strictly in accordance with the applicable license terms. */ +/* */ +/* By expressly accepting such terms or by downloading, installing, activating */ +/* and/or otherwise using the software, you are agreeing that you have read, and */ +/* that you agree to comply with and are bound by, such license terms. */ +/* */ +/* If you do not agree to be bound by the applicable license terms, then you may not */ +/* retain, install, activate or otherwise use the software. */ +/* **************************************************************************** */ +/* */ +/* ===== DESCRIPTION ===== */ +/* */ +/* One of the issues with applications that make use of semihosting operations */ +/* (such as printf calls) is that the code will not execute correctly when the */ +/* debugger is not connected. Generally this will show up with the application */ +/* appearing to just hang. This may include the application running from reset */ +/* or powering up the board (with the application already in FLASH), and also */ +/* as the application failing to continue to execute after a debug session is */ +/* terminated. */ +/* */ +/* The problem here is that the "bottom layer" of the semihosted variants of */ +/* the C library, semihosting is implemented by a "BKPT 0xAB" instruction. */ +/* When the debug tools are not connected, this instruction triggers a hard */ +/* fault - and the default hard fault handler within an application will */ +/* typically just contains an infinite loop - causing the application to */ +/* appear to have hang when no debugger is connected. */ +/* */ +/* The below code provides an example hard fault handler which instead looks */ +/* to see what the instruction that caused the hard fault was - and if it */ +/* was a "BKPT 0xAB", then it instead returns back to the user application. */ +/* */ +/* In most cases this will allow applications containing semihosting */ +/* operations to execute (to some degree) when the debugger is not connected. */ +/* */ +/* == NOTE == */ +/* */ +/* Correct execution of the application containing semihosted operations */ +/* which are vectored onto this hard fault handler cannot be guaranteed. This */ +/* is because the handler may not return data or return codes that the higher */ +/* level C library code or application code expects. This hard fault handler */ +/* is meant as a development aid, and it is not recommended to leave */ +/* semihosted code in a production build of your application! */ +/* */ +/* **************************************************************************** */ + +/* Allow handler to be removed by setting a define (via command line) */ +#if !defined( __SEMIHOST_HARDFAULT_DISABLE ) + +__attribute__( ( naked ) ) +void HardFault_Handler( void ) +{ + __asm( ".syntax unified\n" + /* Check which stack is in use */ + "MOVS R0, #4 \n" + "MOV R1, LR \n" + "TST R0, R1 \n" + "BEQ _MSP \n" + "MRS R0, PSP \n" + "B _process \n" + "_MSP: \n" + "MRS R0, MSP \n" + /* Load the instruction that triggered hard fault */ + "_process: \n" + "LDR R1,[R0,#24] \n" + "LDRH R2,[r1] \n" + /* Semihosting instruction is "BKPT 0xAB" (0xBEAB) */ + "LDR R3,=0xBEAB \n" + "CMP R2,R3 \n" + "BEQ _semihost_return \n" + /* Wasn't semihosting instruction so enter infinite loop */ + "B . \n" + /* Was semihosting instruction, so adjust location to */ + /* return to by 1 instruction (2 bytes), then exit function */ + "_semihost_return: \n" + "ADDS R1,#2 \n" + "STR R1,[R0,#24] \n" + /* Set a return value from semihosting operation. */ + /* 32 is slightly arbitrary, but appears to allow most */ + /* C Library IO functions sitting on top of semihosting to */ + /* continue to operate to some degree */ + "MOVS R1,#32 \n" + "STR R1,[ R0,#0 ] \n" /* R0 is at location 0 on stack */ + /* Return from hard fault handler to application */ + "BX LR \n" + ".syntax divided\n" ); +} + +#endif /* if !defined( __SEMIHOST_HARDFAULT_DISABLE ) */ diff --git a/examples/evkbmimxrt1060/sesip/simple_pub_sub_task.c b/examples/evkbmimxrt1060/sesip/simple_pub_sub_task.c new file mode 100644 index 0000000..ec54397 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/simple_pub_sub_task.c @@ -0,0 +1,680 @@ +/* + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + */ + +/* + * This file demonstrates task which use the MQTT agent API + * to send unique MQTT payloads to unique topics over the same MQTT connection + * to the same MQTT agent. Some tasks use QoS0 and others QoS1. + * + * vSimpleSubscribePublishTask() subscribes to a topic then periodically publishes a message to the same + * topic to which it has subscribed. The command context sent to + * MQTTAgent_Publish() contains a unique number that is sent back to the task + * as a task notification from the callback function that executes when the + * PUBLISH operation is acknowledged (or just sent in the case of QoS 0). The + * task checks the number it receives from the callback equals the number it + * previously set in the command context before printing out either a success + * or failure message. + */ + + +/* Standard includes. */ +#include +#include +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Demo Specific configs. */ +#include "demo_config.h" + +/* MQTT library includes. */ +#include "core_mqtt.h" + +/* MQTT agent include. */ +#include "core_mqtt_agent.h" + +/* MQTT agent task API. */ +#include "mqtt_agent_task.h" + +/* Fetches thing name from the key store */ +#include "kvstore.h" + +/** + * @brief Delay for the synchronous publisher task between publishes. + */ +#define mqttexampleDELAY_BETWEEN_PUBLISH_OPERATIONS_MS ( 2000U ) + +/** + * @brief Number of publishes done by each task in this demo. + */ +#define mqttexamplePUBLISH_COUNT UINT32_MAX + +/** + * @brief Number of times a publish has to be retried if agent cannot send a QoS0 packet + * or an ACK is not received for a QoS1 packet. + */ +#define mqttexampleNUM_PUBLISH_RETRIES ( 3 ) + +/** + * @brief The maximum amount of time in milliseconds to wait for the commands + * to be posted to the MQTT agent should the MQTT agent's command queue be full. + * Tasks wait in the Blocked state, so don't use any CPU time. + */ +#define mqttexampleMAX_COMMAND_SEND_BLOCK_TIME_MS ( 1000 ) + +/** + * @brief Maximum length of the thing name as set by AWS IoT. + * This is used to set the maximum size of topic buffer that needs to be allocated. + */ +#define mqttexampleTHING_NAME_MAX_LENGTH ( 128 ) + +/** + * @brief Size of statically allocated buffers for holding payloads. + */ +#define mqttexampleSTRING_BUFFER_LENGTH ( 100 ) + +/** + * @brief Format of the loop-back topic. + * Demo task subscribes to the loop-back topic and then publishes to the same topic so as to echo back + * the message published onto the serial console. This tests the full publish-subscribe path of the message + * without an external application sending messages to the device. + * + * Topic format follows a hierarchy as follows: domain_name/device_identifier/publisher_identifier. + * domain_name refers to domain under which all devices publishes and subscribes message with the MQTT broker. + * device_identifier is a unique identifier for a device sending message within the domain. The domain name and + * device_identifier together can be used a topic filter to subscribe to all messages from device. + * publisher_identifier is a unique identifier for an entity within a device which is publishing the message. In + * this demo this can be a task number, when more than one tasks are publishing within a device. + * + */ +#define mqttexampleLOOPBACK_TOPIC_FORMAT "pubsub_demo/%s/task_%lu" + +/** + * @brief Format for the topic to which demo task sends PUBLISH messages to broker. + * The topic is set by default as the loopback topic, so that device will receive the same message which is sent to the + * broker. + */ +#define mqttexampleOUTPUT_TOPIC_FORMAT mqttexampleLOOPBACK_TOPIC_FORMAT + +/** + * @brief Size of the static buffer to hold the output topic name. + * The buffer should accommodate the topic format string, thing name and the task number which is a 32bit integer. + */ +#define mqttexampleOUTPUT_TOPIC_BUFFER_LENGTH ( sizeof( mqttexampleOUTPUT_TOPIC_FORMAT ) + mqttexampleTHING_NAME_MAX_LENGTH + 10U ) + +/** + * @brief Format for the topic to receive incoming messages from the MQTT broker. + * Topic is set by default as the loopback topic so that the device will receive the same message which is published to the + * broker. + */ +#define mqttexampleINPUT_TOPIC_FORMAT mqttexampleLOOPBACK_TOPIC_FORMAT + +/** + * @brief Size of the static buffer to hold the topic name. + * The buffer should accommodate the topic format string, thing name and the task number which is a 32bit integer. + */ +#define mqttexampleINPUT_TOPIC_BUFFER_LENGTH ( sizeof( mqttexampleINPUT_TOPIC_FORMAT ) + mqttexampleTHING_NAME_MAX_LENGTH + 10U ) + +/*-----------------------------------------------------------*/ + +/** + * @brief Defines the structure to use as the command callback context in this + * demo. + */ +struct MQTTAgentCommandContext +{ + TaskHandle_t xTaskToNotify; + void * pArgs; +}; + +/*-----------------------------------------------------------*/ + +/** + * @brief Passed into MQTTAgent_Subscribe() as the callback to execute when the + * broker ACKs the SUBSCRIBE message. Its implementation sends a notification + * to the task that called MQTTAgent_Subscribe() to let the task know the + * SUBSCRIBE operation completed. It also sets the xReturnStatus of the + * structure passed in as the command's context to the value of the + * xReturnStatus parameter - which enables the task to check the status of the + * operation. + * + * See https://freertos.org/mqtt/mqtt-agent-demo.html#example_mqtt_api_call + * + * @param[in] pxCommandContext Context of the initial command. + * @param[in].xReturnStatus The result of the command. + */ +static void prvSubscribeCommandCallback( MQTTAgentCommandContext_t * pxCommandContext, + MQTTAgentReturnInfo_t * pxReturnInfo ); + +/** + * @brief Passed into MQTTAgent_Publish() as the callback to execute when the + * broker ACKs the PUBLISH message. Its implementation sends a notification + * to the task that called MQTTAgent_Publish() to let the task know the + * PUBLISH operation completed. It also sets the xReturnStatus of the + * structure passed in as the command's context to the value of the + * xReturnStatus parameter - which enables the task to check the status of the + * operation. + * + * See https://freertos.org/mqtt/mqtt-agent-demo.html#example_mqtt_api_call + * + * @param[in] pxCommandContext Context of the initial command. + * @param[in].xReturnStatus The result of the command. + */ +static void prvPublishCommandCallback( MQTTAgentCommandContext_t * pxCommandContext, + MQTTAgentReturnInfo_t * pxReturnInfo ); + +/** + * @brief Passed into MQTTAgent_Subscribe() as the callback to execute when + * there is an incoming publish on the topic being subscribed to. Its + * implementation just logs information about the incoming publish including + * the publish messages source topic and payload. + * + * See https://freertos.org/mqtt/mqtt-agent-demo.html#example_mqtt_api_call + * + * @param[in] pvIncomingPublishCallbackContext Context of the initial command. + * @param[in] pxPublishInfo Deserialized publish. + */ +static void prvIncomingPublishCallback( void * pvIncomingPublishCallbackContext, + MQTTPublishInfo_t * pxPublishInfo ); + +/** + * @brief Subscribe to the topic the demo task will also publish to - that + * results in all outgoing publishes being published back to the task + * (effectively echoed back). + * + * @param[in] xQoS The quality of service (QoS) to use. Can be zero or one + * for all MQTT brokers. Can also be QoS2 if supported by the broker. AWS IoT + * does not support QoS2. + * @param[in] pcTopicFilter Pointer to the topic filter string to subscribe for. + * @param[in] xTopicFilterLength Length of the topic filter string. + */ +static MQTTStatus_t prvSubscribeToTopic( MQTTQoS_t xQoS, + char * pcTopicFilter, + size_t xTopicFilterLength ); + + +/** + * @brief Publishes the given payload using the given qos to the topic provided. + * + * Function queues a publish command with the MQTT agent and waits for response. For + * Qos0 publishes command is successful when the message is sent out of network. For Qos1 + * publishes, the command succeeds once a puback is received. If publish is unsuccessful, the function + * retries the publish for a configure number of tries. + * + * @param[in] xQoS The quality of service (QoS) to use. Can be zero or one + * for all MQTT brokers. Can also be QoS2 if supported by the broker. AWS IoT + * does not support QoS2. + * @param[in] pcTopic NULL terminated topic string to which message is published. + * @param[in] xTopicLength Length of the topic string. + * @param[in] pucPayload The payload blob to be published. + * @param[in] xPayloadLength Length of the payload blob to be published. + * @param[in] lNumTries Number of retries if the QoS1 publish is not acknowledged. + */ +static MQTTStatus_t prvPublishToTopic( MQTTQoS_t xQoS, + char * pcTopic, + size_t xTopicLength, + uint8_t * pucPayload, + size_t xPayloadLength, + int32_t lNumTries ); + +/** + * @brief Retrieves the thing name from key store to use in demo. + * + * @return Pointer to null terminated string containing the thing name. + * NULL if thing name not found. + */ +static char * prvGetThingNameFromKeyStore( void ); + +/** + * @brief The function that implements the task demonstrated by this file. + * + * @param pvParameters The parameters to the task. + */ +void vSimpleSubscribePublishTask( void * pvParameters ); + + +/** + * @brief Starts a group of publish subscribe tasks as requested by the user. + * All tasks share the same code, task stack size and task priority, but publishes + * messages to different topics. + * + * @param ulNumPubsubTasks Number of publish subscribe tasks to start. + * @param uxStackSize Stack size for each publish subscribe task. + * @param uxPriority Priority for each publish subscribe task. + */ +BaseType_t xStartSimplePubSubTasks( uint32_t ulNumPubsubTasks, + configSTACK_DEPTH_TYPE uxStackSize, + UBaseType_t uxPriority ); + +/*-----------------------------------------------------------*/ + +/** + * @brief The MQTT agent manages the MQTT contexts. This set the handle to the + * context used by this demo. + */ +extern MQTTAgentContext_t xGlobalMqttAgentContext; + +/*-----------------------------------------------------------*/ + +static void prvPublishCommandCallback( MQTTAgentCommandContext_t * pxCommandContext, + MQTTAgentReturnInfo_t * pxReturnInfo ) +{ + if( pxCommandContext->xTaskToNotify != NULL ) + { + ( void ) xTaskNotify( pxCommandContext->xTaskToNotify, + pxReturnInfo->returnCode, + eSetValueWithOverwrite ); + } +} + +/*-----------------------------------------------------------*/ + +static void prvSubscribeCommandCallback( MQTTAgentCommandContext_t * pxCommandContext, + MQTTAgentReturnInfo_t * pxReturnInfo ) +{ + BaseType_t xSubscriptionAdded = pdFALSE; + MQTTAgentSubscribeArgs_t * pxSubscribeArgs = ( MQTTAgentSubscribeArgs_t * ) pxCommandContext->pArgs; + + /* Check if the subscribe operation is a success. Only one topic is + * subscribed by this demo. */ + if( pxReturnInfo->returnCode == MQTTSuccess ) + { + /* Add subscription so that incoming publishes are routed to the application + * callback. */ + xSubscriptionAdded = xAddMQTTTopicFilterCallback( pxSubscribeArgs->pSubscribeInfo->pTopicFilter, + pxSubscribeArgs->pSubscribeInfo->topicFilterLength, + prvIncomingPublishCallback, + NULL, + pdTRUE ); + configASSERT( xSubscriptionAdded == pdTRUE ); + } + + xTaskNotify( pxCommandContext->xTaskToNotify, + ( uint32_t ) ( pxReturnInfo->returnCode ), + eSetValueWithOverwrite ); +} + +/*-----------------------------------------------------------*/ + +static void prvIncomingPublishCallback( void * pvIncomingPublishCallbackContext, + MQTTPublishInfo_t * pxPublishInfo ) +{ + static char cTerminatedString[ mqttexampleSTRING_BUFFER_LENGTH ]; + + ( void ) pvIncomingPublishCallbackContext; + + /* Create a message that contains the incoming MQTT payload to the logger, + * terminating the string first. */ + if( pxPublishInfo->payloadLength < mqttexampleSTRING_BUFFER_LENGTH ) + { + memcpy( ( void * ) cTerminatedString, pxPublishInfo->pPayload, pxPublishInfo->payloadLength ); + cTerminatedString[ pxPublishInfo->payloadLength ] = 0x00; + } + else + { + memcpy( ( void * ) cTerminatedString, pxPublishInfo->pPayload, mqttexampleSTRING_BUFFER_LENGTH ); + cTerminatedString[ mqttexampleSTRING_BUFFER_LENGTH - 1 ] = 0x00; + } + + LogInfo( ( "Received incoming publish message %s", cTerminatedString ) ); +} + +/*-----------------------------------------------------------*/ + +static MQTTStatus_t prvSubscribeToTopic( MQTTQoS_t xQoS, + char * pcTopicFilter, + size_t xTopicFilterLength ) +{ + MQTTStatus_t xCommandStatus; + MQTTAgentSubscribeArgs_t xSubscribeArgs = { 0 }; + MQTTSubscribeInfo_t xSubscribeInfo = { 0 }; + MQTTAgentCommandContext_t xCommandContext = { 0UL }; + MQTTAgentCommandInfo_t xCommandParams = { 0UL }; + uint32_t ulNotifiedValue = 0U; + + /* Complete the subscribe information. The topic string must persist for + * duration of subscription! */ + xSubscribeInfo.pTopicFilter = pcTopicFilter; + xSubscribeInfo.topicFilterLength = ( uint16_t ) xTopicFilterLength; + xSubscribeInfo.qos = xQoS; + xSubscribeArgs.pSubscribeInfo = &xSubscribeInfo; + xSubscribeArgs.numSubscriptions = 1; + + /* Complete an application defined context associated with this subscribe message. + * This gets updated in the callback function so the variable must persist until + * the callback executes. */ + xCommandContext.xTaskToNotify = xTaskGetCurrentTaskHandle(); + xCommandContext.pArgs = ( void * ) &xSubscribeArgs; + + xCommandParams.blockTimeMs = mqttexampleMAX_COMMAND_SEND_BLOCK_TIME_MS; + xCommandParams.cmdCompleteCallback = prvSubscribeCommandCallback; + xCommandParams.pCmdCompleteCallbackContext = ( void * ) &xCommandContext; + + xTaskNotifyStateClear( NULL ); + + /* Loop in case the queue used to communicate with the MQTT agent is full and + * attempts to post to it time out. The queue will not become full if the + * priority of the MQTT agent task is higher than the priority of the task + * calling this function. */ + do + { + xCommandStatus = MQTTAgent_Subscribe( &xGlobalMqttAgentContext, + &xSubscribeArgs, + &xCommandParams ); + + if( xCommandStatus == MQTTSuccess ) + { + /* + * If command was enqueued successfully, then agent will either process the packet successfully, or if + * there is a disconnect, then it either retries the subscribe message while reconnecting and resuming + * persistent sessions or cancel the operation and invokes the callback for failed response. + * Hence the caller task wait indefinitely for a success or failure response from agent. + */ + ( void ) xTaskNotifyWait( 0UL, + UINT32_MAX, + &ulNotifiedValue, + portMAX_DELAY ); + xCommandStatus = ( MQTTStatus_t ) ( ulNotifiedValue ); + } + + if( xCommandStatus != MQTTSuccess ) + { + if( xGetMQTTAgentState() == MQTT_AGENT_STATE_DISCONNECTED ) + { + ( void ) xWaitForMQTTAgentState( MQTT_AGENT_STATE_CONNECTED, portMAX_DELAY ); + } + } + } while( xCommandStatus != MQTTSuccess ); + + return xCommandStatus; +} +/*-----------------------------------------------------------*/ + +static MQTTStatus_t prvPublishToTopic( MQTTQoS_t xQoS, + char * pcTopic, + size_t xTopicLength, + uint8_t * pucPayload, + size_t xPayloadLength, + int32_t lNumRetries ) +{ + MQTTPublishInfo_t xPublishInfo = { 0UL }; + MQTTAgentCommandContext_t xCommandContext = { 0 }; + MQTTStatus_t xCommandStatus; + MQTTAgentCommandInfo_t xCommandParams = { 0UL }; + uint32_t ulNotifiedValue = 0U; + + xTaskNotifyStateClear( NULL ); + + /* Configure the publish operation. */ + xPublishInfo.qos = xQoS; + xPublishInfo.pTopicName = pcTopic; + xPublishInfo.topicNameLength = ( uint16_t ) xTopicLength; + xPublishInfo.pPayload = pucPayload; + xPublishInfo.payloadLength = xPayloadLength; + + xCommandContext.xTaskToNotify = xTaskGetCurrentTaskHandle(); + + xCommandParams.blockTimeMs = mqttexampleMAX_COMMAND_SEND_BLOCK_TIME_MS; + xCommandParams.cmdCompleteCallback = prvPublishCommandCallback; + xCommandParams.pCmdCompleteCallbackContext = &xCommandContext; + + do + { + xCommandStatus = MQTTAgent_Publish( &xGlobalMqttAgentContext, + &xPublishInfo, + &xCommandParams ); + + if( xCommandStatus == MQTTSuccess ) + { + /* + * If command was enqueued successfully, then agent will either process the packet successfully, or if + * there is a disconnect, then it either retries the publish after reconnecting and resuming session + * (only for persistent sessions) or cancel the operation and invokes the callback for failed response. + * Hence the caller task wait indefinitely for a success or failure response from agent. + */ + ( void ) xTaskNotifyWait( 0UL, + UINT32_MAX, + &ulNotifiedValue, + portMAX_DELAY ); + xCommandStatus = ( MQTTStatus_t ) ( ulNotifiedValue ); + } + + if( ( xCommandStatus != MQTTSuccess ) && ( lNumRetries > 0 ) ) + { + if( xGetMQTTAgentState() == MQTT_AGENT_STATE_DISCONNECTED ) + { + ( void ) xWaitForMQTTAgentState( MQTT_AGENT_STATE_CONNECTED, portMAX_DELAY ); + } + + if( xQoS == MQTTQoS1 ) + { + xPublishInfo.dup = true; + } + } + } while( ( xCommandStatus != MQTTSuccess ) && ( lNumRetries-- > 0 ) ); + + return xCommandStatus; +} +/*-----------------------------------------------------------*/ + +static char * prvGetThingNameFromKeyStore( void ) +{ + size_t xValueLength = 0U; + char * pcValue = NULL; + + /* Load broker endpoint and thing name for client connection, from the key store. */ + xValueLength = KVStore_getValueLength( KVS_CORE_THING_NAME ); + + if( xValueLength > 0 ) + { + pcValue = pvPortMalloc( xValueLength + 1 ); + + if( pcValue != NULL ) + { + ( void ) KVStore_getString( KVS_CORE_THING_NAME, pcValue, ( xValueLength + 1 ) ); + } + } + + return pcValue; +} + +/*-----------------------------------------------------------*/ + + +void vSimpleSubscribePublishTask( void * pvParameters ) +{ + uint32_t ulTaskNumber = ( uint32_t ) pvParameters; + MQTTQoS_t xQoS; + TickType_t xTicksToDelay; + char cPayloadBuf[ mqttexampleSTRING_BUFFER_LENGTH ]; + char cInTopicBuf[ mqttexampleINPUT_TOPIC_BUFFER_LENGTH ]; + char cOutTopicBuf[ mqttexampleOUTPUT_TOPIC_BUFFER_LENGTH ]; + size_t xInTopicLength = 0UL, xOutTopicLength = 0UL, xPayloadLength = 0UL; + char * pcThingName = NULL; + uint32_t ulPublishCount = 0U, ulSuccessCount = 0U, ulFailCount = 0U; + BaseType_t xStatus = pdPASS; + MQTTStatus_t xMQTTStatus; + + /* Have different tasks use different QoS. 0 and 1. 2 can also be used + * if supported by the broker. */ + xQoS = ( MQTTQoS_t ) ( ulTaskNumber % 2UL ); + + /* + * Get the thing name to be used in topic filter. + */ + pcThingName = prvGetThingNameFromKeyStore(); + + if( pcThingName == NULL ) + { + xStatus = pdFAIL; + } + + if( xStatus == pdPASS ) + { + if( xGetMQTTAgentState() != MQTT_AGENT_STATE_CONNECTED ) + { + ( void ) xWaitForMQTTAgentState( MQTT_AGENT_STATE_CONNECTED, portMAX_DELAY ); + } + } + + if( xStatus == pdPASS ) + { + /* Create a topic name for this task to publish to. */ + xInTopicLength = snprintf( cInTopicBuf, + mqttexampleINPUT_TOPIC_BUFFER_LENGTH, + mqttexampleINPUT_TOPIC_FORMAT, + pcThingName, + ulTaskNumber ); + + /* Assert if the topic buffer is enough to hold the required topic. */ + configASSERT( xInTopicLength <= mqttexampleINPUT_TOPIC_BUFFER_LENGTH ); + + /* Subscribe to the same topic to which this task will publish. That will + * result in each published message being published from the server back to + * the target. */ + + LogInfo( ( "Sending subscribe request to agent for topic filter: %.*s", xInTopicLength, cInTopicBuf ) ); + + xMQTTStatus = prvSubscribeToTopic( xQoS, cInTopicBuf, xInTopicLength ); + + if( xMQTTStatus != MQTTSuccess ) + { + LogError( ( "Failed to subscribe to topic: %.*s", + xInTopicLength, + cInTopicBuf ) ); + xStatus = pdFALSE; + } + else + { + LogError( ( "Successfully subscribed to topic: %.*s", + xInTopicLength, + cInTopicBuf ) ); + } + } + + if( xStatus == pdTRUE ) + { + /* Create a topic name for this task to publish to. */ + xOutTopicLength = snprintf( cOutTopicBuf, + mqttexampleOUTPUT_TOPIC_BUFFER_LENGTH, + mqttexampleOUTPUT_TOPIC_FORMAT, + pcThingName, + ulTaskNumber ); + + /* Assert if the topic buffer is enough to hold the required topic. */ + configASSERT( xOutTopicLength <= mqttexampleOUTPUT_TOPIC_BUFFER_LENGTH ); + + /* For a finite number of publishes... */ + for( ulPublishCount = 0UL; ulPublishCount < mqttexamplePUBLISH_COUNT; ulPublishCount++ ) + { + /* Create a payload to send with the publish message. This contains + * the task name and an incrementing number. */ + xPayloadLength = snprintf( cPayloadBuf, + mqttexampleSTRING_BUFFER_LENGTH, + "Task %lu publishing message %d", + ulTaskNumber, + ( int ) ulPublishCount ); + + /* Assert if the buffer length is not enough to hold the message.*/ + configASSERT( xPayloadLength <= mqttexampleSTRING_BUFFER_LENGTH ); + + LogInfo( ( "Sending publish request on topic \"%.*s\"", xOutTopicLength, cOutTopicBuf ) ); + + xMQTTStatus = prvPublishToTopic( xQoS, + cOutTopicBuf, + xOutTopicLength, + ( uint8_t * ) cPayloadBuf, + xPayloadLength, + mqttexampleNUM_PUBLISH_RETRIES ); + + if( xMQTTStatus == MQTTSuccess ) + { + ulSuccessCount++; + LogInfo( ( "Successfully sent QoS %u publish to topic: %s (PassCount:%d, FailCount:%d).", + xQoS, + cOutTopicBuf, + ulSuccessCount, + ulFailCount ) ); + } + else + { + ulFailCount++; + LogError( ( "Timed out while sending QoS %u publish to topic: %s (PassCount:%d, FailCount: %d)", + xQoS, + cOutTopicBuf, + ulSuccessCount, + ulFailCount ) ); + } + + /* Add a little randomness into the delay so the tasks don't remain + * in lockstep. */ + xTicksToDelay = pdMS_TO_TICKS( mqttexampleDELAY_BETWEEN_PUBLISH_OPERATIONS_MS ) + + ( xTaskGetTickCount() % 0xff ); + + if( xWaitForMQTTAgentState( MQTT_AGENT_STATE_DISCONNECTED, xTicksToDelay ) == pdTRUE ) + { + ( void ) xWaitForMQTTAgentState( MQTT_AGENT_STATE_CONNECTED, portMAX_DELAY ); + } + } + + /* Delete the task if it is complete. */ + LogInfo( ( "Task %u completed.", ulTaskNumber ) ); + } + + if( pcThingName != NULL ) + { + vPortFree( pcThingName ); + pcThingName = NULL; + } + + vTaskDelete( NULL ); +} + +BaseType_t xStartSimplePubSubTasks( uint32_t ulNumPubsubTasks, + configSTACK_DEPTH_TYPE uxStackSize, + UBaseType_t uxPriority ) +{ + BaseType_t xResult = pdFAIL; + uint32_t ulTaskNum; + + for( ulTaskNum = 0; ulTaskNum < ulNumPubsubTasks; ulTaskNum++ ) + { + xResult = xTaskCreate( vSimpleSubscribePublishTask, + "PUBSUB", + uxStackSize, + ( void * ) ulTaskNum, + uxPriority, + NULL ); + + if( xResult == pdFAIL ) + { + break; + } + } + + return xResult; +} diff --git a/examples/evkbmimxrt1060/sesip/task/demo_restricted_task.c b/examples/evkbmimxrt1060/sesip/task/demo_restricted_task.c new file mode 100644 index 0000000..5824ea3 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/task/demo_restricted_task.c @@ -0,0 +1,389 @@ +/* + * FreeRTOS version 202012.00-LTS + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @brief Demonstration of Memory Protection Unit functionalities. + * Demo creates two restricted tasks read-only task and and a read write task. + * To find more about create restricted task API, see: https://www.freertos.org/xTaskCreateRestricted.html. + * Read-only task has read only access to a shared memory region, while Read-Write task has both read and write + * access to it. Read-only task sets a global flag to one and then try to write to the shared memory region, which generates + * hard fault by MPU. The hard fault handler implemented in this demo handles the exception gracefully by setting the global + * flag back to zero and skipping to the next instruction in the task. The read only task verifies that flag is reset to zero to confirm + * that the memory fault was raised and handled gracefully. + */ + +/* FreeRTOS include. */ +#include "FreeRTOS.h" + +/* Task API include. */ +#include "task.h" + +/* Contains PRINTF APIs. */ +#include "fsl_debug_console.h" + +/** + * @brief Flag to enable or disable memory fault injection. + * To enable, set the flag to 1. Enabling this will cause the read-only task to write to a shared memory region + * thereby causing a hard fault. + */ +#define INJECT_TEST_MEMORY_FAULT ( 1 ) + +/** + * @brief Size of the shared memory between the restricted tasks. + */ +#define SHARED_MEMORY_SIZE 32 + +/** + * @brief Size of the memory region used by the Read only task and hard fault handler. + */ +#define MIN_REGION_SIZE 32 + +/** + * @brief Stack size of the restricted tasks. + */ +#define RESTRICTED_TASK_STACK_SIZE 128 + +/* + * @brief Macro to override printf funtion to run it in privileged mode. + * NXP PRINTF code resides somewhere in RAM that could be provided as accessible region, but it's simpler to + * just run it as privileged */ +#define MPU_PRINTF( ... ) \ + { \ + portRAISE_PRIVILEGE(); \ + PRINTF( __VA_ARGS__ ); \ + portRESET_PRIVILEGE(); \ + } + +/* For readability. Read about Hardfault Entry in ARMv7 docs for more details */ +typedef struct +{ + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr; + uint32_t return_address; + uint32_t xPSR; +} HardFaultStack_t; + + +/** + * @brief Calls the port specific code to raise the privilege. + * + * @return pdFALSE if privilege was raised, pdTRUE otherwise. + */ +extern BaseType_t xPortRaisePrivilege( void ); + +/** + * @brief Calls the port specific code to reset the privilege. + * If xRunningPrivileged is pdFALSE, calls the port specific + * code to reset the privilege, otherwise does nothing. + * + * @param[in] xRunningPrivileged Whether running in privelged mode or not. + */ +extern void vPortResetPrivilege( BaseType_t xRunningPrivileged ); + +/** + * @brief Function used to dump the MPU memory regions allocated by linker script. + */ +void printRegions( void ); + +/** + * @brief The Read write restricted task. + * Task loops and keeps writing to the shared memory region. Since task has both read and write access it should + * not cause a memory fault. + * + * @param[in] pvParameters Parameters to the task. + */ +static void prvRWAccessTask( void * pvParameters ); + +/** + * @brief The read only task + * Task loops and reads from the shared memory region. If INJECT_TEST_MEMORY_FAULT is set to 1, task also writes to + * shared memory region. Using hard fault handler it recovers from the hard fault and prints the memory access violation + * to the console. + * + * @param[in] pvParameters Parameters to the task. + */ +static void prvROAccessTask( void * pvParameters ); + +/** + * @brief Memory regions used by the linker script. + */ +extern uint32_t __privileged_functions_start__[]; +extern uint32_t __privileged_functions_end__[]; +extern uint32_t __FLASH_segment_start__[]; +extern uint32_t __FLASH_segment_end__[]; +extern uint32_t __privileged_data_start__[]; +extern uint32_t __privileged_data_end__[]; +extern uint32_t __syscalls_flash_start__[]; +extern uint32_t __syscalls_flash_end__[]; +extern uint32_t __SRAM_segment_start__[]; +extern uint32_t __SRAM_segment_end__[]; + + +/** + * @brief Shared memory area used between the restricted tasks. + */ +static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ); + +/** + * @brief Statically allocated stack for Read-write access restristed task. + */ +static StackType_t xRWAccessTaskStack[ RESTRICTED_TASK_STACK_SIZE ] __attribute__( ( aligned( RESTRICTED_TASK_STACK_SIZE * sizeof( StackType_t ) ) ) ); + +/* + * @brief The memory region shared between Read only task and hard fault handler. + * + * This is how RO task communicates to handler that it intentionally memory faulted. + * Note, handlers run priviliged thus will have access) + * Also note, 32B is minimum valid size for region*/ +static volatile uint8_t ucROTaskFaultTracker[ MIN_REGION_SIZE ] __attribute__( ( aligned( MIN_REGION_SIZE ) ) ) = { 0 }; + +/** + * @brief Statically allocated stack for Read-only access restristed task. + */ +static StackType_t xROAccessTaskStack[ RESTRICTED_TASK_STACK_SIZE ] __attribute__( ( aligned( RESTRICTED_TASK_STACK_SIZE * sizeof( StackType_t ) ) ) ); + +/* ------------------------------------------------------------------------------- */ + +/** + * @brief This function prints the regions defined in the linker + * script. + */ +void printRegions( void ) +{ + uint32_t * tmp = NULL; + + tmp = __privileged_functions_start__; + tmp = __privileged_functions_end__; + tmp = __FLASH_segment_start__; + tmp = __FLASH_segment_end__; + tmp = __privileged_data_start__; + tmp = __privileged_data_end__; + + ( void ) tmp; + + PRINTF( "\r\n" ); + PRINTF( "privileged functions: %08x - %08x\r\n", __privileged_functions_start__, __privileged_functions_end__ ); + PRINTF( "privileged data: %08x - %08x\r\n", __privileged_data_start__, __privileged_data_end__ ); + PRINTF( "system calls: %08x - %08x\r\n", __syscalls_flash_start__, __syscalls_flash_end__ ); + PRINTF( "flash segment: %08x - %08x\r\n", __FLASH_segment_start__, __FLASH_segment_end__ ); + PRINTF( "sram segment: %08x - %08x\r\n", __SRAM_segment_start__, __SRAM_segment_end__ ); + PRINTF( "\r\n" ); +} + +/** + * @brief A task with read-write access to the variable + * ucSharedMemory. + * + * @param[in] pvParameters Parameter being passed to the + * task. It is not used. + */ +static void prvRWAccessTask( void * pvParameters ) +{ + /* Unused parameters. */ + ( void ) pvParameters; + + ucSharedMemory[ 0 ] = 0; + + while( 1 ) + { + ucSharedMemory[ 0 ] = 1; + MPU_PRINTF( "Ran RW task\r\n" ); + + vTaskDelay( pdMS_TO_TICKS( 500 ) ); + } +} + +/** + * @brief A task without write access to the variable + * ucSharedMemory. Still this task tried to write to it + * triggering a memory fault. + * + * @param[in] pvParameters Parameter being passed to the + * task. It is not used. + */ +static void prvROAccessTask( void * pvParameters ) +{ + uint8_t ucVal; + + /* Unused parameters. */ + ( void ) pvParameters; + ucROTaskFaultTracker[ 0 ] = 0; + + for( ; ; ) + { + /* This task has RO access to ucSharedMemory and therefore it can read + * it but cannot modify it. */ + ucVal = ucSharedMemory[ 0 ]; + + /* Silent compiler warnings about unused variables. */ + ( void ) ucVal; + + #if ( INJECT_TEST_MEMORY_FAULT == 1 ) + ucROTaskFaultTracker[ 0 ] = 1; + + MPU_PRINTF( "Triggering memory violation...\r\n" ); + + /* Illegal access to generate Memory Fault. */ + ucSharedMemory[ 0 ] = 0; + + /* Ensure that the above line did generate MemFault and the fault + * handler did clear the ucROTaskFaultTracker[ 0 ]. */ + if( ucROTaskFaultTracker[ 0 ] == 0 ) + { + MPU_PRINTF( "Access Violation handled.\r\n" ); + } + else + { + MPU_PRINTF( "Error: Access violation should have triggered a fault\r\n" ); + } + #endif /* ifdef INJECT_TEST_MEMORY_FAULT */ + MPU_PRINTF( "Ran RO task\r\n" ); + + vTaskDelay( pdMS_TO_TICKS( 500 ) ); + } +} + +/** + * @brief Create a read only and read write tasks. The read-write + * task has the privilege to write to a given common variable while + * the read-only task doesn't have the privilege to write to the + * variable and still tries to access it creating a memory fault. + * + * @param[in] xPriority The priority at which the RO and RW tasks + * are to be created. + */ +void xCreateRestrictedTasks( BaseType_t xPriority ) +{ + /* Create restricted tasks. */ + TaskParameters_t xRWAccessTaskParameters = + { + .pvTaskCode = prvRWAccessTask, + .pcName = "RWAccess", + .usStackDepth = RESTRICTED_TASK_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = xPriority, + .puxStackBuffer = xRWAccessTaskStack, + .xRegions = + { + { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER }, + { 0, 0, 0 }, + { 0, 0, 0 }, + } + }; + + xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL ); + + TaskParameters_t xROAccessTaskParameters = + { + .pvTaskCode = prvROAccessTask, + .pcName = "ROAccess", + .usStackDepth = RESTRICTED_TASK_STACK_SIZE, + .pvParameters = NULL, + .uxPriority = xPriority, + .puxStackBuffer = xROAccessTaskStack, + .xRegions = + { + { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucROTaskFaultTracker, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER }, + { 0, 0, 0 } + /*{ 0x20000500, 0x100, portMPU_REGION_READ_WRITE }, */ + } + }; + xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL ); +} + + +/* ------------------------------------------------------------------------------- */ + +/** + * @brief The hard fault handler defined by the demo. + * Function takes in hardfaulted stack address, finds out the next instructions to skip to, + * resets the shared flag to zero for read-only task and then skips the stack pointer to the next + * instruction to be executed. + */ +portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress ) +{ + uint32_t ulPC; + uint16_t usOffendingInstruction; + + HardFaultStack_t * const xFaultStack = ( HardFaultStack_t * ) pulFaultStackAddress; + + /* Read program counter. */ + ulPC = xFaultStack->return_address; + + if( ucROTaskFaultTracker[ 0 ] == 1 ) + { + /* Read the offending instruction. */ + usOffendingInstruction = *( uint16_t * ) ulPC; + + /* From ARM docs: + * If the value of bits[15:11] of the halfword being decoded is one of + * the following, the halfword is the first halfword of a 32-bit + * instruction: + * - 0b11101. + * - 0b11110. + * - 0b11111. + * Otherwise, the halfword is a 16-bit instruction. + */ + + /* Extract bits[15:11] of the offending instruction. */ + usOffendingInstruction = usOffendingInstruction & 0xF800; + usOffendingInstruction = ( usOffendingInstruction >> 11 ); + + /* Increment to next instruction, depending on current instruction size (32-bit or 16-bit) */ + if( ( usOffendingInstruction == 0x001F ) || + ( usOffendingInstruction == 0x001E ) || + ( usOffendingInstruction == 0x001D ) ) + { + ulPC += 4; + } + else + { + ulPC += 2; + } + + /* Indicate to RO task its expected fault was handled */ + ucROTaskFaultTracker[ 0 ] = 0; + + /* Resume execution after offending instruction from RO task */ + xFaultStack->return_address = ulPC; + + PRINTF( "Expected memory violation caught by handler...\r\n", ulPC ); + } + else + { + PRINTF( "Memory Access Violation. Inst @ %x\r\n", ulPC ); + + while( 1 ) + { + } + } +} diff --git a/examples/evkbmimxrt1060/sesip/task/demo_restricted_task.h b/examples/evkbmimxrt1060/sesip/task/demo_restricted_task.h new file mode 100644 index 0000000..3159c64 --- /dev/null +++ b/examples/evkbmimxrt1060/sesip/task/demo_restricted_task.h @@ -0,0 +1,46 @@ +/* + * FreeRTOS version 202012.00-LTS + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @brief Header file contains APIs to demonstrate MPU functionalities. + */ + +#ifndef USER_DEMO_RESTRICTED_TASK_H_ +#define USER_DEMO_RESTRICTED_TASK_H_ + +void printRegions( void ); + +/** + * @brief Demo function to create restricted tasks given priority. + * Function creates a read-only task and read-write task to demonstrate the MPU + * functionalities with FreeRTOS tasks. + * + * @param[in] xPriority Priority of the restricted tasks. + */ +void xCreateRestrictedTasks( BaseType_t xPriority ); + +#endif /* USER_DEMO_RESTRICTED_TASK_H_ */ diff --git a/projects/evkmimxrt1060/bootloader/.cproject b/projects/evkmimxrt1060/bootloader/.cproject index 769366d..b242c0b 100644 --- a/projects/evkmimxrt1060/bootloader/.cproject +++ b/projects/evkmimxrt1060/bootloader/.cproject @@ -35,7 +35,7 @@