From 882bbf393f9898f00bd732d11d091bce25a0c051 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 20 Dec 2024 12:21:09 +0100 Subject: [PATCH 1/6] soc: silabs: siwg917: Rename ulpuart0 in ulpuart MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch tries to unify the name the devices on siwx917: - Currently, devices from the Ultra Low Power (ULP) domain are sometime numbered sometime not. Since there is at most one instance of each device in the ULP domain, just drop the numbering. - Keep numbering for device outside of ULP. The numbering sometime start with 0, sometime with 1. We keep this weirdness, since it is used in the reference manual. Signed-off-by: Jérôme Pouiller --- .../radio_boards/siwx917_rb4338a/siwx917_rb4338a.dts | 10 +++++----- dts/arm/silabs/siwg917.dtsi | 2 +- dts/bindings/pinctrl/silabs,siwx917-pinctrl.yaml | 10 +++++----- soc/silabs/silabs_siwx917/siwg917/soc.c | 2 +- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.dts b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.dts index 0ea5768..f7375a4 100644 --- a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.dts +++ b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.dts @@ -18,8 +18,8 @@ chosen { zephyr,sram = &sram0; zephyr,code-partition = &code_partition; - zephyr,console = &ulpuart0; - zephyr,shell-uart = &ulpuart0; + zephyr,console = &ulpuart; + zephyr,shell-uart = &ulpuart; zephyr,bt-hci = &bt_hci_silabs_siwx917; }; @@ -63,9 +63,9 @@ status = "okay"; }; -&ulpuart0 { +&ulpuart { status = "okay"; - pinctrl-0 = <&ulpuart0_default>; + pinctrl-0 = <&ulpuart_default>; pinctrl-names = "default"; }; @@ -83,7 +83,7 @@ }; &pinctrl0 { - ulpuart0_default: ulpuart0_default { + ulpuart_default: ulpuart_default { out { pinmux = ; }; diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi index 4dec4e8..ec6844e 100644 --- a/dts/arm/silabs/siwg917.dtsi +++ b/dts/arm/silabs/siwg917.dtsi @@ -59,7 +59,7 @@ }; }; - ulpuart0: uart@24041800 { + ulpuart: uart@24041800 { compatible = "ns16550"; reg = <0x24041800 0x1000>; interrupts = <12 0>; diff --git a/dts/bindings/pinctrl/silabs,siwx917-pinctrl.yaml b/dts/bindings/pinctrl/silabs,siwx917-pinctrl.yaml index 1ad4a51..3c01b4a 100644 --- a/dts/bindings/pinctrl/silabs,siwx917-pinctrl.yaml +++ b/dts/bindings/pinctrl/silabs,siwx917-pinctrl.yaml @@ -9,18 +9,18 @@ description: | The pinctrl settings are referenced in a device tree peripheral node. For example when configuring a UART: - &ulpuart0 { - pinctrl-0 = <&ulpuart0_default>; + &ulpuart { + pinctrl-0 = <&ulpuart_default>; pinctrl-names = "default"; } pinctrl-0 is a phandle that stores the pin settings for the peripheral, in - this example &ulpuart0_default. This phandle is defined as a child node of the + this example &ulpuart_default. This phandle is defined as a child node of the 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board directory or a device tree overlay in the application: &pinctrl { - ulpuart0_default: ulpuart0_default { + ulpuart_default: ulpuart_default { out { pinmux = ; /* Configure ULP pin 11 as ULPUART TX */ }; @@ -30,7 +30,7 @@ description: | }; }; - The 'ulpuart0_default' child node encodes the pin configurations for a + The 'ulpuart_default' child node encodes the pin configurations for a particular state of the device, the default (active) state. Pin configurations are organized in groups within each child node. The name diff --git a/soc/silabs/silabs_siwx917/siwg917/soc.c b/soc/silabs/silabs_siwx917/siwg917/soc.c index 3d58bef..8ad1529 100644 --- a/soc/silabs/silabs_siwx917/siwg917/soc.c +++ b/soc/silabs/silabs_siwx917/siwg917/soc.c @@ -27,7 +27,7 @@ int silabs_siwx917_init(void) PLL_REF_CLK_VAL_XTAL); /* FIXME: do not hardcode UART instances */ -#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpuart0), okay) +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpuart), okay) RSI_ULPSS_UlpUartClkConfig(ULPCLK, ENABLE_STATIC_CLK, 0, ULP_UART_ULP_32MHZ_RC_CLK, 1); #endif #if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) From 8681798fc63984eec52a0b42909eb80e2d61375a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 20 Dec 2024 12:22:48 +0100 Subject: [PATCH 2/6] soc: silabs: siwg917: Rename udma1 in ulpdma MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch tries to unify the name the devices on siwx917: - All the devices in the Ultra Low Power are prefixed with ULP. - Currently, devices from the Ultra Low Power (ULP) domain are sometime numbered sometime not. Since there is at most 1 instance of each device in the ULP domain, just drop the numbering. Note, we still use a reference to "udma1" in the linker file since this reference is shared with WiseConnect. Signed-off-by: Jérôme Pouiller --- drivers/dma/dma_silabs_siwx917.c | 10 +++++----- dts/arm/silabs/siwg917.dtsi | 4 ++-- dts/bindings/dma/silabs,siwx917-dma.yaml | 2 +- soc/silabs/silabs_siwx917/siwg917/soc.c | 2 +- .../chan_blen_transfer/boards/siwx917_rb4338a.overlay | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/dma/dma_silabs_siwx917.c b/drivers/dma/dma_silabs_siwx917.c index c404fe3..79a15d2 100644 --- a/drivers/dma/dma_silabs_siwx917.c +++ b/drivers/dma/dma_silabs_siwx917.c @@ -169,7 +169,7 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, void *udma_handle = &data->dma_rom_buff; int status; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for udma1 */ + /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } @@ -204,7 +204,7 @@ static int dma_siwx917_reload(const struct device *dev, uint32_t channel, uint32 uint32_t length; RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for udma1 */ + /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } @@ -252,7 +252,7 @@ static int dma_siwx917_start(const struct device *dev, uint32_t channel) struct dma_siwx917_data *data = dev->data; void *udma_handle = &data->dma_rom_buff; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for udma1 */ + /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } @@ -276,7 +276,7 @@ static int dma_siwx917_stop(const struct device *dev, uint32_t channel) struct dma_siwx917_data *data = dev->data; void *udma_handle = &data->dma_rom_buff; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for udma1 */ + /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } @@ -293,7 +293,7 @@ static int dma_siwx917_get_status(const struct device *dev, uint32_t channel, const struct dma_siwx917_config *cfg = dev->config; RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for udma1 */ + /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi index ec6844e..3a11be5 100644 --- a/dts/arm/silabs/siwg917.dtsi +++ b/dts/arm/silabs/siwg917.dtsi @@ -235,13 +235,13 @@ status = "disabled"; }; - udma1: dma@24078000 { + ulpdma: dma@24078000 { compatible = "silabs,siwx917-dma"; #address-cells = <1>; #size-cells = <0>; reg = <0x24078000 0x82C>; interrupts = <10 0>; - interrupt-names = "udma1"; + interrupt-names = "ulpdma"; silabs,sram-desc-addr = <0x24061c00>; #dma-cells = < 1>; dma-channels = <12>; diff --git a/dts/bindings/dma/silabs,siwx917-dma.yaml b/dts/bindings/dma/silabs,siwx917-dma.yaml index 37251b3..9f67134 100644 --- a/dts/bindings/dma/silabs,siwx917-dma.yaml +++ b/dts/bindings/dma/silabs,siwx917-dma.yaml @@ -14,7 +14,7 @@ properties: description: | SRAM Address for UDMA Descriptor Storage. This address must correspond to the location of the udma_addr0 section in the linker script for the udma0 node, and the udma_addr1 - section for the udma1 node. Ensure that the value specified for the SRAM address matches + section for the ulpdma node. Ensure that the value specified for the SRAM address matches the respective section defined in the linker file for each UDMA node, as this alignment is critical for proper descriptor management and data transfer. diff --git a/soc/silabs/silabs_siwx917/siwg917/soc.c b/soc/silabs/silabs_siwx917/siwg917/soc.c index 8ad1529..7e2e5c5 100644 --- a/soc/silabs/silabs_siwx917/siwg917/soc.c +++ b/soc/silabs/silabs_siwx917/siwg917/soc.c @@ -52,7 +52,7 @@ int silabs_siwx917_init(void) RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); RSI_CLK_PeripheralClkEnable(M4CLK, UDMA_CLK, ENABLE_STATIC_CLK); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(udma1), okay) +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpdma), okay) RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UDMA); RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_UDMA_CLK, ENABLE_STATIC_CLK); #endif diff --git a/tests/drivers/dma/chan_blen_transfer/boards/siwx917_rb4338a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/siwx917_rb4338a.overlay index c1de2ed..c658f7c 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/siwx917_rb4338a.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/siwx917_rb4338a.overlay @@ -8,6 +8,6 @@ tst_dma0: &udma0 { status = "okay"; }; -tst_dma1: &udma1 { +tst_dma1: &ulpdma { status = "okay"; }; From 652a099fc21d1ad16a8c1d478e894ef261a66283 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 20 Dec 2024 12:23:40 +0100 Subject: [PATCH 3/6] soc: silabs: siwg917: Rename udma0 in dma0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch tries to unify the name the devices on siwx917. We tends to name the node with their role (UART, DMA, ...) rather than with the name of the hardware block (UDMA). So, rename "udma0" in "dma0". Note, we still use a reference to `udma0` in the linker file since this reference is shared with WiseConnect. Signed-off-by: Jérôme Pouiller --- drivers/dma/dma_silabs_siwx917.c | 10 +++++----- dts/arm/silabs/siwg917.dtsi | 4 ++-- dts/bindings/dma/silabs,siwx917-dma.yaml | 2 +- soc/silabs/silabs_siwx917/siwg917/soc.c | 2 +- .../chan_blen_transfer/boards/siwx917_rb4338a.overlay | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/dma/dma_silabs_siwx917.c b/drivers/dma/dma_silabs_siwx917.c index 79a15d2..245c3c6 100644 --- a/drivers/dma/dma_silabs_siwx917.c +++ b/drivers/dma/dma_silabs_siwx917.c @@ -169,7 +169,7 @@ static int dma_siwx917_configure(const struct device *dev, uint32_t channel, void *udma_handle = &data->dma_rom_buff; int status; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ + /* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } @@ -204,7 +204,7 @@ static int dma_siwx917_reload(const struct device *dev, uint32_t channel, uint32 uint32_t length; RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ + /* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } @@ -252,7 +252,7 @@ static int dma_siwx917_start(const struct device *dev, uint32_t channel) struct dma_siwx917_data *data = dev->data; void *udma_handle = &data->dma_rom_buff; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ + /* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } @@ -276,7 +276,7 @@ static int dma_siwx917_stop(const struct device *dev, uint32_t channel) struct dma_siwx917_data *data = dev->data; void *udma_handle = &data->dma_rom_buff; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ + /* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } @@ -293,7 +293,7 @@ static int dma_siwx917_get_status(const struct device *dev, uint32_t channel, const struct dma_siwx917_config *cfg = dev->config; RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr; - /* Expecting a fixed channel number between 0-31 for udma0 and 0-11 for ulpdma */ + /* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */ if (channel >= cfg->channels) { return -EINVAL; } diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi index 3a11be5..e4e4cfb 100644 --- a/dts/arm/silabs/siwg917.dtsi +++ b/dts/arm/silabs/siwg917.dtsi @@ -222,13 +222,13 @@ reg = <0x45090000 0x8>; }; - udma0: dma@44030000 { + dma0: dma@44030000 { compatible = "silabs,siwx917-dma"; #address-cells = <1>; #size-cells = <0>; reg = <0x44030000 0x82C>; interrupts = <33 0>; - interrupt-names = "udma0"; + interrupt-names = "dma0"; silabs,sram-desc-addr = <0x2fc00>; #dma-cells = < 1>; dma-channels = <32>; diff --git a/dts/bindings/dma/silabs,siwx917-dma.yaml b/dts/bindings/dma/silabs,siwx917-dma.yaml index 9f67134..0136291 100644 --- a/dts/bindings/dma/silabs,siwx917-dma.yaml +++ b/dts/bindings/dma/silabs,siwx917-dma.yaml @@ -13,7 +13,7 @@ properties: required: true description: | SRAM Address for UDMA Descriptor Storage. This address must correspond to the location - of the udma_addr0 section in the linker script for the udma0 node, and the udma_addr1 + of the udma_addr0 section in the linker script for the dma0 node, and the udma_addr1 section for the ulpdma node. Ensure that the value specified for the SRAM address matches the respective section defined in the linker file for each UDMA node, as this alignment is critical for proper descriptor management and data transfer. diff --git a/soc/silabs/silabs_siwx917/siwg917/soc.c b/soc/silabs/silabs_siwx917/siwg917/soc.c index 7e2e5c5..304d67f 100644 --- a/soc/silabs/silabs_siwx917/siwg917/soc.c +++ b/soc/silabs/silabs_siwx917/siwg917/soc.c @@ -48,7 +48,7 @@ int silabs_siwx917_init(void) RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2C); RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2C_CLK, ENABLE_STATIC_CLK); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(udma0), okay) +#if DT_NODE_HAS_STATUS(DT_NODELABEL(dma0), okay) RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); RSI_CLK_PeripheralClkEnable(M4CLK, UDMA_CLK, ENABLE_STATIC_CLK); #endif diff --git a/tests/drivers/dma/chan_blen_transfer/boards/siwx917_rb4338a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/siwx917_rb4338a.overlay index c658f7c..d3ac62d 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/siwx917_rb4338a.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/siwx917_rb4338a.overlay @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -tst_dma0: &udma0 { +tst_dma0: &dma0 { status = "okay"; }; From 8190731dfa9fb28b95e1b55418ef48dc7c31e683 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Wed, 8 Jan 2025 17:20:58 +0100 Subject: [PATCH 4/6] soc: silabs: siwg917: Import clock_update.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit clock_update.c provides RSI_CLK_GetBaseClock(). Signed-off-by: Jérôme Pouiller --- modules/hal_silabs/wiseconnect/CMakeLists.txt | 1 + west.yml | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/modules/hal_silabs/wiseconnect/CMakeLists.txt b/modules/hal_silabs/wiseconnect/CMakeLists.txt index 45bfef0..4f64cdb 100644 --- a/modules/hal_silabs/wiseconnect/CMakeLists.txt +++ b/modules/hal_silabs/wiseconnect/CMakeLists.txt @@ -44,6 +44,7 @@ zephyr_compile_definitions_ifdef(CONFIG_SIWX917_FLASH_MODE_COMMON zephyr_library_sources( ${DEVICE_DIR}/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c ${DEVICE_DIR}/silabs/si91x/mcu/core/chip/src/system_si91x.c + ${DEVICE_DIR}/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c ${DEVICE_DIR}/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c ${DEVICE_DIR}/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c ${DEVICE_DIR}/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c diff --git a/west.yml b/west.yml index a901be1..0e86295 100644 --- a/west.yml +++ b/west.yml @@ -11,7 +11,7 @@ manifest: projects: - name: hal_silabs remote: silabs - revision: 24b2879d7a3e0129bad22cb1dc513d1493a08323 + revision: 73c8b43d22bbf11ba0bc3bde4969a4cb8fe296a4 path: modules/hal/silabs - name: zephyr remote: zephyrproject-rtos From 297ddc974f96e0e98e14f77ccc02fd07da0df233 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Tue, 17 Dec 2024 16:41:01 +0100 Subject: [PATCH 5/6] drivers: clock: siwx917: Add dumb clock driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This driver is mostly the initial seed for further implementation of a real clock driver. Currently, sinc ethe driver do not enable the clock sources, this driver still contains the series of #ifdef to enable the clocks. It also doesn't allow the user to choose the clock source for the various peripherals. The driver hardcodes some sane values. Signed-off-by: Jérôme Pouiller --- .../siwx917_rb4338a/siwx917_rb4338a_defconfig | 1 + drivers/CMakeLists.txt | 1 + drivers/clock_control/CMakeLists.txt | 5 + drivers/clock_control/Kconfig | 8 + drivers/clock_control/Kconfig.siwx917 | 15 ++ .../clock_control_silabs_siwx917.c | 206 ++++++++++++++++++ dts/arm/silabs/siwg917.dtsi | 22 +- dts/bindings/clock/silabs,siwx917-clock.yaml | 18 ++ .../dt-bindings/clock/silabs/siwx917-clock.h | 16 ++ soc/silabs/silabs_siwx917/siwg917/soc.c | 42 ---- 10 files changed, 289 insertions(+), 45 deletions(-) create mode 100644 drivers/clock_control/CMakeLists.txt create mode 100644 drivers/clock_control/Kconfig create mode 100644 drivers/clock_control/Kconfig.siwx917 create mode 100644 drivers/clock_control/clock_control_silabs_siwx917.c create mode 100644 dts/bindings/clock/silabs,siwx917-clock.yaml create mode 100644 include/zephyr/dt-bindings/clock/silabs/siwx917-clock.h diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig index b008914..64142ee 100644 --- a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig +++ b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig @@ -6,5 +6,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_PINCTRL=y +CONFIG_CLOCK_CONTROL=y CONFIG_SIWX917_FLASH_MODE_COMMON=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index 5cbf42f..b239ee4 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -2,6 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory(bluetooth) +add_subdirectory(clock_control) add_subdirectory(entropy) add_subdirectory(flash) add_subdirectory(gpio) diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt new file mode 100644 index 0000000..bd35fb6 --- /dev/null +++ b/drivers/clock_control/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_amend() +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SILABS_SIWX917 clock_control_silabs_siwx917.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig new file mode 100644 index 0000000..5aa3133 --- /dev/null +++ b/drivers/clock_control/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +if CLOCK_CONTROL + +rsource "Kconfig.siwx917" + +endif diff --git a/drivers/clock_control/Kconfig.siwx917 b/drivers/clock_control/Kconfig.siwx917 new file mode 100644 index 0000000..60c7460 --- /dev/null +++ b/drivers/clock_control/Kconfig.siwx917 @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +config CLOCK_CONTROL_SILABS_SIWX917 + bool "SiWx917 clock control driver" + default y + depends on DT_HAS_SILABS_SIWX917_CLOCK_ENABLED + help + Enable clock management on Silicon Labs SiWx917 chips. This driver + includes support for HP (High Performace), ULP (Ultra Low Power), and + ULP VBAT clocks. + + The original hardware allow to customize the various clocks offered for + every devices. This driver does not provide such customizations. It + just hardcodes sane default parameters for every devices. diff --git a/drivers/clock_control/clock_control_silabs_siwx917.c b/drivers/clock_control/clock_control_silabs_siwx917.c new file mode 100644 index 0000000..d812e67 --- /dev/null +++ b/drivers/clock_control/clock_control_silabs_siwx917.c @@ -0,0 +1,206 @@ +/* Copyright (c) 2024 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Poor man driver for 917 clocks. 917 includes High Performace (HP) clock + * (@46000000), Ultra Lower Power (ULP) clock (@24041400) and ULP VBAT (@24048000) + * + */ +#include +#include +#include + +#include "rsi_power_save.h" +#include "rsi_rom_ulpss_clk.h" +#include "rsi_rom_clks.h" +#include "clock_update.h" +#include "sl_si91x_clock_manager.h" + +#define DT_DRV_COMPAT silabs_siwx917_clock + +LOG_MODULE_REGISTER(siwx917_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL); + +struct siwx917_clock_data { + uint32_t enable; +}; + +static int siwx917_clock_on(const struct device *dev, clock_control_subsys_t sys) +{ + struct siwx917_clock_data *data = dev->data; + uintptr_t clockid = (uintptr_t)sys; + + switch (clockid) { + case SIWX917_CLK_ULP_UART: + RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UART); + RSI_ULPSS_UlpUartClkConfig(ULPCLK, ENABLE_STATIC_CLK, + false, ULP_UART_ULP_32MHZ_RC_CLK, 1); + break; + case SIWX917_CLK_ULP_I2C: + RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2C); + RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2C_CLK, ENABLE_STATIC_CLK); + break; + case SIWX917_CLK_ULP_DMA: + RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UDMA); + RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_UDMA_CLK, ENABLE_STATIC_CLK); + break; + case SIWX917_CLK_UART1: + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + /* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */ + RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART1, 0, 1); + break; + case SIWX917_CLK_UART2: + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + /* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */ + RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART2, 0, 1); + break; + case SIWX917_CLK_I2C0: + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + RSI_CLK_I2CClkConfig(M4CLK, true, 0); + break; + case SIWX917_CLK_I2C1: + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + RSI_CLK_I2CClkConfig(M4CLK, true, 1); + break; + case SIWX917_CLK_DMA0: + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + RSI_CLK_PeripheralClkEnable(M4CLK, UDMA_CLK, ENABLE_STATIC_CLK); + break; + default: + return -EINVAL; + } + data->enable |= BIT(clockid); + + return 0; +} + +static int siwx917_clock_off(const struct device *dev, clock_control_subsys_t sys) +{ + struct siwx917_clock_data *data = dev->data; + uintptr_t clockid = (uintptr_t)sys; + + switch (clockid) { + case SIWX917_CLK_ULP_I2C: + RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_I2C_CLK); + break; + case SIWX917_CLK_ULP_DMA: + RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_UDMA_CLK); + break; + case SIWX917_CLK_UART1: + RSI_CLK_PeripheralClkDisable(M4CLK, USART1_CLK); + break; + case SIWX917_CLK_UART2: + RSI_CLK_PeripheralClkDisable(M4CLK, USART2_CLK); + break; + case SIWX917_CLK_DMA0: + RSI_CLK_PeripheralClkDisable(M4CLK, UDMA_CLK); + break; + case SIWX917_CLK_ULP_UART: + case SIWX917_CLK_I2C0: + case SIWX917_CLK_I2C1: + /* Not supported */ + return 0; + default: + return -EINVAL; + } + + data->enable &= ~BIT(clockid); + return 0; +} + +static int siwx917_clock_get_rate(const struct device *dev, clock_control_subsys_t sys, + uint32_t *rate) +{ + uintptr_t clockid = (uintptr_t)sys; + + switch (clockid) { + case SIWX917_CLK_ULP_UART: + *rate = RSI_CLK_GetBaseClock(ULPSS_UART); + return 0; + case SIWX917_CLK_UART1: + *rate = RSI_CLK_GetBaseClock(M4_USART0); + return 0; + case SIWX917_CLK_UART2: + *rate = RSI_CLK_GetBaseClock(M4_UART1); + return 0; + default: + /* For now, no other driver need clock rate */ + return -EINVAL; + } +} + +static enum clock_control_status siwx917_clock_get_status(const struct device *dev, + clock_control_subsys_t sys) +{ + struct siwx917_clock_data *data = dev->data; + uintptr_t clockid = (uintptr_t)sys; + + if (data->enable & BIT(clockid)) { + return CLOCK_CONTROL_STATUS_ON; + } else { + return CLOCK_CONTROL_STATUS_OFF; + } +} + +static int siwx917_clock_init(const struct device *dev) +{ + SystemCoreClockUpdate(); + + /* Use SoC PLL at configured frequency as core clock */ + sl_si91x_clock_manager_m4_set_core_clk(M4_SOCPLLCLK, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + + /* Use interface PLL at configured frequency as peripheral clock */ + sl_si91x_clock_manager_set_pll_freq(INFT_PLL, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + PLL_REF_CLK_VAL_XTAL); + + /* FIXME: Currently the clock consumer use clocks without power on them. + * This should be fixed in drivers. Meanwhile, get the list of required + * clocks using DT labels. + */ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpuart), okay) + siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_ULP_UART); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpi2c), okay) + siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_ULP_I2C); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpdma), okay) + siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_ULP_DMA); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) + siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_UART1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) + siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_UART2); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c0), okay) + siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_I2C0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay) + siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_I2C1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(udma0), okay) + siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_DMA0); +#endif + + return 0; +} + +static const struct clock_control_driver_api siwx917_clock_api = { + .on = siwx917_clock_on, + .off = siwx917_clock_off, + .get_rate = siwx917_clock_get_rate, + .get_status = siwx917_clock_get_status, +}; + +#define SIWX917_CLOCK_INIT(p) \ + static struct siwx917_clock_data siwx917_clock_data_##p; \ + DEVICE_DT_INST_DEFINE(p, siwx917_clock_init, NULL, &siwx917_clock_data_##p, NULL, \ + PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \ + &siwx917_clock_api); + +DT_INST_FOREACH_STATUS_OKAY(SIWX917_CLOCK_INIT) diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi index e4e4cfb..3e202a2 100644 --- a/dts/arm/silabs/siwg917.dtsi +++ b/dts/arm/silabs/siwg917.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { chosen { @@ -41,6 +42,16 @@ }; soc { + clock0: clock@46000000 { + compatible = "silabs,siwx917-clock"; + reg = <0x46000000 0x100>, + <0x46000800 0x100>, + <0x24041400 0x100>, + <0x24048000 0x200>; + #clock-cells = <1>; + status = "okay"; + }; + pinctrl0: pinctrl@46130000 { compatible = "silabs,siwx917-pinctrl"; reg = <0x46130000 0x1000>; @@ -64,7 +75,7 @@ reg = <0x24041800 0x1000>; interrupts = <12 0>; reg-shift = <2>; - clock-frequency = <32000000>; + clocks = <&clock0 SIWX917_CLK_ULP_UART>; current-speed = <115200>; status = "disabled"; }; @@ -74,7 +85,7 @@ reg = <0x44000000 0x1000>; interrupts = <38 0>; reg-shift = <2>; - clock-frequency = <25000000>; + clocks = <&clock0 SIWX917_CLK_UART1>; current-speed = <115200>; status = "disabled"; }; @@ -84,7 +95,7 @@ reg = <0x45020000 0x1000>; interrupts = <39 0>; reg-shift = <2>; - clock-frequency = <20000000>; + clocks = <&clock0 SIWX917_CLK_UART2>; current-speed = <115200>; status = "disabled"; }; @@ -194,6 +205,7 @@ reg = <0x44010000 0x100>; interrupts = <42 0>; interrupt-names = "i2c0"; + clocks = <&clock0 SIWX917_CLK_I2C0>; status = "disabled"; }; @@ -204,6 +216,7 @@ reg = <0x47040000 0x100>; interrupts = <61 0>; interrupt-names = "i2c1"; + clocks = <&clock0 SIWX917_CLK_I2C1>; status = "disabled"; }; @@ -214,6 +227,7 @@ reg = <0x24040000 0x100>; interrupts = <13 0>; interrupt-names = "i2c2"; + clocks = <&clock0 SIWX917_CLK_ULP_I2C>; status = "disabled"; }; @@ -229,6 +243,7 @@ reg = <0x44030000 0x82C>; interrupts = <33 0>; interrupt-names = "dma0"; + clocks = <&clock0 SIWX917_CLK_DMA0>; silabs,sram-desc-addr = <0x2fc00>; #dma-cells = < 1>; dma-channels = <32>; @@ -242,6 +257,7 @@ reg = <0x24078000 0x82C>; interrupts = <10 0>; interrupt-names = "ulpdma"; + clocks = <&clock0 SIWX917_CLK_ULP_DMA>; silabs,sram-desc-addr = <0x24061c00>; #dma-cells = < 1>; dma-channels = <12>; diff --git a/dts/bindings/clock/silabs,siwx917-clock.yaml b/dts/bindings/clock/silabs,siwx917-clock.yaml new file mode 100644 index 0000000..12f7074 --- /dev/null +++ b/dts/bindings/clock/silabs,siwx917-clock.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: Clocks embedded on Silabs SiWx917 chips + +compatible: "silabs,siwx917-clock" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 1 + +clock-cells: + - clkid diff --git a/include/zephyr/dt-bindings/clock/silabs/siwx917-clock.h b/include/zephyr/dt-bindings/clock/silabs/siwx917-clock.h new file mode 100644 index 0000000..97fdb9c --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/siwx917-clock.h @@ -0,0 +1,16 @@ +/* Copyright (c) 2024 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX917_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX917_CLOCK_H_ + +#define SIWX917_CLK_ULP_UART 0 +#define SIWX917_CLK_ULP_I2C 1 +#define SIWX917_CLK_ULP_DMA 2 +#define SIWX917_CLK_UART1 3 +#define SIWX917_CLK_UART2 4 +#define SIWX917_CLK_I2C0 5 +#define SIWX917_CLK_I2C1 6 +#define SIWX917_CLK_DMA0 7 + +#endif diff --git a/soc/silabs/silabs_siwx917/siwg917/soc.c b/soc/silabs/silabs_siwx917/siwg917/soc.c index 304d67f..6f3586f 100644 --- a/soc/silabs/silabs_siwx917/siwg917/soc.c +++ b/soc/silabs/silabs_siwx917/siwg917/soc.c @@ -15,48 +15,6 @@ int silabs_siwx917_init(void) { SystemInit(); - SystemCoreClockUpdate(); - - /* Use SoC PLL at configured frequency as core clock */ - sl_si91x_clock_manager_m4_set_core_clk(M4_SOCPLLCLK, - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); - - /* Use interface PLL at configured frequency as peripheral clock */ - sl_si91x_clock_manager_set_pll_freq(INFT_PLL, - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, - PLL_REF_CLK_VAL_XTAL); - - /* FIXME: do not hardcode UART instances */ -#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpuart), okay) - RSI_ULPSS_UlpUartClkConfig(ULPCLK, ENABLE_STATIC_CLK, 0, ULP_UART_ULP_32MHZ_RC_CLK, 1); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) - RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART1, 0, 1); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) - RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART2, 0, 1); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c0), okay) - RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); - RSI_CLK_I2CClkConfig(M4CLK, true, 0); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay) - RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); - RSI_CLK_I2CClkConfig(M4CLK, true, 1); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpi2c), okay) - RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2C); - RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2C_CLK, ENABLE_STATIC_CLK); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(dma0), okay) - RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); - RSI_CLK_PeripheralClkEnable(M4CLK, UDMA_CLK, ENABLE_STATIC_CLK); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpdma), okay) - RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UDMA); - RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_UDMA_CLK, ENABLE_STATIC_CLK); -#endif - return 0; } SYS_INIT(silabs_siwx917_init, PRE_KERNEL_1, 0); From 7cfab048bc0413277e3505469b42d5b2b3864a0c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= Date: Fri, 20 Dec 2024 16:52:20 +0100 Subject: [PATCH 6/6] drivers: dma: siwx917: Manage the clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SiWx917 DMA is now able to enable the clock when required. Signed-off-by: Jérôme Pouiller --- drivers/clock_control/clock_control_silabs_siwx917.c | 8 -------- drivers/dma/dma_silabs_siwx917.c | 11 +++++++++++ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/clock_control/clock_control_silabs_siwx917.c b/drivers/clock_control/clock_control_silabs_siwx917.c index d812e67..a500665 100644 --- a/drivers/clock_control/clock_control_silabs_siwx917.c +++ b/drivers/clock_control/clock_control_silabs_siwx917.c @@ -163,10 +163,6 @@ static int siwx917_clock_init(const struct device *dev) siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_ULP_I2C); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpdma), okay) - siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_ULP_DMA); -#endif - #if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_UART1); #endif @@ -183,10 +179,6 @@ static int siwx917_clock_init(const struct device *dev) siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_I2C1); #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(udma0), okay) - siwx917_clock_on(dev, (clock_control_subsys_t)SIWX917_CLK_DMA0); -#endif - return 0; } diff --git a/drivers/dma/dma_silabs_siwx917.c b/drivers/dma/dma_silabs_siwx917.c index 245c3c6..a196c43 100644 --- a/drivers/dma/dma_silabs_siwx917.c +++ b/drivers/dma/dma_silabs_siwx917.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include "rsi_rom_udma_wrapper.h" @@ -29,6 +30,8 @@ struct dma_siwx917_config { uint8_t channels; /* UDMA channel count */ uint8_t irq_number; /* IRQ number */ RSI_UDMA_DESC_T *sram_desc_addr; /* SRAM Address for UDMA Descriptor Storage */ + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; void (*irq_configure)(void); /* IRQ configure function */ }; @@ -326,6 +329,12 @@ static int dma_siwx917_init(const struct device *dev) .udma_irq_num = cfg->irq_number, .desc = cfg->sram_desc_addr, }; + int ret; + + ret = clock_control_on(cfg->clock_dev, cfg->clock_subsys); + if (ret) { + return ret; + } udma_handle = UDMAx_Initialize(&udma_resources, udma_resources.desc, NULL, (uint32_t *)&data->dma_rom_buff); @@ -406,6 +415,8 @@ static const struct dma_driver_api siwx917_dma_driver_api = { irq_enable(DT_INST_IRQ(inst, irq)); \ } \ static const struct dma_siwx917_config dma##inst##_cfg = { \ + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \ + .clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid), \ .reg = (UDMA0_Type *)DT_INST_REG_ADDR(inst), \ .channels = DT_INST_PROP(inst, dma_channels), \ .irq_number = DT_INST_PROP_BY_IDX(inst, interrupts, 0), \