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Bus address width is a generic on the top-levels, but it's not a generic for the widths of output registers for vhdmmio (understandibly).
The easiest way to fix this would be to remove the generic from the top-level and only allow it to be set through the command-line parameters of Fletchgen.
Another way to fix it would be to resize it before it enters the corresponding ACCM instance at the nucleus level, but it would be a bit obscure, since the generated vhdmmio docs won't convey the limited number of bits used to represent addresses.
The text was updated successfully, but these errors were encountered:
johanpel
changed the title
[Fletchgen] Mismatch between bus address width and addresses passed through vhdmmio
Mismatch between bus address width and addresses passed through vhdmmio
Oct 1, 2020
Bus address width is a generic on the top-levels, but it's not a generic for the widths of output registers for vhdmmio (understandibly).
The easiest way to fix this would be to remove the generic from the top-level and only allow it to be set through the command-line parameters of Fletchgen.
Another way to fix it would be to resize it before it enters the corresponding ACCM instance at the nucleus level, but it would be a bit obscure, since the generated vhdmmio docs won't convey the limited number of bits used to represent addresses.
The text was updated successfully, but these errors were encountered: