diff --git a/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h b/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h index a7d102313..9b3372578 100644 --- a/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h +++ b/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_armclang_a.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.2.3 - * @date 11. October 2023 - ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(A) Compiler ARMClang (Arm Compiler 6) Header File + */ + #ifndef __CMSIS_ARMCLANG_A_H #define __CMSIS_ARMCLANG_A_H @@ -102,6 +100,7 @@ #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif + /* ########################## Core Instruction Access ######################### */ /** \brief No Operation @@ -109,6 +108,7 @@ */ #define __NOP __builtin_arm_nop + /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. @@ -218,6 +218,7 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) */ #define __RBIT __builtin_arm_rbit + /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. @@ -242,6 +243,7 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) return __builtin_clz(value); } + /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. @@ -502,7 +504,7 @@ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); + return (result); } #endif /* (__ARM_FEATURE_DSP == 1) */ @@ -707,23 +709,23 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) __STATIC_INLINE void __FPU_Enable(void) { __ASM volatile( - //Permit access to VFP/NEON, registers by modifying CPACR + // Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" " ORR R1,R1,#0x00F00000 \n" " MCR p15,0,R1,c1,c0,2 \n" - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + // Ensure that subsequent instructions occur in the context of VFP/NEON access permitted " ISB \n" - //Enable VFP/NEON + // Enable VFP/NEON " VMRS R1,FPEXC \n" " ORR R1,R1,#0x40000000 \n" " VMSR FPEXC,R1 \n" - //Initialise VFP/NEON registers to 0 + // Initialise VFP/NEON registers to 0 " MOV R2,#0 \n" - //Initialise D16 registers to 0 + // Initialise D16 registers to 0 " VMOV D0, R2,R2 \n" " VMOV D1, R2,R2 \n" " VMOV D2, R2,R2 \n" @@ -742,7 +744,7 @@ __STATIC_INLINE void __FPU_Enable(void) " VMOV D15,R2,R2 \n" #if (defined(__ARM_NEON) && (__ARM_NEON == 1)) - //Initialise D32 registers to 0 + // Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" " VMOV D18,R2,R2 \n" @@ -761,7 +763,7 @@ __STATIC_INLINE void __FPU_Enable(void) " VMOV D31,R2,R2 \n" #endif - //Initialise FPSCR to a known state + // Initialise FPSCR to a known state " VMRS R1,FPSCR \n" " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " AND R1,R1,R2 \n" diff --git a/CMSIS/Core/Include/a-profile/cmsis_clang_a.h b/CMSIS/Core/Include/a-profile/cmsis_clang_a.h index b38b58f86..49057b8d9 100644 --- a/CMSIS/Core/Include/a-profile/cmsis_clang_a.h +++ b/CMSIS/Core/Include/a-profile/cmsis_clang_a.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_clang_a.h - * @brief CMSIS compiler Clang header file - * @version V0.1.0 - * @date 24. October 2023 - ******************************************************************************/ /* * Copyright (c) 2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(A) Compiler LLVM/Clang Header File + */ + #ifndef __CMSIS_CLANG_A_H #define __CMSIS_CLANG_A_H @@ -113,6 +111,7 @@ */ #define __NOP() __ASM volatile ("nop") + /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. @@ -285,6 +284,7 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) return __builtin_clz(value); } + /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. @@ -600,7 +600,8 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) /* ################### Compiler specific Intrinsics ########################### */ -#if (__ARM_FEATURE_DSP == 1) +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __builtin_arm_sadd8 #define __QADD8 __builtin_arm_qadd8 #define __SHADD8 __builtin_arm_shadd8 diff --git a/CMSIS/Core/Include/a-profile/cmsis_cp15.h b/CMSIS/Core/Include/a-profile/cmsis_cp15.h index e68f0537a..a20e9d8fa 100644 --- a/CMSIS/Core/Include/a-profile/cmsis_cp15.h +++ b/CMSIS/Core/Include/a-profile/cmsis_cp15.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_cp15.h - * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.0.2 - * @date 19. December 2022 - ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * @@ -22,13 +16,17 @@ * limitations under the License. */ +/* + * CMSIS-Core(A) Compiler Specific Macros, Functions, Instructions + */ + #ifndef __CMSIS_CP15_H #define __CMSIS_CP15_H #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ #endif /** \brief Get ACTLR diff --git a/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h b/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h index d25bdedca..8e77efcda 100644 --- a/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h +++ b/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_gcc_a.h - * @brief CMSIS compiler GCC header file - * @version V1.3.4 - * @date 11. October 2023 - ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(A) Compiler GCC Header File + */ + #ifndef __CMSIS_GCC_A_H #define __CMSIS_GCC_A_H @@ -120,6 +118,7 @@ */ #define __NOP() __ASM volatile ("nop") + /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. @@ -294,6 +293,7 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) return __builtin_clz(value); } + /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. @@ -623,7 +623,8 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) /* ################### Compiler specific Intrinsics ########################### */ -#if (__ARM_FEATURE_DSP == 1) +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __builtin_arm_sadd8 #define __QADD8 __builtin_arm_qadd8 #define __SHADD8 __builtin_arm_shadd8 diff --git a/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h b/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h index e8bed5281..3ddd0ba79 100644 --- a/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h +++ b/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h @@ -1,30 +1,25 @@ -/**************************************************************************//** - * @file cmsis_iccarm_a.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.8 - * @date 13. November 2022 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2018 IAR Systems -// Copyright (c) 2018-2019 Arm Limited -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ +/* + * Copyright (c) 2017-2018 IAR Systems + * Copyright (c) 2018-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * CMSIS-Core(A) Compiler ICCARM (IAR Compiler for Arm) Header File + */ #ifndef __CMSIS_ICCARM_A_H__ #define __CMSIS_ICCARM_A_H__ @@ -185,16 +180,6 @@ #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) #endif -#if 0 -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma language=save - #pragma language=extended - __packed struct __iar_u32 { uint32_t v; }; - #pragma language=restore - #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif -#endif - #ifndef __USED #if __ICCARM_V8 #define __USED __attribute__((used)) diff --git a/CMSIS/Core/Include/a-profile/irq_ctrl.h b/CMSIS/Core/Include/a-profile/irq_ctrl.h index 64ffb9723..7264fb936 100644 --- a/CMSIS/Core/Include/a-profile/irq_ctrl.h +++ b/CMSIS/Core/Include/a-profile/irq_ctrl.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file irq_ctrl.h - * @brief Interrupt Controller API header file - * @version V1.1.0 - * @date 03. March 2020 - ******************************************************************************/ /* * Copyright (c) 2017-2020 ARM Limited. All rights reserved. * @@ -22,13 +16,17 @@ * limitations under the License. */ +/* + * CMSIS-Core(A) Interrupt Controller API Header File + */ + #ifndef IRQ_CTRL_H_ #define IRQ_CTRL_H_ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ #endif #include diff --git a/CMSIS/Core/Include/cmsis_compiler.h b/CMSIS/Core/Include/cmsis_compiler.h index 42adf8011..173cd9035 100644 --- a/CMSIS/Core/Include/cmsis_compiler.h +++ b/CMSIS/Core/Include/cmsis_compiler.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V6.0.0 - * @date 23. November 2023 - ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS Compiler Generic Header File + */ + #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H @@ -137,10 +135,6 @@ #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) @@ -214,10 +208,6 @@ #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) @@ -290,10 +280,6 @@ #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) diff --git a/CMSIS/Core/Include/cmsis_version.h b/CMSIS/Core/Include/cmsis_version.h index 13f7a2037..bdb65ddb4 100644 --- a/CMSIS/Core/Include/cmsis_version.h +++ b/CMSIS/Core/Include/cmsis_version.h @@ -17,7 +17,7 @@ */ /* - * CMSIS Core Version definitions + * CMSIS Core Version Definitions */ #if defined ( __ICCARM__ ) diff --git a/CMSIS/Core/Include/core_ca.h b/CMSIS/Core/Include/core_ca.h index d6cb6b94c..9f73df666 100644 --- a/CMSIS/Core/Include/core_ca.h +++ b/CMSIS/Core/Include/core_ca.h @@ -1334,16 +1334,6 @@ __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { } } -/** \brief Clean and Invalidate the entire data or unified cache -* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency -* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean -* \deprecated Use generic L1C_CleanInvalidateCache instead. -*/ -CMSIS_DEPRECATED -__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { - L1C_CleanInvalidateCache(op); -} - /** \brief Invalidate the whole data cache. */ __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { @@ -1476,7 +1466,7 @@ __STATIC_INLINE void L2C_CleanInvPa (void *pa) /* ########################## GIC functions ###################################### */ #if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \ defined(DOXYGEN) - + /** \brief Enable the interrupt distributor using the GIC's CTLR register. */ __STATIC_INLINE void GIC_EnableDistributor(void) @@ -1863,7 +1853,7 @@ __STATIC_INLINE void GIC_Enable(void) /* ########################## Generic Timer functions ############################ */ #if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ defined(DOXYGEN) - + /* PL1 Physical Timer */ #if (__CORTEX_A == 7U) || defined(DOXYGEN) diff --git a/CMSIS/Core/Include/core_cm7.h b/CMSIS/Core/Include/core_cm7.h index a7ecf1657..bb36b787e 100644 --- a/CMSIS/Core/Include/core_cm7.h +++ b/CMSIS/Core/Include/core_cm7.h @@ -884,9 +884,6 @@ typedef struct #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ -#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ - #define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ #define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ diff --git a/CMSIS/Core/Include/core_sc300.h b/CMSIS/Core/Include/core_sc300.h index fcc6390f9..ab17573e0 100644 --- a/CMSIS/Core/Include/core_sc300.h +++ b/CMSIS/Core/Include/core_sc300.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V6.0.0 - * @date 16. October 2023 - ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS SC300 Core Peripheral Access Layer Header File + */ + #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) diff --git a/CMSIS/Core/Include/core_starmc1.h b/CMSIS/Core/Include/core_starmc1.h index b8650a158..b79e3f292 100644 --- a/CMSIS/Core/Include/core_starmc1.h +++ b/CMSIS/Core/Include/core_starmc1.h @@ -581,9 +581,9 @@ typedef struct typedef struct { - __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ - __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ } EMSS_Type; /** \brief SCB CPUID Register Definitions */ diff --git a/CMSIS/Core/Include/m-profile/armv7m_cachel1.h b/CMSIS/Core/Include/m-profile/armv7m_cachel1.h index 25e273d81..d7338a72e 100644 --- a/CMSIS/Core/Include/m-profile/armv7m_cachel1.h +++ b/CMSIS/Core/Include/m-profile/armv7m_cachel1.h @@ -1,9 +1,3 @@ -/****************************************************************************** - * @file armv7m_cachel1.h - * @brief CMSIS Level 1 Cache API for Armv7-M and later - * @version V1.0.3 - * @date 17. March 2023 - ******************************************************************************/ /* * Copyright (c) 2020-2021 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later + */ + #ifndef ARM_ARMV7M_CACHEL1_H #define ARM_ARMV7M_CACHEL1_H diff --git a/CMSIS/Core/Include/m-profile/armv7m_mpu.h b/CMSIS/Core/Include/m-profile/armv7m_mpu.h index 4237cee0d..5a4eba231 100644 --- a/CMSIS/Core/Include/m-profile/armv7m_mpu.h +++ b/CMSIS/Core/Include/m-profile/armv7m_mpu.h @@ -1,9 +1,3 @@ -/****************************************************************************** - * @file armv7m_mpu.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.1.2 - * @date 25. May 2020 - ******************************************************************************/ /* * Copyright (c) 2017-2020 Arm Limited. All rights reserved. * @@ -21,7 +15,11 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + +/* + * CMSIS-Core(M) MPU API for Armv7-M MPU + */ + #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H @@ -30,7 +28,7 @@ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif - + #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes @@ -79,12 +77,12 @@ /** * MPU Memory Access Attributes -* +* * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ +*/ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ @@ -93,7 +91,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. @@ -110,7 +108,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. @@ -119,7 +117,7 @@ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. -*/ +*/ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) @@ -129,7 +127,7 @@ * - Shareable * - Non-cacheable * - Non-bufferable -*/ +*/ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) /** @@ -140,7 +138,7 @@ * - Bufferable (if shareable) or non-bufferable (if non-shareable) * * \param IsShareable Configures the device memory as shareable or non-shareable. -*/ +*/ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) /** @@ -153,7 +151,7 @@ * \param OuterCp Configures the outer cache policy. * \param InnerCp Configures the inner cache policy. * \param IsShareable Configures the memory as shareable or non-shareable. -*/ +*/ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) /** @@ -184,7 +182,7 @@ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -224,7 +222,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rasr Value for RASR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; @@ -235,7 +233,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rasr Value for RASR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; @@ -251,7 +249,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -261,7 +259,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { diff --git a/CMSIS/Core/Include/m-profile/armv81m_pac.h b/CMSIS/Core/Include/m-profile/armv81m_pac.h index 6a285ff5e..648cf8864 100644 --- a/CMSIS/Core/Include/m-profile/armv81m_pac.h +++ b/CMSIS/Core/Include/m-profile/armv81m_pac.h @@ -1,9 +1,3 @@ -/****************************************************************************** - * @file armv81m_pac.h - * @brief CMSIS PAC key functions for Armv8.1-M PAC extension - * @version V1.0.0 - * @date 23. March 2022 - ******************************************************************************/ /* * Copyright (c) 2022 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension + */ + #ifndef PAC_ARMV81_H #define PAC_ARMV81_H diff --git a/CMSIS/Core/Include/m-profile/armv8m_mpu.h b/CMSIS/Core/Include/m-profile/armv8m_mpu.h index fdf4c03c4..d743af12c 100644 --- a/CMSIS/Core/Include/m-profile/armv8m_mpu.h +++ b/CMSIS/Core/Include/m-profile/armv8m_mpu.h @@ -1,9 +1,3 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.9.0 - * @date 11. April 2023 - ******************************************************************************/ /* * Copyright (c) 2017-2022 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + #ifndef ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H @@ -95,7 +93,7 @@ #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) /* \brief Specifies MAIR_ATTR number */ -#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) /** * Shareability @@ -164,7 +162,7 @@ (MPU_RLAR_EN_Msk)) #if defined(MPU_RLAR_PXN_Pos) - + /** \brief Region Limit Address Register with PXN value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. @@ -175,7 +173,7 @@ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) - + #endif /** @@ -194,7 +192,7 @@ __STATIC_INLINE uint32_t ARM_MPU_TYPE() { return ((MPU->TYPE) >> 8); } - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -261,11 +259,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; - + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } - + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } @@ -312,7 +310,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ +{ ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif @@ -322,7 +320,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; @@ -334,7 +332,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); @@ -345,10 +343,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif @@ -360,7 +358,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -372,7 +370,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { @@ -381,7 +379,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - + mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; @@ -392,7 +390,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } - + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } @@ -402,7 +400,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } @@ -413,7 +411,7 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } diff --git a/CMSIS/Core/Include/m-profile/armv8m_pmu.h b/CMSIS/Core/Include/m-profile/armv8m_pmu.h index 8e5ff876a..fb1653317 100644 --- a/CMSIS/Core/Include/m-profile/armv8m_pmu.h +++ b/CMSIS/Core/Include/m-profile/armv8m_pmu.h @@ -1,9 +1,3 @@ -/****************************************************************************** - * @file pmu_armv8.h - * @brief CMSIS PMU API for Armv8.1-M PMU - * @version V1.0.1 - * @date 15. April 2020 - ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(M) PMU API for Armv8.1-M PMU + */ + #ifndef ARM_PMU_ARMV8_H #define ARM_PMU_ARMV8_H @@ -192,23 +190,23 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); -/** +/** \brief Enable the PMU */ -__STATIC_INLINE void ARM_PMU_Enable(void) +__STATIC_INLINE void ARM_PMU_Enable(void) { PMU->CTRL |= PMU_CTRL_ENABLE_Msk; } -/** +/** \brief Disable the PMU */ -__STATIC_INLINE void ARM_PMU_Disable(void) +__STATIC_INLINE void ARM_PMU_Disable(void) { PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; } -/** +/** \brief Set event to count for PMU eventer counter \param [in] num Event counter (0-30) to configure \param [in] type Event to count @@ -218,7 +216,7 @@ __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) PMU->EVTYPER[num] = type; } -/** +/** \brief Reset cycle counter */ __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) @@ -226,7 +224,7 @@ __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; } -/** +/** \brief Reset all event counters */ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) @@ -234,8 +232,8 @@ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; } -/** - \brief Enable counters +/** + \brief Enable counters \param [in] mask Counters to enable \note Enables one or more of the following: - event counters (0-30) @@ -246,7 +244,7 @@ __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) PMU->CNTENSET = mask; } -/** +/** \brief Disable counters \param [in] mask Counters to enable \note Disables one or more of the following: @@ -258,7 +256,7 @@ __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) PMU->CNTENCLR = mask; } -/** +/** \brief Read cycle counter \return Cycle count */ @@ -267,7 +265,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) return PMU->CCNTR; } -/** +/** \brief Read event counter \param [in] num Event counter (0-30) to read \return Event count @@ -277,7 +275,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; } -/** +/** \brief Read counter overflow status \return Counter overflow status bits for the following: - event counters (0-30) @@ -285,10 +283,10 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) */ __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) { - return PMU->OVSSET; + return PMU->OVSSET; } -/** +/** \brief Clear counter overflow status \param [in] mask Counter overflow status bits to clear \note Clears overflow status bits for one or more of the following: @@ -300,8 +298,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) PMU->OVSCLR = mask; } -/** - \brief Enable counter overflow interrupt request +/** + \brief Enable counter overflow interrupt request \param [in] mask Counter overflow interrupt request bits to set \note Sets overflow interrupt request bits for one or more of the following: - event counters (0-30) @@ -312,8 +310,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) PMU->INTENSET = mask; } -/** - \brief Disable counter overflow interrupt request +/** + \brief Disable counter overflow interrupt request \param [in] mask Counter overflow interrupt request bits to clear \note Clears overflow interrupt request bits for one or more of the following: - event counters (0-30) @@ -324,8 +322,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) PMU->INTENCLR = mask; } -/** - \brief Software increment event counter +/** + \brief Software increment event counter \param [in] mask Counters to increment \note Software increment bits for one or more event counters (0-30) */ diff --git a/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h b/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h index 5550de1e3..47fb45284 100644 --- a/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h +++ b/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_armclang_m.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V6.0.0 - * @date 23. November 2023 - ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File + */ + #ifndef __CMSIS_ARMCLANG_M_H #define __CMSIS_ARMCLANG_M_H @@ -1158,7 +1156,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure PSPLIM is RAZ/WI */ return (0U); #else @@ -1205,7 +1203,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure PSPLIM is RAZ/WI */ (void)ProcStackPtrLimit; #else @@ -1248,7 +1246,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure MSPLIM is RAZ/WI */ return (0U); #else @@ -1295,7 +1293,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure MSPLIM is RAZ/WI */ (void)MainStackPtrLimit; #else diff --git a/CMSIS/Core/Include/m-profile/cmsis_clang_m.h b/CMSIS/Core/Include/m-profile/cmsis_clang_m.h index 1e3c6614c..97de89659 100644 --- a/CMSIS/Core/Include/m-profile/cmsis_clang_m.h +++ b/CMSIS/Core/Include/m-profile/cmsis_clang_m.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_clang_m.h - * @brief CMSIS compiler LLVM/Clang header file - * @version V1.1.0 - * @date 23. November 2023 - ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(M) Compiler LLVM/Clang Header File + */ + #ifndef __CMSIS_CLANG_M_H #define __CMSIS_CLANG_M_H @@ -1159,7 +1157,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure PSPLIM is RAZ/WI */ return (0U); #else @@ -1206,7 +1204,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure PSPLIM is RAZ/WI */ (void)ProcStackPtrLimit; #else @@ -1249,7 +1247,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure MSPLIM is RAZ/WI */ return (0U); #else @@ -1296,7 +1294,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure MSPLIM is RAZ/WI */ (void)MainStackPtrLimit; #else diff --git a/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h b/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h index 179fda7a7..ad4eb56fc 100644 --- a/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h +++ b/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_gcc_m.h - * @brief CMSIS compiler GCC header file - * @version V6.0.1 - * @date 23. November 2023 - ******************************************************************************/ /* * Copyright (c) 2009-2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(M) Compiler GCC Header File + */ + #ifndef __CMSIS_GCC_M_H #define __CMSIS_GCC_M_H @@ -1342,7 +1340,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure PSPLIM is RAZ/WI */ return (0U); #else @@ -1389,7 +1387,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure PSPLIM is RAZ/WI */ (void)ProcStackPtrLimit; #else @@ -1432,7 +1430,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure MSPLIM is RAZ/WI */ return (0U); #else @@ -1479,7 +1477,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure MSPLIM is RAZ/WI */ (void)MainStackPtrLimit; #else diff --git a/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h b/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h index 82f3b2378..f43f0a7b9 100644 --- a/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h +++ b/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h @@ -1,30 +1,25 @@ -/**************************************************************************//** - * @file cmsis_iccarm_m.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.4.0 - * @date 20. January 2023 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2021 IAR Systems -// Copyright (c) 2017-2023 Arm Limited. All rights reserved. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ +/* + * Copyright (c) 2017-2021 IAR Systems + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File + */ #ifndef __CMSIS_ICCARM_M_H__ #define __CMSIS_ICCARM_M_H__ diff --git a/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h b/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h index 9cfe44c72..1026e46ba 100644 --- a/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h +++ b/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h @@ -1,9 +1,3 @@ -/**************************************************************************//** - * @file cmsis_tiarmclang_m.h - * @brief CMSIS compiler tiarmclang header file - * @version V1.1.0 - * @date 23. November 2023 - ******************************************************************************/ /* * Copyright (c) 2023 Arm Limited. All rights reserved. * @@ -22,6 +16,10 @@ * limitations under the License. */ +/* + * CMSIS-Core(M) Compiler TIARMClang Header File + */ + #ifndef __CMSIS_TIARMCLANG_M_H #define __CMSIS_TIARMCLANG_M_H @@ -1158,7 +1156,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure PSPLIM is RAZ/WI */ return (0U); #else @@ -1205,7 +1203,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure PSPLIM is RAZ/WI */ (void)ProcStackPtrLimit; #else @@ -1248,7 +1246,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure MSPLIM is RAZ/WI */ return (0U); #else @@ -1295,7 +1293,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (((__ARM_ARCH_8M_MAIN__ < 1) && \ (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) + (__ARM_FEATURE_CMSE < 3) ) /* without main extensions, the non-secure MSPLIM is RAZ/WI */ (void)MainStackPtrLimit; #else