forked from Distrotech/memtest86
-
Notifications
You must be signed in to change notification settings - Fork 7
/
Copy pathinit.c
1335 lines (1199 loc) · 28.9 KB
/
init.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* MemeTest86+ V5 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, [email protected]
* http://www.canardpc.com - http://www.memetest.org
* ------------------------------------------------
* init.c - MemeTest-86 Version 3.6
*
* Released under version 2 of the Gnu Public License.
* By Chris Brady
*/
#include "stdin.h"
#include "stddef.h"
#include "test.h"
#include "defs.h"
#include "config.h"
#include "cpuid.h"
#include "smp.h"
#include "io.h"
#include "spd.h"
#include "pci.h"
#include "controller.h"
#include "playst2.h" // memetest
extern struct tseq tseq[];
extern short memsz_mode;
extern int num_cpus;
extern int act_cpus;
extern int found_cpus;
unsigned long imc_type = 0;
extern int maxcpus;
extern char cpu_mask[];
extern void initialise_cpus();
/* Here we store all of the cpuid data */
extern struct cpu_ident cpu_id;
int l1_cache=0, l2_cache=0, l3_cache=0;
int tsc_invariable = 0;
ulong extclock;
ulong memspeed(ulong src, ulong len, int iter);
static void cpu_type(void);
static int cpuspeed(void);
static void get_cache_size();
static void cpu_cache_speed();
void get_cpuid();
int beepmode;
extern short dmi_initialized;
extern int dmi_err_cnts[MAX_DMI_MEMDEVS];
/* Failsafe function */
/* msec: number of ms to wait - scs: scancode expected to stop */
/* bits: 0 = extended detection - 1: SMP - 2: Temp Check */
/* 3: MP SMP - 4-7: RSVD */
void failsafe(int msec, int scs)
{
int i;
ulong sh, sl, l, h, t;
unsigned char c;
volatile char *pp;
int music_forever;
unsigned int music_tick_count;
#if 0
// memetest: don't overwrite background
for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<40; i++, pp+=2) {
*pp = 0x1E;
}
for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<3; i++, pp+=2) {
*pp = 0x9E;
}
for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(55*2)+1); i<3; i++, pp+=2) {
*pp = 0x9E;
}
#endif
cprint(18, 18, "==> Press F1 to enter Fail-Safe Mode <==");
if(v->fail_safe & 2)
{
cprint(19, 15, "==> Press F2 to force Multi-Threading (SMP) <==");
}
cprint(20, 15, "==> Press F4 if you want the song name <==");
music_forever = 0;
// memetest: init music
music_init();
/* save the starting time */
asm __volatile__(
"rdtsc":"=a" (sl),"=d" (sh));
music_tick_count = 0;
/* loop for n seconds */
while (1) {
asm __volatile__(
"rdtsc":"=a" (l),"=d" (h));
asm __volatile__ (
"subl %2,%0\n\t"
"sbbl %3,%1"
:"=a" (l), "=d" (h)
:"g" (sl), "g" (sh),
"0" (l), "1" (h));
t = h * ((unsigned)0xffffffff / v->clks_msec);
t += (l / v->clks_msec);
unsigned int new_music_tick = t / MUSIC_MS_PER_TICK;
if (new_music_tick != music_tick_count) {
music_tick_count = new_music_tick;
music_tick();
}
/* Is the time up? */
if (t >= msec) { break; }
/* Is expected Scan code pressed? */
c = get_key();
c &= 0x7f;
/* F1 */
if(c == scs) { v->fail_safe |= 1; break; }
/* F2 */
if(c == scs+1)
{
v->fail_safe ^= 2;
break;
}
/* F3 */
if(c == scs+2)
{
if(v->fail_safe & 2) { v->fail_safe ^= 2; }
v->fail_safe |= 8;
break;
}
/* F4 */
if(c == scs + 3) { music_forever = 1; break;}
}
cprint(18, 18, " ");
cprint(19, 15, " ");
if (music_forever) {
cprint(20, 15, "AND DON'T SAY DARUDE SANDSTORM! (system_reset to exit)");
cprint(21, 15, "(song tracked by YouTube user Ober-91 - thanks)");
music_play_forever();
} else {
cprint(20, 15, " ");
music_stop();
}
#if 0
// memetest: don't overwrite background
for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<40; i++, pp+=2) {
*pp = 0x17;
}
#endif
}
static void display_init(void)
{
int i;
volatile char *pp;
/* Set HW cursor out of screen boundaries */
__outb(0x0F, 0x03D4);
__outb(0xFF, 0x03D5);
__outb(0x0E, 0x03D4);
__outb(0xFF, 0x03D5);
serial_echo_init();
serial_echo_print("[LINE_SCROLL;24r"); /* Set scroll area row 7-23 */
serial_echo_print("[H[2J"); /* Clear Screen */
serial_echo_print("[37m[44m");
serial_echo_print("[0m");
serial_echo_print("[37m[44m");
/* Clear screen & set background to dank */
for(i=0, pp=(char *)(SCREEN_ADR); i<80*24; i++) {
*pp++ = ' ';
// memetest: don't clear background
//*pp++ = 0x17;
pp++;
}
/* Make the name background green */
for(i=0, pp=(char *)(SCREEN_ADR+1); i<TITLE_WIDTH; i++, pp+=2) {
*pp = 0x20;
}
cprint(0, 0, " Memetest86 5.01 ");
/* Set Blinking "+" */
for(i=0, pp=(char *)(SCREEN_ADR+1); i<2; i++, pp+=30) {
*pp = 0xA4;
}
cprint(0, 15, "+");
#if 0
// memetest: don't clear background
/* Do reverse video for the bottom display line */
for(i=0, pp=(char *)(SCREEN_ADR+1+(24 * 160)); i<80; i++, pp+=2) {
*pp = 0x71;
}
#endif
serial_echo_print("[0m");
}
/*
* Initialize test, setup screen and find out how much memory there is.
*/
void init(void)
{
int i;
outb(0x8, 0x3f2); /* Kill Floppy Motor */
/* Turn on cache */
set_cache(1);
/* Setup the display */
display_init();
cprint(5, 60, "| Time: 0:00:00");
cprint(1, COL_MID,"Pass %");
cprint(2, COL_MID,"Test %");
cprint(3, COL_MID,"Test #");
cprint(4, COL_MID,"Testing: ");
cprint(5, COL_MID,"Pattern: ");
cprint(1, 0, "CLK: (32b Mode)");
cprint(2, 0, "L1 Ca$h: Unknown ");
cprint(3, 0, "L2 Ca$h: Unknown ");
cprint(4, 0, "L3 Ca$h: None ");
cprint(5, 0, "Memory : ");
cprint(6, 0, "------------------------------------------------------------------------------");
cprint(7, 0, "Core#:");
cprint(8, 0, "State:");
cprint(9, 0, "Core$: Active / Total (Run: All) | Pass: 0 Errors: 0 ");
cprint(10, 0, "------------------------------------------------------------------------------");
/*
for(i=0, pp=(char *)(SCREEN_ADR+(5*160)+(53*2)+1); i<20; i++, pp+=2) {
*pp = 0x92;
}
for(i=0, pp=(char *)(SCREEN_ADR+0*160+1); i<80; i++, pp+=2) {
*pp = 0x47;
}
*/
cprint(7, 39, "| Chipset : Unknown");
cprint(8, 39, "| Memeory Type : Unown ");
for(i=0; i < 6; i++) {
cprint(i, COL_MID-2, "| ");
}
footer();
aprint(5, 10, v->test_pages);
v->pass = 0;
v->msg_line = 0;
v->ecount = 0;
v->ecc_ecount = 0;
v->testsel = -1;
v->msg_line = LINE_SCROLL-1;
v->scroll_start = v->msg_line * 160;
v->erri.low_addr.page = 0x7fffffff;
v->erri.low_addr.offset = 0xfff;
v->erri.high_addr.page = 0;
v->erri.high_addr.offset = 0;
v->erri.min_bits = 32;
v->erri.max_bits = 0;
v->erri.min_bits = 32;
v->erri.max_bits = 0;
v->erri.maxl = 0;
v->erri.cor_err = 0;
v->erri.ebits = 0;
v->erri.hdr_flag = 0;
v->erri.tbits = 0;
for (i=0; tseq[i].msg != NULL; i++) {
tseq[i].errors = 0;
}
if (dmi_initialized) {
for (i=0; i < MAX_DMI_MEMDEVS; i++){
if (dmi_err_cnts[i] > 0) {
dmi_err_cnts[i] = 0;
}
}
}
/* setup beep mode */
beepmode = BEEP_MODE;
/* Get the cpu and cache information */
get_cpuid();
/* setup pci */
pci_init();
get_cache_size();
cpu_type();
cpu_cache_speed();
/* Check fail safe */
failsafe(5000, 0x3B);
/* Initalize SMP */
initialise_cpus();
for (i = 0; i <num_cpus; i++) {
dprint(7, i+7, i%10, 1, 0);
cprint(8, i+7, "S");
}
dprint(9, 19, num_cpus, 2, 0);
if((v->fail_safe & 3) == 2)
{
cprint(LINE_CPU,9, "(SMP: Disabled)");
cprint(LINE_RAM,9, "Running...");
}
// dprint(10, 5, found_cpus, 2, 0);
/* Find Memory Specs */
if(v->fail_safe & 1)
{
cprint(LINE_CPU, COL_SPEC, " **** FAIL SAFE **** FAIL SAFE **** ");
cprint(LINE_RAM, COL_SPEC, " No detection, same reliability ");
} else {
find_controller();
get_spd_spec();
if(num_cpus <= 16 && !(v->fail_safe & 4)) { coretemp(); }
}
if(v->check_temp > 0 && !(v->fail_safe & 4))
{
cprint(LINE_CPU, 26, "| CPU Temp");
cprint(LINE_CPU+1, 26, "| øC");
}
beep(600);
beep(1000);
/* Record the start time */
asm __volatile__ ("rdtsc":"=a" (v->startl),"=d" (v->starth));
v->snapl = v->startl;
v->snaph = v->starth;
if (l1_cache == 0) { l1_cache = 64; }
if (l2_cache == 0) { l1_cache = 512; }
v->printmode=PRINTMODE_ADDRESSES;
v->numpatn=0;
}
/* Get cache sizes for most AMD and Intel CPUs, exceptions for old CPUs are
* handled in CPU detection */
void get_cache_size()
{
int i, j, n, size;
unsigned int v[4];
unsigned char *dp = (unsigned char *)v;
struct cpuid4_eax *eax = (struct cpuid4_eax *)&v[0];
struct cpuid4_ebx *ebx = (struct cpuid4_ebx *)&v[1];
struct cpuid4_ecx *ecx = (struct cpuid4_ecx *)&v[2];
switch(cpu_id.vend_id.char_array[0]) {
/* AMD Processors */
case 'A':
//l1_cache = cpu_id.cache_info.amd.l1_i_sz;
l1_cache = cpu_id.cache_info.amd.l1_d_sz;
l2_cache = cpu_id.cache_info.amd.l2_sz;
l3_cache = cpu_id.cache_info.amd.l3_sz;
l3_cache *= 512;
break;
case 'G':
/* Intel Processors */
l1_cache = 0;
l2_cache = 0;
l3_cache = 0;
/* Use CPUID(4) if it is available */
if (cpu_id.max_cpuid > 3) {
/* figure out how many cache leaves */
n = -1;
do
{
++n;
/* Do cpuid(4) loop to find out num_cache_leaves */
cpuid_count(4, n, &v[0], &v[1], &v[2], &v[3]);
} while ((eax->ctype) != 0);
/* loop through all of the leaves */
for (i=0; i<n; i++)
{
cpuid_count(4, i, &v[0], &v[1], &v[2], &v[3]);
/* Check for a valid cache type */
if (eax->ctype == 1 || eax->ctype == 3)
{
/* Compute the cache size */
size = (ecx->number_of_sets + 1) *
(ebx->coherency_line_size + 1) *
(ebx->physical_line_partition + 1) *
(ebx->ways_of_associativity + 1);
size /= 1024;
switch (eax->level)
{
case 1:
l1_cache += size;
break;
case 2:
l2_cache += size;
break;
case 3:
l3_cache += size;
break;
}
}
}
return;
}
/* No CPUID(4) so we use the older CPUID(2) method */
/* Get number of times to iterate */
cpuid(2, &v[0], &v[1], &v[2], &v[3]);
n = v[0] & 0xff;
for (i=0 ; i<n ; i++) {
cpuid(2, &v[0], &v[1], &v[2], &v[3]);
/* If bit 31 is set, this is an unknown format */
for (j=0 ; j<3 ; j++) {
if (v[j] & (1 << 31)) {
v[j] = 0;
}
}
/* Byte 0 is level count, not a descriptor */
for (j = 1 ; j < 16 ; j++) {
switch(dp[j]) {
case 0x6:
case 0xa:
case 0x66:
l1_cache += 8;
break;
case 0x8:
case 0xc:
case 0xd:
case 0x60:
case 0x67:
l1_cache += 16;
break;
case 0xe:
l1_cache += 24;
break;
case 0x9:
case 0x2c:
case 0x30:
case 0x68:
l1_cache += 32;
break;
case 0x39:
case 0x3b:
case 0x41:
case 0x79:
l2_cache += 128;
break;
case 0x3a:
l2_cache += 192;
break;
case 0x21:
case 0x3c:
case 0x3f:
case 0x42:
case 0x7a:
case 0x82:
l2_cache += 256;
break;
case 0x3d:
l2_cache += 384;
break;
case 0x3e:
case 0x43:
case 0x7b:
case 0x7f:
case 0x80:
case 0x83:
case 0x86:
l2_cache += 512;
break;
case 0x44:
case 0x78:
case 0x7c:
case 0x84:
case 0x87:
l2_cache += 1024;
break;
case 0x45:
case 0x7d:
case 0x85:
l2_cache += 2048;
break;
case 0x48:
l2_cache += 3072;
break;
case 0x4e:
l2_cache += 6144;
break;
case 0x23:
case 0xd0:
l3_cache += 512;
break;
case 0xd1:
case 0xd6:
l3_cache += 1024;
break;
case 0x25:
case 0xd2:
case 0xd7:
case 0xdc:
case 0xe2:
l3_cache += 2048;
break;
case 0x29:
case 0x46:
case 0x49:
case 0xd8:
case 0xdd:
case 0xe3:
l3_cache += 4096;
break;
case 0x4a:
l3_cache += 6144;
break;
case 0x47:
case 0x4b:
case 0xde:
case 0xe4:
l3_cache += 8192;
break;
case 0x4c:
case 0xea:
l3_cache += 12288;
break;
case 0x4d:
l3_cache += 16384;
break;
case 0xeb:
l3_cache += 18432;
break;
case 0xec:
l3_cache += 24576;
break;
} /* end switch */
} /* end for 1-16 */
} /* end for 0 - n */
}
}
/*
* Find IMC type and set global variables accordingly
*/
void detect_imc(void)
{
// Check AMD IMC
if(cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.family == 0xF)
{
switch(cpu_id.vers.bits.extendedFamily)
{
case 0x0:
imc_type = 0x0100; // Old K8
break;
case 0x1:
case 0x2:
imc_type = 0x0101; // K10 (Family 10h & 11h)
break;
case 0x3:
imc_type = 0x0102; // A-Series APU (Family 12h)
break;
case 0x5:
imc_type = 0x0103; // C- / E- / Z- Series APU (Family 14h)
break;
case 0x6:
imc_type = 0x0104; // FX Series (Family 15h)
break;
case 0x7:
imc_type = 0x0105; // Kabini & related (Family 16h)
break;
}
return;
}
// Check Intel IMC
if(cpu_id.vend_id.char_array[0] == 'G' && cpu_id.vers.bits.family == 6 && cpu_id.vers.bits.extendedModel)
{
switch(cpu_id.vers.bits.model)
{
case 0x5:
if(cpu_id.vers.bits.extendedModel == 2) { imc_type = 0x0003; } // Core i3/i5 1st Gen 45 nm (NHM)
if(cpu_id.vers.bits.extendedModel == 3) { v->fail_safe |= 4; } // Atom Clover Trail
if(cpu_id.vers.bits.extendedModel == 4) { imc_type = 0x0007; } // HSW-ULT
break;
case 0x6:
if(cpu_id.vers.bits.extendedModel == 3) {
imc_type = 0x0009; // Atom Cedar Trail
v->fail_safe |= 4; // Disable Core temp
}
break;
case 0xA:
switch(cpu_id.vers.bits.extendedModel)
{
case 0x1:
imc_type = 0x0001; // Core i7 1st Gen 45 nm (NHME)
break;
case 0x2:
imc_type = 0x0004; // Core 2nd Gen (SNB)
break;
case 0x3:
imc_type = 0x0006; // Core 3nd Gen (IVB)
break;
}
break;
case 0xC:
switch(cpu_id.vers.bits.extendedModel)
{
case 0x1:
if(cpu_id.vers.bits.stepping > 9) { imc_type = 0x0008; } // Atom PineView
v->fail_safe |= 4; // Disable Core temp
break;
case 0x2:
imc_type = 0x0002; // Core i7 1st Gen 32 nm (WMR)
break;
case 0x3:
imc_type = 0x0007; // Core 4nd Gen (HSW)
break;
}
break;
case 0xD:
imc_type = 0x0005; // SNB-E
break;
case 0xE:
imc_type = 0x0001; // Core i7 1st Gen 45 nm (NHM)
break;
}
if(imc_type) { tsc_invariable = 1; }
return;
}
}
void smp_default_mode(void)
{
int i, result;
char *cpupsn = cpu_id.brand_id.char_array;
char *disabledcpu[] = { "Opteron", "Xeon", "Genuine Intel" };
for(i = 0; i < 3; i++)
{
result = strstr(cpupsn , disabledcpu[i]);
if(result != -1) { v->fail_safe |= 0b10; }
}
// For 5.01 release, SMP disabled by defualt by config.h toggle
if(CONSERVATIVE_SMP) { v->fail_safe |= 0b10; }
}
/*
* Find CPU type
*/
void cpu_type(void)
{
/* If we can get a brand string use it, and we are done */
if (cpu_id.max_xcpuid >= 0x80000004) {
cprint(0, COL_MID, cpu_id.brand_id.char_array);
//If we have a brand string, maybe we have an IMC. Check that.
detect_imc();
smp_default_mode();
return;
}
/* The brand string is not available so we need to figure out
* CPU what we have */
switch(cpu_id.vend_id.char_array[0]) {
/* AMD Processors */
case 'A':
switch(cpu_id.vers.bits.family) {
case 4:
switch(cpu_id.vers.bits.model) {
case 3:
cprint(0, COL_MID, "AMD 486DX2");
break;
case 7:
cprint(0, COL_MID, "AMD 486DX2-WB");
break;
case 8:
cprint(0, COL_MID, "AMD 486DX4");
break;
case 9:
cprint(0, COL_MID, "AMD 486DX4-WB");
break;
case 14:
cprint(0, COL_MID, "AMD 5x86-WT");
break;
case 15:
cprint(0, COL_MID, "AMD 5x86-WB");
break;
}
/* Since we can't get CPU speed or cache info return */
return;
case 5:
switch(cpu_id.vers.bits.model) {
case 0:
case 1:
case 2:
case 3:
cprint(0, COL_MID, "AMD K5");
l1_cache = 8;
break;
case 6:
case 7:
cprint(0, COL_MID, "AMD K6");
break;
case 8:
cprint(0, COL_MID, "AMD K6-2");
break;
case 9:
cprint(0, COL_MID, "AMD K6-III");
break;
case 13:
cprint(0, COL_MID, "AMD K6-III+");
break;
}
break;
case 6:
switch(cpu_id.vers.bits.model) {
case 1:
cprint(0, COL_MID, "AMD Athlon (0.25)");
break;
case 2:
case 4:
cprint(0, COL_MID, "AMD Athlon (0.18)");
break;
case 6:
if (l2_cache == 64) {
cprint(0, COL_MID, "AMD Duron (0.18)");
} else {
cprint(0, COL_MID, "Athlon XP (0.18)");
}
break;
case 8:
case 10:
if (l2_cache == 64) {
cprint(0, COL_MID, "AMD Duron (0.13)");
} else {
cprint(0, COL_MID, "Athlon XP (0.13)");
}
break;
case 3:
case 7:
cprint(0, COL_MID, "AMD Duron");
/* Duron stepping 0 CPUID for L2 is broken */
/* (AMD errata T13)*/
if (cpu_id.vers.bits.stepping == 0) { /* stepping 0 */
/* Hard code the right L2 size */
l2_cache = 64;
} else {
}
break;
}
break;
/* All AMD family values >= 10 have the Brand ID
* feature so we don't need to find the CPU type */
}
break;
/* Intel or Transmeta Processors */
case 'G':
if ( cpu_id.vend_id.char_array[7] == 'T' ) { /* GenuineTMx86 */
if (cpu_id.vers.bits.family == 5) {
cprint(0, COL_MID, "TM 5x00");
} else if (cpu_id.vers.bits.family == 15) {
cprint(0, COL_MID, "TM 8x00");
}
l1_cache = cpu_id.cache_info.ch[3] + cpu_id.cache_info.ch[7];
l2_cache = (cpu_id.cache_info.ch[11]*256) + cpu_id.cache_info.ch[10];
} else { /* GenuineIntel */
if (cpu_id.vers.bits.family == 4) {
switch(cpu_id.vers.bits.model) {
case 0:
case 1:
cprint(0, COL_MID, "Intel 486DX");
break;
case 2:
cprint(0, COL_MID, "Intel 486SX");
break;
case 3:
cprint(0, COL_MID, "Intel 486DX2");
break;
case 4:
cprint(0, COL_MID, "Intel 486SL");
break;
case 5:
cprint(0, COL_MID, "Intel 486SX2");
break;
case 7:
cprint(0, COL_MID, "Intel 486DX2-WB");
break;
case 8:
cprint(0, COL_MID, "Intel 486DX4");
break;
case 9:
cprint(0, COL_MID, "Intel 486DX4-WB");
break;
}
/* Since we can't get CPU speed or cache info return */
return;
}
switch(cpu_id.vers.bits.family) {
case 5:
switch(cpu_id.vers.bits.model) {
case 0:
case 1:
case 2:
case 3:
case 7:
cprint(0, COL_MID, "Pentium");
if (l1_cache == 0) {
l1_cache = 8;
}
break;
case 4:
case 8:
cprint(0, COL_MID, "Pentium-MMX");
if (l1_cache == 0) {
l1_cache = 16;
}
break;
}
break;
case 6:
switch(cpu_id.vers.bits.model) {
case 0:
case 1:
cprint(0, COL_MID, "Pentium Pro");
break;
case 3:
case 4:
cprint(0, COL_MID, "Pentium II");
break;
case 5:
if (l2_cache == 0) {
cprint(0, COL_MID, "Celeron");
} else {
cprint(0, COL_MID, "Pentium II");
}
break;
case 6:
if (l2_cache == 128) {
cprint(0, COL_MID, "Celeron");
} else {
cprint(0, COL_MID, "Pentium II");
}
}
break;
case 7:
case 8:
case 11:
if (l2_cache == 128) {
cprint(0, COL_MID, "Celeron");
} else {
cprint(0, COL_MID, "Pentium III");
}
break;
case 9:
if (l2_cache == 512) {
cprint(0, COL_MID, "Celeron M (0.13)");
} else {
cprint(0, COL_MID, "Pentium M (0.13)");
}
break;
case 10:
cprint(0, COL_MID, "Pentium III Xeon");
break;
case 12:
l1_cache = 24;
cprint(0, COL_MID, "Atom (0.045)");
break;
case 13:
if (l2_cache == 1024) {
cprint(0, COL_MID, "Celeron M (0.09)");
} else {
cprint(0, COL_MID, "Pentium M (0.09)");
}
break;
case 14:
cprint(0, COL_MID, "Intel Core");
break;
case 15:
if (l2_cache == 1024) {
cprint(0, COL_MID, "Pentium E");
} else {
cprint(0, COL_MID, "Intel Core 2");
}
break;
}
break;
case 15:
switch(cpu_id.vers.bits.model) {
case 0:
case 1:
case 2:
if (l2_cache == 128) {
cprint(0, COL_MID, "Celeron");
} else {
cprint(0, COL_MID, "Pentium 4");
}
break;
case 3:
case 4:
if (l2_cache == 256) {
cprint(0, COL_MID, "Celeron (0.09)");
} else {
cprint(0, COL_MID, "Pentium 4 (0.09)");
}
break;
case 6:
cprint(0, COL_MID, "Pentium D (65nm)");
break;
default:
cprint(0, COL_MID, "Unknown Intel");
break;
break;
}
}
break;
/* VIA/Cyrix/Centaur Processors with CPUID */
case 'C':
if ( cpu_id.vend_id.char_array[1] == 'e' ) { /* CentaurHauls */
l1_cache = cpu_id.cache_info.ch[3] + cpu_id.cache_info.ch[7];
l2_cache = cpu_id.cache_info.ch[11];
switch(cpu_id.vers.bits.family){
case 5:
cprint(0, COL_MID, "Centaur 5x86");
break;
case 6: // VIA C3
switch(cpu_id.vers.bits.model){
default:
if (cpu_id.vers.bits.stepping < 8) {
cprint(0, COL_MID, "VIA C3 Samuel2");
} else {
cprint(0, COL_MID, "VIA C3 Eden");
}
break;
case 10:
cprint(0, COL_MID, "VIA C7 (C5J)");
l1_cache = 64;
l2_cache = 128;
break;
case 13:
cprint(0, COL_MID, "VIA C7 (C5R)");
l1_cache = 64;
l2_cache = 128;
break;
case 15:
cprint(0, COL_MID, "VIA Isaiah (CN)");
l1_cache = 64;
l2_cache = 128;
break;
}
}
} else { /* CyrixInstead */
switch(cpu_id.vers.bits.family) {
case 5:
switch(cpu_id.vers.bits.model) {
case 0:
cprint(0, COL_MID, "Cyrix 6x86MX/MII");
break;
case 4:
cprint(0, COL_MID, "Cyrix GXm");