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Build the VexRISCV verilog as part of the module generation run #4

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mithro opened this issue Nov 5, 2020 · 1 comment

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mithro commented Nov 5, 2020

Currently the generation of VexRISCV verilog is done manually.

It would be nice if the pythondata-auto tool would checkout the VexRISCV module and run the generation of the Verilog output (and commit that).

mithro mentioned this issue

Building a vexriscv_smp variant SoC standalone? enjoy-digital/litex#687

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mithro commented Nov 5, 2020

It would be good if the module.ini file could specify a generation command that is run as part of generating the module.

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