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https://alive2.llvm.org/ce/z/k4SnKK
define i32 @src(i32 %x, i32 range(i32 0, 32) %y) { %res = call i32 @llvm.fshl(i32 %x, i32 0, i32 %y) ret i32 %res } define i32 @tgt(i32 %x, i32 range(i32 0, 32) %y) { %res = shl i32 %x, %y ret i32 %res }
We currently only do this if the shift amount is constant, but not for a dynamic shift amount that is < bitwidth based on known bits.
The text was updated successfully, but these errors were encountered:
@dtcxzyw suggested masking the shift amount as an alternative:
https://alive2.llvm.org/ce/z/3oTEop
define i32 @src(i32 %x, i32 %y) { %res = call i32 @llvm.fshl.i32(i32 %x, i32 0, i32 %y) ret i32 %res } define i32 @tgt(i32 %x, i32 %y) { %rem = and i32 %y, 31 %res = shl i32 %x, %rem ret i32 %res }
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Interested, I can work on this
AmrDeveloper
Successfully merging a pull request may close this issue.
https://alive2.llvm.org/ce/z/k4SnKK
We currently only do this if the shift amount is constant, but not for a dynamic shift amount that is < bitwidth based on known bits.
The text was updated successfully, but these errors were encountered: