From 4f557823ae691155282759d4b2900d53954fd98b Mon Sep 17 00:00:00 2001 From: Martin Velay Date: Thu, 16 Jan 2025 10:24:06 +0000 Subject: [PATCH] [hmac,dv] Disable S&R for stress_reset test - The stress_reset test is currently failing when a reset is happening when the Save and Restore is in a particular state. This should be removed later when the reset will be handled properly in the env. Signed-off-by: Martin Velay --- hw/ip/hmac/dv/env/seq_lib/hmac_stress_reset_vseq.sv | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_reset_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_reset_vseq.sv index bf873cc5d325e..3f50f2aba401c 100644 --- a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_reset_vseq.sv +++ b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_reset_vseq.sv @@ -9,6 +9,7 @@ class hmac_stress_reset_vseq extends hmac_base_vseq; // Standard SV/UVM methods extern function new(string name=""); + extern task pre_body(); extern task body(); endclass : hmac_stress_reset_vseq @@ -17,6 +18,12 @@ function hmac_stress_reset_vseq::new(string name=""); super.new(name); endfunction : new +task hmac_stress_reset_vseq::pre_body(); + // TODO (#25809) - The S&R is causing troubles with this test, this flag will be removed later + // when reset is handled properly. + cfg.save_and_restore_pct = 0; + super.pre_body(); +endtask : pre_body task hmac_stress_reset_vseq::body(); for (int i = 1; i <= num_trans; i++) begin