You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
As you mentioned in my previous issue there are indeed three clocks but it seems that they are limited inside of a site as their ROUTE_STATUS is INTRASITE and I cant connect them to the extra circuit. For example pll_clk1:
I explored the netlist schematic and found past the IBUF and the BUFGCTRL, a clock net that is being used by other parts of the circuit:
So is the crypt_clk an appropriate input clock for my extra circuit since this one seems to be used by other parts of the design as well? I dont see any other that i am able to route to my circuit.
The text was updated successfully, but these errors were encountered:
As you mentioned in my previous issue there are indeed three clocks but it seems that they are limited inside of a site as their ROUTE_STATUS is INTRASITE and I cant connect them to the extra circuit. For example pll_clk1:
I explored the netlist schematic and found past the IBUF and the BUFGCTRL, a clock net that is being used by other parts of the circuit:
So is the crypt_clk an appropriate input clock for my extra circuit since this one seems to be used by other parts of the design as well? I dont see any other that i am able to route to my circuit.
The text was updated successfully, but these errors were encountered: