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0002-v4.1.0.5-x310-add-twstft-amaranth.patch
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From b204f371151d071a7211eee784d6877ed3d8253f Mon Sep 17 00:00:00 2001
From: Gwenhael Goavec-Merou <[email protected]>
Date: Mon, 12 Sep 2022 18:50:29 +0200
Subject: [PATCH] adding a patch for UHD to integrate twstft into X310
firmware
Signed-off-by: Gwenhael Goavec-Merou <[email protected]>
---
fpga/usrp3/top/x300/Makefile | 15 ++++++
fpga/usrp3/top/x300/Makefile.x300.inc | 1 +
fpga/usrp3/top/x300/x300.v | 76 +++++++++++++++++++++++++--
fpga/usrp3/top/x300/x300.xdc | 12 ++---
4 files changed, 95 insertions(+), 9 deletions(-)
diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile
index 2f5e1b924..42b91aa3a 100644
--- a/fpga/usrp3/top/x300/Makefile
+++ b/fpga/usrp3/top/x300/Makefile
@@ -64,6 +64,20 @@ else
post_build = @echo "Skipping bitfile export."
endif
+# 0: syrte
+# 3: besac
+TAPS?=0
+NOISELEN?=2500000
+BITLEN?=22
+INVERT_FIRST_CODE?=0
+
+AMARANTH_OPTS = -v --taps $(TAPS) --noiselen $(NOISELEN) --bitlen $(BITLEN)
+
+ifeq ($(INVERT_FIRST_CODE),1)
+AMARANTH_OPTS += --invert-first-code
+endif
+
+
##
##Supported Targets
##-----------------
@@ -82,6 +96,7 @@ X300_1G:
##X310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
X310_HG:
+ python -m amaranth_twstft.flashZedBoard --no-load --no-build --build-dir amaranth $(AMARANTH_OPTS)
$(call vivado_build,X310,$(HG_DEFS) X310=1)
$(call post_build,X310,HG)
diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc
index 1f18cbf02..2ff6c86d9 100644
--- a/fpga/usrp3/top/x300/Makefile.x300.inc
+++ b/fpga/usrp3/top/x300/Makefile.x300.inc
@@ -63,6 +63,7 @@ x300_core.v \
x300_sfpp_io_core.v \
x300_zpu_config.vhd \
x300_eth_interface.v \
+amaranth/top.v \
nirio_chdr64_adapter.v \
soft_ctrl.v \
capture_ddrlvds.v \
diff --git a/fpga/usrp3/top/x300/x300.v b/fpga/usrp3/top/x300/x300.v
index 8fbfa39b9..ddbc9491c 100644
--- a/fpga/usrp3/top/x300/x300.v
+++ b/fpga/usrp3/top/x300/x300.v
@@ -168,7 +168,15 @@ module x300
//
///////////////////////////////////
- inout [11:0] FrontPanelGpio,
+ //GGM
+ //inout [11:0] FrontPanelGpio,
+ inout [5:0] FrontPanelGpio,
+ output FrontPanelGpio6, // invert prn o
+ input FrontPanelGpio7, // OUT carrier
+ output FrontPanelGpio8, // PPS
+ input FrontPanelGpio9, // ENABLE
+ output FrontPanelGpio10, // OUTPUT
+ output FrontPanelGpio11, // PPS out2
output LED_ACT1, output LED_ACT2,
output LED_LINK1, output LED_LINK2,
@@ -383,6 +391,62 @@ module x300
.CLK_OUT1(radio_clk), .CLK_OUT2(radio_clk_2x), .CLK_OUT3(dac_dci_clk),
.RESET(sw_rst[2]), .LOCKED(radio_clk_locked));
+
+ /* amaranth begin */
+ wire amaranth_clk280, amaranth_clk280_int;
+ wire amaranth_rst;
+ wire amaranth_clkfb;
+
+ MMCME2_BASE #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT_F(7.0),
+ .CLKFBOUT_PHASE(0.0),
+ .CLKIN1_PERIOD(32'd5),
+ .CLKOUT0_DIVIDE_F(5.0),
+ .CLKOUT0_DUTY_CYCLE(0.5),
+ .CLKOUT0_PHASE(0.0)
+ ) mmcm (
+ .CLKFBIN(amaranth_clkfb),
+ .CLKFBOUT(amaranth_clkfb),
+ .CLKIN1(radio_clk),
+ .CLKOUT0(amaranth_clk280_int),
+ .LOCKED(amaranth_rst),
+ .PWRDWN(1'h0),
+ .RST(!radio_clk_locked)
+ );
+
+ // Output buffering
+ //-----------------------------------
+ BUFG amaranth_clk280_bufg
+ (.O (amaranth_clk280),
+ .I (amaranth_clk280_int));
+
+ /* FrontPanelGpio
+ * ++
+ * ||--- +
+ * |-----| 1'b0 0 x x 1 GLOB EN
+ * | SP6 | 1'b0 2 x x 3 OUTPUT
+ * | | 1'b0 4 x x 5 PPS_IN
+ * | | 1'b0 6 x x 7 SWITCH MODE
+ * | | GND 8 x x 9 GND
+ * +-----+
+ |--- *
+ *
+ */
+ mixer mixer (
+ .clk(amaranth_clk280),
+ .global_enable(FrontPanelGpio9),
+ .output_carrier(FrontPanelGpio7),
+ .mod_out(FrontPanelGpio10),
+ .pps_in(EXT_PPS_IN),
+ .pps_out(FrontPanelGpio8),
+ .the_pps_we_love(FrontPanelGpio11),
+ .rst(!amaranth_rst),
+ .invert_prn_o(FrontPanelGpio6),
+ .switch_mode(1'b0/*FrontPanelGpio11*/)
+ );
+
+ /* amaranth end */
////////////////////////////////////////////////////////////////////
//
// IJB. Radio PLL doesn't seem to lock at power up.
@@ -1304,7 +1368,13 @@ module x300
.gpio_ddr(db1_gpio_ddr), .gpio_out(db1_gpio_out), .gpio_in(db1_gpio_in)
);
-`ifdef DEBUG_UART
+
+ gpio_atr_io #(.WIDTH(6)) fp_gpio_atr_inst (
+ .clk(radio_clk), .gpio_pins(FrontPanelGpio[5:0]),
+ .gpio_ddr(fp_gpio_ddr[5:0]), .gpio_out(fp_gpio_out[5:0]), .gpio_in(fp_gpio_in[5:0])
+ );
+ assign fp_gpio_in[11:6] = 0;
+/*`ifdef DEBUG_UART
gpio_atr_io #(.WIDTH(10)) fp_gpio_atr_inst (
.clk(radio_clk), .gpio_pins(FrontPanelGpio[9:0]),
.gpio_ddr(fp_gpio_ddr[9:0]), .gpio_out(fp_gpio_out[9:0]), .gpio_in(fp_gpio_in[9:0])
@@ -1317,7 +1387,7 @@ module x300
.gpio_ddr(fp_gpio_ddr[11:0]), .gpio_out(fp_gpio_out[11:0]), .gpio_in(fp_gpio_in[11:0])
);
assign debug_rxd = 1'b0;
-`endif
+`endif */
assign fp_gpio_in[31:12] = 20'h0;
///////////////////////////////////////////////////////////////////////////////////
diff --git a/fpga/usrp3/top/x300/x300.xdc b/fpga/usrp3/top/x300/x300.xdc
index 11290b79f..946f563a7 100644
--- a/fpga/usrp3/top/x300/x300.xdc
+++ b/fpga/usrp3/top/x300/x300.xdc
@@ -510,12 +510,12 @@ set_property PACKAGE_PIN AD28 [get_ports {FrontPanelGpio[2]}]
set_property PACKAGE_PIN AG30 [get_ports {FrontPanelGpio[3]}]
set_property PACKAGE_PIN AH30 [get_ports {FrontPanelGpio[4]}]
set_property PACKAGE_PIN AC26 [get_ports {FrontPanelGpio[5]}]
-set_property PACKAGE_PIN AD26 [get_ports {FrontPanelGpio[6]}]
-set_property PACKAGE_PIN AJ27 [get_ports {FrontPanelGpio[7]}]
-set_property PACKAGE_PIN AK28 [get_ports {FrontPanelGpio[8]}]
-set_property PACKAGE_PIN AG27 [get_ports {FrontPanelGpio[9]}]
-set_property PACKAGE_PIN AG28 [get_ports {FrontPanelGpio[10]}]
-set_property PACKAGE_PIN AH26 [get_ports {FrontPanelGpio[11]}]
+set_property PACKAGE_PIN AD26 [get_ports {FrontPanelGpio6}]
+set_property PACKAGE_PIN AJ27 [get_ports {FrontPanelGpio7}]
+set_property PACKAGE_PIN AK28 [get_ports {FrontPanelGpio8}]
+set_property PACKAGE_PIN AG27 [get_ports {FrontPanelGpio9}]
+set_property PACKAGE_PIN AG28 [get_ports {FrontPanelGpio10}]
+set_property PACKAGE_PIN AH26 [get_ports {FrontPanelGpio11}]
set_property IOSTANDARD LVCMOS33 [get_ports {FrontPanelGpio*}]
set_property PULLDOWN TRUE [get_ports {FrontPanelGpio*}]
--
2.37.4