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Steven Herbst edited this page Aug 12, 2020 · 11 revisions

using part xc7z020clg400-1 (i.e., FPGA on the PYNQ_Z1 board)

  • Fixed-point:
    • ADD (input range 10, output 20)
      • WIDTH 25: 24 LUTs
      • WIDTH 24: 23 LUTs
      • WIDTH 26: LUTs
    • ADD_CONST
      • LONG=25, SHORT=18
    • MUL (input range 10, output 100)
      • A, B, C @ 25 bits:
      • A @ 25, B @ 18, C @ 25:
      • A @ 25, B @ 19, C @ 25:
      • A @ 25, B @ 22, C @ 25:
      • A @ 25, B @ 20, C @ 25:
      • A @ 26, B @ 18, C @ 25:
      • A @ 27, B @ 18, C @ 25:
    • MUL_CONST
      • LONG=25, SHORT=18
  • HardFloat:
    • ADD
      • EXP=8, WIDTH=24:
    • ADD_CONST
      • EXP=8, WIDTH=24
    • MUL
      • EXP=8, WIDTH=24: 313 LUTs, 3 DSPs
      • EXP=8, WIDTH=23: 187 LUTs, 2 DSPs
      • EXP=8, WIDTH=25: 348 LUTs, 3 DSPs
      • EXP=8, WIDTH=22: 177 LUTs, 2 DSPs
      • EXP=8, WIDTH=21: 168 LUTs, 2 DSPs
      • EXP=8, WIDTH=20: 238 LUTs, 1 DSP
      • EXP=8, WIDTH=19: 215 LUTs, 1 DSP
      • EXP=8, WIDTH=18: 169 LUTs, 1 DSP
      • EXP=7, WIDTH=24: 321 LUTs, 3 DSPs
      • EXP=9, WIDTH=24: 311 LUTs, 3 DSPs
    • MUL_CONST
      • EXP=8, WIDTH=24
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