inst_commands.go

// Code generated by gen/inst/inst.go; DO NOT EDIT.

package arm

// The Commands table contains opcode/encoding info for all instructions.
// Each encoding contains a 32-bit opcode, followed by a length-prefixed list
// of encoding operators. Encoding operators apply to Flat types.
// Opcode bytes are big-endian ordered to match encoding diagrams.
// The table is indexed through offsets stored in the Patterns table.
var Commands = [...]byte{
	// abs Dd, Dn
	0b01011110, 0b11100000, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// abs Vd.16B, Vn.16B
	// abs Vd.8B, Vn.8B
	0b00001110, 0b00100000, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// abs Vd.8H, Vn.8H
	// abs Vd.4H, Vn.4H
	0b00001110, 0b01100000, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// abs Vd.4S, Vn.4S
	// abs Vd.2S, Vn.2S
	0b00001110, 0b10100000, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// abs Vd.2D, Vn.2D
	0b00001110, 0b11100000, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// adc Wd, Wn, Wm
	0b00011010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// adc Xd, Xn, Xm
	0b10011010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// adcs Wd, Wn, Wm
	0b00111010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// adcs Xd, Xn, Xm
	0b10111010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// add Wd, Wn, Wm {, LSL|LSR|ASR #imm }  ·········································  (0 <= imm < 32)
	0b00001011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// add Xd, Xn, Xm {, LSL|LSR|ASR #imm }  ·········································  (0 <= imm < 64)
	0b10001011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,
	// add Wd|WSP, Wn|WSP, Wm {, LSL|UXT[BHWX]|SXT[BHWX] #imm }  ·····················  (0 <= imm <= 4)
	0b00001011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsW, CmdUrange, 10, 0, 4,
	// add Xd|SP, Xn|SP, Wm {, UXT[BHW]|SXT[BHW] #imm }  ·····························  (0 <= imm <= 4)
	0b10001011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// add Xd|SP, Xn|SP, Xm {, LSL|UXTX|SXTX #imm }  ·································  (0 <= imm <= 4)
	0b10001011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// add Wd|WSP, Wn|WSP, #imm1 {, LSL #imm2 }  ·················  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b00010001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,
	// add Xd|SP, Xn|SP, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b10010001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,
	// add Dd, Dn, Dm
	0b01011110, 0b11100000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// add Vd.16B, Vn.16B, Vm.16B
	// add Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// add Vd.8H, Vn.8H, Vm.8H
	// add Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// add Vd.4S, Vn.4S, Vm.4S
	// add Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// add Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// addhn Vd.8B, Vn.8H, Vm.8H
	0b00001110, 0b00100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// addhn Vd.4H, Vn.4S, Vm.4S
	0b00001110, 0b01100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// addhn Vd.2S, Vn.2D, Vm.2D
	0b00001110, 0b10100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// addhn2 Vd.16B, Vn.8H, Vm.8H
	0b01001110, 0b00100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// addhn2 Vd.8H, Vn.4S, Vm.4S
	0b01001110, 0b01100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// addhn2 Vd.4S, Vn.2D, Vm.2D
	0b01001110, 0b10100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// addp Dd, Vn.2D
	0b01011110, 0b11110001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// addp Vd.16B, Vn.16B, Vm.16B
	// addp Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// addp Vd.8H, Vn.8H, Vm.8H
	// addp Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// addp Vd.4S, Vn.4S, Vm.4S
	// addp Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// addp Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b10111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// adds Wd, Wn, Wm {, LSL|LSR|ASR #imm }  ········································  (0 <= imm < 32)
	0b00101011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// adds Xd, Xn, Xm {, LSL|LSR|ASR #imm }  ········································  (0 <= imm < 64)
	0b10101011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,
	// adds Wd, Wn|WSP, Wm {, LSL|UXT[BHWX]|SXT[BHWX] #imm }  ························  (0 <= imm <= 4)
	0b00101011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsW, CmdUrange, 10, 0, 4,
	// adds Xd, Xn|SP, Wm {, UXT[BHW]|SXT[BHW] #imm }  ·······························  (0 <= imm <= 4)
	0b10101011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// adds Xd, Xn|SP, Xm {, LSL|UXTX|SXTX #imm }  ···································  (0 <= imm <= 4)
	0b10101011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// adds Wd, Wn|WSP, #imm1 {, LSL #imm2 }  ····················  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b00110001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,
	// adds Xd, Xn|SP, #imm1 {, LSL #imm2 }  ·····················  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b10110001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,

	// addv Bd, Vn.16B
	// addv Bd, Vn.8B
	0b00001110, 0b00110001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// addv Hd, Vn.8H
	// addv Hd, Vn.4H
	0b00001110, 0b01110001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// addv Sd, Vn.4S
	0b00001110, 0b10110001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// adr Xd, <offset>  ···············································  (offset is 21-bit (+/- 1 MB))
	0b00010000, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelAdr,

	// adrp Xd, <offset>  ········································  (offset >> 12 is 21-bit (+/- 4 GB))
	0b10010000, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelAdrp,

	// aesd Vd.16B, Vn.16B
	0b01001110, 0b00101000, 0b01011000, 0b00000000, 2, CmdR0, CmdR5,

	// aese Vd.16B, Vn.16B
	0b01001110, 0b00101000, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,

	// aesimc Vd.16B, Vn.16B
	0b01001110, 0b00101000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,

	// aesmc Vd.16B, Vn.16B
	0b01001110, 0b00101000, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,

	// and Vd.16B, Vn.16B, Vm.16B
	// and Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// and Wd|WSP, Wn, #imm  ·················································  (imm is 32-bit logical)
	0b00010010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSpecial, 10, SpecialImmLogical32,
	// and Xd|SP, Xn, #imm  ··················································  (imm is 64-bit logical)
	0b10010010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSpecial, 10, SpecialImmLogical64,
	// and Wd, Wn, Wm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 32)
	0b00001010, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// and Xd, Xn, Xm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 64)
	0b10001010, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// ands Wd, Wn, #imm  ····················································  (imm is 32-bit logical)
	0b01110010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSpecial, 10, SpecialImmLogical32,
	// ands Xd, Xn, #imm  ····················································  (imm is 64-bit logical)
	0b11110010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSpecial, 10, SpecialImmLogical64,
	// ands Wd, Wn, Wm {, LSL|LSR|ASR|ROR #imm }  ····································  (0 <= imm < 32)
	0b01101010, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// ands Xd, Xn, Xm {, LSL|LSR|ASR|ROR #imm }  ····································  (0 <= imm < 64)
	0b11101010, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// asr Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// asr Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// asr Wd, Wn, #imm  ·····························································  (0 <= imm < 32)
	0b00010011, 0b00000000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,
	// asr Xd, Xn, #imm  ·····························································  (0 <= imm < 64)
	0b10010011, 0b01000000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 6,

	// asrv Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// asrv Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// at <symbol>, Xn
	0b11010101, 0b00001000, 0b01111000, 0b00000000, 2, CmdLitList, 5, SymATOPS, CmdR0,

	// autda Xd, Xn|SP
	0b11011010, 0b11000001, 0b00011000, 0b00000000, 2, CmdR0, CmdR5,

	// autdb Xd, Xn|SP
	0b11011010, 0b11000001, 0b00011100, 0b00000000, 2, CmdR0, CmdR5,

	// autdza Xd
	0b11011010, 0b11000001, 0b00111011, 0b11100000, 1, CmdR0,

	// autdzb Xd
	0b11011010, 0b11000001, 0b00111111, 0b11100000, 1, CmdR0,

	// autia Xd, Xn|SP
	0b11011010, 0b11000001, 0b00010000, 0b00000000, 2, CmdR0, CmdR5,

	// autia1716
	0b11010101, 0b00000011, 0b00100001, 0b10011111, 0,

	// autiasp
	0b11010101, 0b00000011, 0b00100011, 0b10111111, 0,

	// autiaz
	0b11010101, 0b00000011, 0b00100011, 0b10011111, 0,

	// autib Xd, Xn|SP
	0b11011010, 0b11000001, 0b00010100, 0b00000000, 2, CmdR0, CmdR5,

	// autib1716
	0b11010101, 0b00000011, 0b00100001, 0b11011111, 0,

	// autibsp
	0b11010101, 0b00000011, 0b00100011, 0b11111111, 0,

	// autibz
	0b11010101, 0b00000011, 0b00100011, 0b11011111, 0,

	// autiza Xd
	0b11011010, 0b11000001, 0b00110011, 0b11100000, 1, CmdR0,

	// autizb Xd
	0b11011010, 0b11000001, 0b00110111, 0b11100000, 1, CmdR0,

	// b <cond>, <offset>  ········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b01010100, 0b00000000, 0b00000000, 0b00000000, 2, CmdCond, 0, CmdOffset, RelBCond,
	// b <offset>  ··············································  (offset >> 2 is 26-bit (+/- 128 MB))
	0b00010100, 0b00000000, 0b00000000, 0b00000000, 1, CmdOffset, RelB,

	// bcax Vd.16B, Vn.16B, Vm.16B, Va.16B
	0b11001110, 0b00100000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// bfc Wd, #imm1, #imm2  ·····················  (0 <= imm1 < 32, 0 < imm2 <= 32, imm1 + imm2 <= 32)
	0b00110011, 0b00000000, 0b00000011, 0b11100000, 4, CmdR0, CmdUnegmod, 16, 5, CmdChkUsum, 5, CmdUrange, 10, 1, 32,
	// bfc Xd, #imm1, #imm2  ·····················  (0 <= imm1 < 64, 0 < imm2 <= 64, imm1 + imm2 <= 64)
	0b10110011, 0b01000000, 0b00000011, 0b11100000, 4, CmdR0, CmdUnegmod, 16, 6, CmdChkUsum, 6, CmdUrange, 10, 1, 64,

	// bfi Wd, Wn, #imm1, #imm2  ·················  (0 <= imm1 < 32, 0 < imm2 <= 32, imm1 + imm2 <= 32)
	0b00110011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUnegmod, 16, 5, CmdChkUsum, 5, CmdUrange, 10, 1, 32,
	// bfi Xd, Xn, #imm1, #imm2  ·················  (0 <= imm1 < 64, 0 < imm2 <= 64, imm1 + imm2 <= 64)
	0b10110011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUnegmod, 16, 6, CmdChkUsum, 6, CmdUrange, 10, 1, 64,

	// bfm Wd, Wn, #imm1, #imm2  ····································  (0 <= imm1 < 32, 0 <= imm2 < 32)
	0b00110011, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 5, CmdUbits, 10, 5,
	// bfm Xd, Xn, #imm1, #imm2  ··················  (0 <= imm1 < 64, 0 < imm2 < 64, imm1 + imm2 <= 64)
	0b10110011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 6, CmdChkUsum, 6, CmdUbits, 10, 6,

	// bfxil Wd, Wn, #imm1, #imm2  ···············  (0 <= imm1 < 32, 0 < imm2 <= 32, imm1 + imm2 <= 32)
	0b00110011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 5, CmdChkUsum, 5, CmdUsumdec, 10, 5,
	// bfxil Xd, Xn, #imm1, #imm2  ···············  (0 <= imm1 < 64, 0 < imm2 <= 64, imm1 + imm2 <= 64)
	0b10110011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 6, CmdChkUsum, 6, CmdUsumdec, 10, 6,

	// bic Vd.8H, #imm1 {, LSL #imm2 }  ····························  (0 <= imm1 < 256, imm2 in [0, 8])
	// bic Vd.4H, #imm1 {, LSL #imm2 }  ····························  (0 <= imm1 < 256, imm2 in [0, 8])
	0b00101111, 0b00000000, 0b10010100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt2, 13, 5, CmdRwidth30,
	// bic Vd.4S, #imm1 {, LSL #imm2 }  ····················  (0 <= imm1 < 256, imm2 in [0, 8, 16, 24])
	// bic Vd.2S, #imm1 {, LSL #imm2 }  ····················  (0 <= imm1 < 256, imm2 in [0, 8, 16, 24])
	0b00101111, 0b00000000, 0b00010100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt4, 13, 0, CmdRwidth30,
	// bic Vd.16B, Vn.16B, Vm.16B
	// bic Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b01100000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// bic Wd, Wn, Wm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 32)
	0b00001010, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// bic Xd, Xn, Xm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 64)
	0b10001010, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// bics Wd, Wn, Wm {, LSL|LSR|ASR|ROR #imm }  ····································  (0 <= imm < 32)
	0b01101010, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// bics Xd, Xn, Xm {, LSL|LSR|ASR|ROR #imm }  ····································  (0 <= imm < 64)
	0b11101010, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// bif Vd.16B, Vn.16B, Vm.16B
	// bif Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b11100000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// bit Vd.16B, Vn.16B, Vm.16B
	// bit Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b10100000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// bl <offset>  ·············································  (offset >> 2 is 26-bit (+/- 128 MB))
	0b10010100, 0b00000000, 0b00000000, 0b00000000, 1, CmdOffset, RelB,

	// blr Xd
	0b11010110, 0b00111111, 0b00000000, 0b00000000, 1, CmdR5,

	// blraa Xd, Xn|SP
	0b11010111, 0b00111111, 0b00001000, 0b00000000, 2, CmdR5, CmdR0,

	// blraaz Xd
	0b11010110, 0b00111111, 0b00001000, 0b00011111, 1, CmdR5,

	// blrab Xd, Xn|SP
	0b11010111, 0b00111111, 0b00001100, 0b00000000, 2, CmdR5, CmdR0,

	// blrabz Xd
	0b11010110, 0b00111111, 0b00001100, 0b00011111, 1, CmdR5,

	// br Xd
	0b11010110, 0b00011111, 0b00000000, 0b00000000, 1, CmdR5,

	// braa Xd, Xn|SP
	0b11010111, 0b00011111, 0b00001000, 0b00000000, 2, CmdR5, CmdR0,

	// braaz Xd
	0b11010110, 0b00011111, 0b00001000, 0b00011111, 1, CmdR5,

	// brab Xd, Xn|SP
	0b11010111, 0b00011111, 0b00001100, 0b00000000, 2, CmdR5, CmdR0,

	// brabz Xd
	0b11010110, 0b00011111, 0b00001100, 0b00011111, 1, CmdR5,

	// brk #imm  ··································································  (0 <= imm < 65536)
	0b11010100, 0b00100000, 0b00000000, 0b00000000, 1, CmdUbits, 5, 16,

	// bsl Vd.16B, Vn.16B, Vm.16B
	// bsl Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b01100000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// cas Wd, Wn, [Xm|SP]
	0b10001000, 0b10100000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// cas Xd, Xn, [Xm|SP]
	0b11001000, 0b10100000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casa Wd, Wn, [Xm|SP]
	0b10001000, 0b11100000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// casa Xd, Xn, [Xm|SP]
	0b11001000, 0b11100000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casab Wd, Wn, [Xm|SP]
	0b00001000, 0b11100000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casah Wd, Wn, [Xm|SP]
	0b01001000, 0b11100000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casal Wd, Wn, [Xm|SP]
	0b10001000, 0b11100000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// casal Xd, Xn, [Xm|SP]
	0b11001000, 0b11100000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casalb Wd, Wn, [Xm|SP]
	0b00001000, 0b11100000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casalh Wd, Wn, [Xm|SP]
	0b01001000, 0b11100000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casb Wd, Wn, [Xm|SP]
	0b00001000, 0b10100000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// cash Wd, Wn, [Xm|SP]
	0b01001000, 0b10100000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casl Wd, Wn, [Xm|SP]
	0b10001000, 0b10100000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// casl Xd, Xn, [Xm|SP]
	0b11001000, 0b10100000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// caslb Wd, Wn, [Xm|SP]
	0b00001000, 0b10100000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// caslh Wd, Wn, [Xm|SP]
	0b01001000, 0b10100000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// casp Wn, Wm, Wa, Wb, [Xd|SP]  ··················  (n is even, m == n + 1, a is even, b == a + 1)
	0b00001000, 0b00100000, 0b01111100, 0b00000000, 5, CmdREven, 16, CmdRNext, CmdREven, 0, CmdRNext, CmdR5,
	// casp Xn, Xm, Xa, Xb, [Xd|SP]  ··················  (n is even, m == n + 1, a is even, b == a + 1)
	0b01001000, 0b00100000, 0b01111100, 0b00000000, 5, CmdREven, 16, CmdRNext, CmdREven, 0, CmdRNext, CmdR5,

	// caspa Wn, Wm, Wa, Wb, [Xd|SP]  ·················  (n is even, m == n + 1, a is even, b == a + 1)
	0b00001000, 0b01100000, 0b01111100, 0b00000000, 5, CmdREven, 16, CmdRNext, CmdREven, 0, CmdRNext, CmdR5,
	// caspa Xn, Xm, Xa, Xb, [Xd|SP]  ·················  (n is even, m == n + 1, a is even, b == a + 1)
	0b01001000, 0b01100000, 0b01111100, 0b00000000, 5, CmdREven, 16, CmdRNext, CmdREven, 0, CmdRNext, CmdR5,

	// caspal Wn, Wm, Wa, Wb, [Xd|SP]  ················  (n is even, m == n + 1, a is even, b == a + 1)
	0b00001000, 0b01100000, 0b11111100, 0b00000000, 5, CmdREven, 16, CmdRNext, CmdREven, 0, CmdRNext, CmdR5,
	// caspal Xn, Xm, Xa, Xb, [Xd|SP]  ················  (n is even, m == n + 1, a is even, b == a + 1)
	0b01001000, 0b01100000, 0b11111100, 0b00000000, 5, CmdREven, 16, CmdRNext, CmdREven, 0, CmdRNext, CmdR5,

	// caspl Wn, Wm, Wa, Wb, [Xd|SP]  ·················  (n is even, m == n + 1, a is even, b == a + 1)
	0b00001000, 0b00100000, 0b11111100, 0b00000000, 5, CmdREven, 16, CmdRNext, CmdREven, 0, CmdRNext, CmdR5,
	// caspl Xn, Xm, Xa, Xb, [Xd|SP]  ·················  (n is even, m == n + 1, a is even, b == a + 1)
	0b01001000, 0b00100000, 0b11111100, 0b00000000, 5, CmdREven, 16, CmdRNext, CmdREven, 0, CmdRNext, CmdR5,

	// cbnz Wd, <offset>  ·········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b00110101, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,
	// cbnz Xd, <offset>  ·········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b10110101, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,

	// cbz Wd, <offset>  ··········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b00110100, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,
	// cbz Xd, <offset>  ··········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b10110100, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,

	// ccmn Wd, #imm1, #imm2, <cond>  ·······························  (0 <= imm1 < 32, 0 <= imm2 < 16)
	0b00111010, 0b01000000, 0b00001000, 0b00000000, 4, CmdR5, CmdUbits, 16, 5, CmdUbits, 0, 4, CmdCond, 12,
	// ccmn Xd, #imm1, #imm2, <cond>  ·······························  (0 <= imm1 < 32, 0 <= imm2 < 16)
	0b10111010, 0b01000000, 0b00001000, 0b00000000, 4, CmdR5, CmdUbits, 16, 5, CmdUbits, 0, 4, CmdCond, 12,
	// ccmn Wd, Wn, #imm, <cond>  ····················································  (0 <= imm < 16)
	0b00111010, 0b01000000, 0b00000000, 0b00000000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,
	// ccmn Xd, Xn, #imm, <cond>  ····················································  (0 <= imm < 16)
	0b10111010, 0b01000000, 0b00000000, 0b00000000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,

	// ccmp Wd, #imm1, #imm2, <cond>  ·······························  (0 <= imm1 < 32, 0 <= imm2 < 16)
	0b01111010, 0b01000000, 0b00001000, 0b00000000, 4, CmdR5, CmdUbits, 16, 5, CmdUbits, 0, 4, CmdCond, 12,
	// ccmp Xd, #imm1, #imm2, <cond>  ·······························  (0 <= imm1 < 32, 0 <= imm2 < 16)
	0b11111010, 0b01000000, 0b00001000, 0b00000000, 4, CmdR5, CmdUbits, 16, 5, CmdUbits, 0, 4, CmdCond, 12,
	// ccmp Wd, Wn, #imm, <cond>  ····················································  (0 <= imm < 16)
	0b01111010, 0b01000000, 0b00000000, 0b00000000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,
	// ccmp Xd, Xn, #imm, <cond>  ····················································  (0 <= imm < 16)
	0b11111010, 0b01000000, 0b00000000, 0b00000000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,

	// cfinv
	0b11010101, 0b00000000, 0b01000000, 0b00011111, 0,

	// cfp RCTX, Xn
	0b11010101, 0b00001011, 0b01110011, 0b10000000, 1, CmdR0,

	// cinc Wd, Wn, <cond>
	0b00011010, 0b10000000, 0b00000100, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdCondInv, 12,
	// cinc Xd, Xn, <cond>
	0b10011010, 0b10000000, 0b00000100, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdCondInv, 12,

	// cinv Wd, Wn, <cond>
	0b01011010, 0b10000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdCondInv, 12,
	// cinv Xd, Xn, <cond>
	0b11011010, 0b10000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdCondInv, 12,

	// clrex #imm  ···································································  (0 <= imm < 16)
	0b11010101, 0b00000011, 0b00110000, 0b01011111, 1, CmdUbits, 8, 4,
	// clrex
	0b11010101, 0b00000011, 0b00111111, 0b01011111, 0,

	// cls Vd.16B, Vn.16B
	// cls Vd.8B, Vn.8B
	0b00001110, 0b00100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cls Vd.8H, Vn.8H
	// cls Vd.4H, Vn.4H
	0b00001110, 0b01100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cls Vd.4S, Vn.4S
	// cls Vd.2S, Vn.2S
	0b00001110, 0b10100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cls Wd, Wn
	0b01011010, 0b11000000, 0b00010100, 0b00000000, 2, CmdR0, CmdR5,
	// cls Xd, Xn
	0b11011010, 0b11000000, 0b00010100, 0b00000000, 2, CmdR0, CmdR5,

	// clz Vd.16B, Vn.16B
	// clz Vd.8B, Vn.8B
	0b00101110, 0b00100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// clz Vd.8H, Vn.8H
	// clz Vd.4H, Vn.4H
	0b00101110, 0b01100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// clz Vd.4S, Vn.4S
	// clz Vd.2S, Vn.2S
	0b00101110, 0b10100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// clz Wd, Wn
	0b01011010, 0b11000000, 0b00010000, 0b00000000, 2, CmdR0, CmdR5,
	// clz Xd, Xn
	0b11011010, 0b11000000, 0b00010000, 0b00000000, 2, CmdR0, CmdR5,

	// cmeq Dd, Dn, Dm
	0b01111110, 0b11100000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// cmeq Vd.16B, Vn.16B, Vm.16B
	// cmeq Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmeq Vd.8H, Vn.8H, Vm.8H
	// cmeq Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmeq Vd.4S, Vn.4S, Vm.4S
	// cmeq Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmeq Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmeq Dd, Dn, #0
	0b01011110, 0b11100000, 0b10011000, 0b00000000, 2, CmdR0, CmdR5,
	// cmeq Vd.16B, Vn.16B, #0
	// cmeq Vd.8B, Vn.8B, #0
	0b00001110, 0b00100000, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmeq Vd.8H, Vn.8H, #0
	// cmeq Vd.4H, Vn.4H, #0
	0b00001110, 0b01100000, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmeq Vd.4S, Vn.4S, #0
	// cmeq Vd.2S, Vn.2S, #0
	0b00001110, 0b10100000, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmeq Vd.2D, Vn.2D, #0
	0b00001110, 0b11100000, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// cmge Dd, Dn, Dm
	0b01011110, 0b11100000, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// cmge Vd.16B, Vn.16B, Vm.16B
	// cmge Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmge Vd.8H, Vn.8H, Vm.8H
	// cmge Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmge Vd.4S, Vn.4S, Vm.4S
	// cmge Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmge Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmge Dd, Dn, #0
	0b01111110, 0b11100000, 0b10001000, 0b00000000, 2, CmdR0, CmdR5,
	// cmge Vd.16B, Vn.16B, #0
	// cmge Vd.8B, Vn.8B, #0
	0b00101110, 0b00100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmge Vd.8H, Vn.8H, #0
	// cmge Vd.4H, Vn.4H, #0
	0b00101110, 0b01100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmge Vd.4S, Vn.4S, #0
	// cmge Vd.2S, Vn.2S, #0
	0b00101110, 0b10100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmge Vd.2D, Vn.2D, #0
	0b00101110, 0b11100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// cmgt Dd, Dn, Dm
	0b01011110, 0b11100000, 0b00110100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// cmgt Vd.16B, Vn.16B, Vm.16B
	// cmgt Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmgt Vd.8H, Vn.8H, Vm.8H
	// cmgt Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmgt Vd.4S, Vn.4S, Vm.4S
	// cmgt Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmgt Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmgt Dd, Dn, #0
	0b01011110, 0b11100000, 0b10001000, 0b00000000, 2, CmdR0, CmdR5,
	// cmgt Vd.16B, Vn.16B, #0
	// cmgt Vd.8B, Vn.8B, #0
	0b00001110, 0b00100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmgt Vd.8H, Vn.8H, #0
	// cmgt Vd.4H, Vn.4H, #0
	0b00001110, 0b01100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmgt Vd.4S, Vn.4S, #0
	// cmgt Vd.2S, Vn.2S, #0
	0b00001110, 0b10100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmgt Vd.2D, Vn.2D, #0
	0b00001110, 0b11100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// cmhi Dd, Dn, Dm
	0b01111110, 0b11100000, 0b00110100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// cmhi Vd.16B, Vn.16B, Vm.16B
	// cmhi Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmhi Vd.8H, Vn.8H, Vm.8H
	// cmhi Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmhi Vd.4S, Vn.4S, Vm.4S
	// cmhi Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmhi Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// cmhs Dd, Dn, Dm
	0b01111110, 0b11100000, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// cmhs Vd.16B, Vn.16B, Vm.16B
	// cmhs Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmhs Vd.8H, Vn.8H, Vm.8H
	// cmhs Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmhs Vd.4S, Vn.4S, Vm.4S
	// cmhs Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmhs Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// cmle Dd, Dn, #0
	0b01111110, 0b11100000, 0b10011000, 0b00000000, 2, CmdR0, CmdR5,
	// cmle Vd.16B, Vn.16B, #0
	// cmle Vd.8B, Vn.8B, #0
	0b00101110, 0b00100000, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmle Vd.8H, Vn.8H, #0
	// cmle Vd.4H, Vn.4H, #0
	0b00101110, 0b01100000, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmle Vd.4S, Vn.4S, #0
	// cmle Vd.2S, Vn.2S, #0
	0b00101110, 0b10100000, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmle Vd.2D, Vn.2D, #0
	0b00101110, 0b11100000, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// cmlt Dd, Dn, #0
	0b01011110, 0b11100000, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// cmlt Vd.16B, Vn.16B, #0
	// cmlt Vd.8B, Vn.8B, #0
	0b00001110, 0b00100000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmlt Vd.8H, Vn.8H, #0
	// cmlt Vd.4H, Vn.4H, #0
	0b00001110, 0b01100000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmlt Vd.4S, Vn.4S, #0
	// cmlt Vd.2S, Vn.2S, #0
	0b00001110, 0b10100000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// cmlt Vd.2D, Vn.2D, #0
	0b00001110, 0b11100000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// cmn Wd, Wn {, LSL|LSR|ASR #imm }  ·············································  (0 <= imm < 32)
	0b00101011, 0b00000000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// cmn Xd, Xn {, LSL|LSR|ASR #imm }  ·············································  (0 <= imm < 64)
	0b10101011, 0b00000000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,
	// cmn Wd|WSP, Wn {, LSL|UXT[BHWX]|SXT[BHWX] #imm }  ·····························  (0 <= imm <= 4)
	0b00101011, 0b00100000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdExtendsW, CmdUrange, 10, 0, 4,
	// cmn Xd|SP, Wn, UXT[BHW]|SXT[BHW] #imm  ········································  (0 <= imm <= 4)
	0b10101011, 0b00100000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// cmn Xd|SP, Xn {, LSL|UXTX|SXTX #imm }  ········································  (0 <= imm <= 4)
	0b10101011, 0b00100000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// cmn Wd|WSP, #imm1 {, LSL #imm2 }  ·························  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b00110001, 0b00000000, 0b00000000, 0b00011111, 3, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,
	// cmn Xd|SP, #imm1 {, LSL #imm2 }  ··························  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b10110001, 0b00000000, 0b00000000, 0b00011111, 3, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,

	// cmp Wd, Wn {, LSL|LSR|ASR #imm }  ·············································  (0 <= imm < 32)
	0b01101011, 0b00000000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// cmp Xd, Xn {, LSL|LSR|ASR #imm }  ·············································  (0 <= imm < 64)
	0b11101011, 0b00000000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,
	// cmp Wd|WSP, Wn {, LSL|UXT[BHWX]|SXT[BHWX] #imm }  ·····························  (0 <= imm <= 4)
	0b01101011, 0b00100000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdExtendsW, CmdUrange, 10, 0, 4,
	// cmp Xd|SP, Wn, UXT[BHW]|SXT[BHW] #imm  ········································  (0 <= imm <= 4)
	0b11101011, 0b00100000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// cmp Xd|SP, Xn {, LSL|UXTX|SXTX #imm }  ········································  (0 <= imm <= 4)
	0b11101011, 0b00100000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// cmp Wd|WSP, #imm1 {, LSL #imm2 }  ·························  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b01110001, 0b00000000, 0b00000000, 0b00011111, 3, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,
	// cmp Xd|SP, #imm1 {, LSL #imm2 }  ··························  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b11110001, 0b00000000, 0b00000000, 0b00011111, 3, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,

	// cmtst Dd, Dn, Dm
	0b01011110, 0b11100000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// cmtst Vd.16B, Vn.16B, Vm.16B
	// cmtst Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmtst Vd.8H, Vn.8H, Vm.8H
	// cmtst Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmtst Vd.4S, Vn.4S, Vm.4S
	// cmtst Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// cmtst Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// cneg Wd, Wn, <cond>
	0b01011010, 0b10000000, 0b00000100, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdCondInv, 12,
	// cneg Xd, Xn, <cond>
	0b11011010, 0b10000000, 0b00000100, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdCondInv, 12,

	// cnt Vd.16B, Vn.16B
	// cnt Vd.8B, Vn.8B
	0b00001110, 0b00100000, 0b01011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// cpp RCTX, Xn
	0b11010101, 0b00001011, 0b01110011, 0b11100000, 1, CmdR0,

	// crc32b Wd, Wn, Wm
	0b00011010, 0b11000000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// crc32cb Wd, Wn, Wm
	0b00011010, 0b11000000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// crc32ch Wd, Wn, Wm
	0b00011010, 0b11000000, 0b01010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// crc32cw Wd, Wn, Wm
	0b00011010, 0b11000000, 0b01011000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// crc32cx Wd, Wn, Xm
	0b10011010, 0b11000000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// crc32h Wd, Wn, Wm
	0b00011010, 0b11000000, 0b01000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// crc32w Wd, Wn, Wm
	0b00011010, 0b11000000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// crc32x Wd, Wn, Xm
	0b10011010, 0b11000000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// csdb
	0b11010101, 0b00000011, 0b00100010, 0b10011111, 0,

	// csel Wd, Wn, Wm, <cond>
	0b00011010, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,
	// csel Xd, Xn, Xm, <cond>
	0b10011010, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,

	// cset Wd, <cond>
	0b00011010, 0b10011111, 0b00000111, 0b11100000, 2, CmdR0, CmdCondInv, 12,
	// cset Xd, <cond>
	0b10011010, 0b10011111, 0b00000111, 0b11100000, 2, CmdR0, CmdCondInv, 12,

	// csetm Wd, <cond>
	0b01011010, 0b10011111, 0b00000011, 0b11100000, 2, CmdR0, CmdCondInv, 12,
	// csetm Xd, <cond>
	0b11011010, 0b10011111, 0b00000011, 0b11100000, 2, CmdR0, CmdCondInv, 12,

	// csinc Wd, Wn, Wm, <cond>
	0b00011010, 0b10000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,
	// csinc Xd, Xn, Xm, <cond>
	0b10011010, 0b10000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,

	// csinv Wd, Wn, Wm, <cond>
	0b01011010, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,
	// csinv Xd, Xn, Xm, <cond>
	0b11011010, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,

	// csneg Wd, Wn, Wm, <cond>
	0b01011010, 0b10000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,
	// csneg Xd, Xn, Xm, <cond>
	0b11011010, 0b10000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,

	// dc <symbol>, Xn
	0b11010101, 0b00001000, 0b01110000, 0b00000000, 2, CmdLitList, 5, SymDCOPS, CmdR0,

	// dcps1  {, #imm }  ··························································  (0 <= imm < 65536)
	0b11010100, 0b10100000, 0b00000000, 0b00000001, 1, CmdUbits, 5, 16,

	// dcps2  {, #imm }  ··························································  (0 <= imm < 65536)
	0b11010100, 0b10100000, 0b00000000, 0b00000010, 1, CmdUbits, 5, 16,

	// dcps3  {, #imm }  ··························································  (0 <= imm < 65536)
	0b11010100, 0b10100000, 0b00000000, 0b00000011, 1, CmdUbits, 5, 16,

	// dmb <symbol>
	0b11010101, 0b00000011, 0b00110000, 0b10111111, 1, CmdLitList, 8, SymBARRIEROPS,
	// dmb #imm  ·····································································  (0 <= imm < 16)
	0b11010101, 0b00000011, 0b00110000, 0b10111111, 1, CmdUbits, 8, 4,

	// drps
	0b11010110, 0b10111111, 0b00000011, 0b11100000, 0,

	// dsb <symbol>
	0b11010101, 0b00000011, 0b00110000, 0b10011111, 1, CmdLitList, 8, SymBARRIEROPS,
	// dsb #imm  ·····································································  (0 <= imm < 16)
	0b11010101, 0b00000011, 0b00110000, 0b10011111, 1, CmdUbits, 8, 4,

	// dup Bd, Vn.B[i]
	0b01011110, 0b00000001, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 17, 4,
	// dup Hd, Vn.H[i]
	0b01011110, 0b00000010, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 18, 3,
	// dup Sd, Vn.S[i]
	0b01011110, 0b00000100, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 19, 2,
	// dup Dd, Vn.D[i]
	0b01011110, 0b00001000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 20, 1,
	// dup Vd.16B, Vn.B[i]
	// dup Vd.8B, Vn.B[i]
	0b00001110, 0b00000001, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 17, 4, CmdRwidth30,
	// dup Vd.8H, Vn.H[i]
	// dup Vd.4H, Vn.H[i]
	0b00001110, 0b00000010, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 18, 3, CmdRwidth30,
	// dup Vd.4S, Vn.S[i]
	// dup Vd.2S, Vn.S[i]
	0b00001110, 0b00000100, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 19, 2, CmdRwidth30,
	// dup Vd.2D, Vn.D[i]
	0b00001110, 0b00001000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 20, 1, CmdRwidth30,
	// dup Vd.16B, Wn
	// dup Vd.8B, Wn
	0b00001110, 0b00000001, 0b00001100, 0b00000000, 3, CmdR0, CmdRwidth30, CmdR5,
	// dup Vd.8H, Wn
	// dup Vd.4H, Wn
	0b00001110, 0b00000010, 0b00001100, 0b00000000, 3, CmdR0, CmdRwidth30, CmdR5,
	// dup Vd.4S, Wn
	// dup Vd.2S, Wn
	0b00001110, 0b00000100, 0b00001100, 0b00000000, 3, CmdR0, CmdRwidth30, CmdR5,
	// dup Vd.2D, Xn
	0b00001110, 0b00001000, 0b00001100, 0b00000000, 3, CmdR0, CmdRwidth30, CmdR5,

	// dvp RCTX, Xn
	0b11010101, 0b00001011, 0b01110011, 0b10100000, 1, CmdR0,

	// eon Wd, Wn, Wm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 32)
	0b01001010, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// eon Xd, Xn, Xm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 64)
	0b11001010, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// eor Vd.16B, Vn.16B, Vm.16B
	// eor Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// eor Wd|WSP, Wn, #imm  ·················································  (imm is 32-bit logical)
	0b01010010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSpecial, 10, SpecialImmLogical32,
	// eor Xd|SP, Xn, #imm  ··················································  (imm is 64-bit logical)
	0b11010010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSpecial, 10, SpecialImmLogical64,
	// eor Wd, Wn, Wm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 32)
	0b01001010, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// eor Xd, Xn, Xm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 64)
	0b11001010, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// eor3 Vd.16B, Vn.16B, Vm.16B, Va.16B
	0b11001110, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// eret
	0b11010110, 0b10011111, 0b00000011, 0b11100000, 0,

	// eretaa
	0b11010110, 0b10011111, 0b00001011, 0b11111111, 0,

	// eretab
	0b11010110, 0b10011111, 0b00001111, 0b11111111, 0,

	// esb
	0b11010101, 0b00000011, 0b00100010, 0b00011111, 0,

	// ext Vd.8B, Vn.8B, Vm.8B, #imm  ·················································  (0 <= imm < 8)
	0b00101110, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 11, 3,
	// ext Vd.16B, Vn.16B, Vm.16B, #imm  ·············································  (0 <= imm < 16)
	0b01101110, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 11, 4,

	// extr Wd, Wn, Wm, #imm  ························································  (0 <= imm < 32)
	0b00010011, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 10, 5,
	// extr Xd, Xn, Xm, #imm  ························································  (0 <= imm < 64)
	0b10010011, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 10, 6,

	// fabd Hd, Hn, Hm
	0b01111110, 0b11000000, 0b00010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fabd Sd, Sn, Sm
	0b01111110, 0b10100000, 0b11010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fabd Dd, Dn, Dm
	0b01111110, 0b11100000, 0b11010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fabd Vd.8H, Vn.8H, Vm.8H
	// fabd Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b11000000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fabd Vd.4S, Vn.4S, Vm.4S
	// fabd Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b11010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fabd Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b11010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fabs Vd.8H, Vn.8H
	// fabs Vd.4H, Vn.4H
	0b00001110, 0b11111000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fabs Vd.4S, Vn.4S
	// fabs Vd.2S, Vn.2S
	0b00001110, 0b10100000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fabs Vd.2D, Vn.2D
	0b00001110, 0b11100000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fabs Hd, Hn
	0b00011110, 0b11100000, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// fabs Sd, Sn
	0b00011110, 0b00100000, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// fabs Dd, Dn
	0b00011110, 0b01100000, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,

	// facge Hd, Hn, Hm
	0b01111110, 0b01000000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// facge Sd, Sn, Sm
	0b01111110, 0b00100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// facge Dd, Dn, Dm
	0b01111110, 0b01100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// facge Vd.8H, Vn.8H, Vm.8H
	// facge Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// facge Vd.4S, Vn.4S, Vm.4S
	// facge Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b00100000, 0b11101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// facge Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b01100000, 0b11101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// facgt Hd, Hn, Hm
	0b01111110, 0b11000000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// facgt Sd, Sn, Sm
	0b01111110, 0b10100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// facgt Dd, Dn, Dm
	0b01111110, 0b11100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// facgt Vd.8H, Vn.8H, Vm.8H
	// facgt Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b11000000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// facgt Vd.4S, Vn.4S, Vm.4S
	// facgt Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b11101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// facgt Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b11101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fadd Vd.8H, Vn.8H, Vm.8H
	// fadd Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fadd Vd.4S, Vn.4S, Vm.4S
	// fadd Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b00100000, 0b11010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fadd Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b01100000, 0b11010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fadd Hd, Hn, Hm
	0b00011110, 0b11100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fadd Sd, Sn, Sm
	0b00011110, 0b00100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fadd Dd, Dn, Dm
	0b00011110, 0b01100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// faddp Hd, Vn.2H
	0b01011110, 0b00110000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// faddp Sd, Vn.2S
	0b01111110, 0b00110000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// faddp Dd, Vn.2D
	0b01111110, 0b01110000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// faddp Vd.8H, Vn.8H, Vm.8H
	// faddp Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// faddp Vd.4S, Vn.4S, Vm.4S
	// faddp Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b00100000, 0b11010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// faddp Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b01100000, 0b11010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fcadd Vd.8H, Vn.8H, Vm.8H, #imm  ···········································  (imm in [90, 270])
	// fcadd Vd.4H, Vn.4H, Vm.4H, #imm  ···········································  (imm in [90, 270])
	0b00101110, 0b01000000, 0b11100100, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUAlt2, 12, 9, CmdRwidth30,
	// fcadd Vd.4S, Vn.4S, Vm.4S, #imm  ···········································  (imm in [90, 270])
	// fcadd Vd.2S, Vn.2S, Vm.2S, #imm  ···········································  (imm in [90, 270])
	0b00101110, 0b10000000, 0b11100100, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUAlt2, 12, 9, CmdRwidth30,
	// fcadd Vd.2D, Vn.2D, Vm.2D, #imm  ···········································  (imm in [90, 270])
	0b00101110, 0b11000000, 0b11100100, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUAlt2, 12, 9, CmdRwidth30,

	// fccmp Hd, Hn, #imm, <cond>  ···················································  (0 <= imm < 16)
	0b00011110, 0b11100000, 0b00000100, 0b00000000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,
	// fccmp Sd, Sn, #imm, <cond>  ···················································  (0 <= imm < 16)
	0b00011110, 0b00100000, 0b00000100, 0b00000000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,
	// fccmp Dd, Dn, #imm, <cond>  ···················································  (0 <= imm < 16)
	0b00011110, 0b01100000, 0b00000100, 0b00000000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,

	// fccmpe Hd, Hn, #imm, <cond>  ··················································  (0 <= imm < 16)
	0b00011110, 0b11100000, 0b00000100, 0b00010000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,
	// fccmpe Sd, Sn, #imm, <cond>  ··················································  (0 <= imm < 16)
	0b00011110, 0b00100000, 0b00000100, 0b00010000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,
	// fccmpe Dd, Dn, #imm, <cond>  ··················································  (0 <= imm < 16)
	0b00011110, 0b01100000, 0b00000100, 0b00010000, 4, CmdR5, CmdR16, CmdUbits, 0, 4, CmdCond, 12,

	// fcmeq Hd, Hn, Hm
	0b01011110, 0b01000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmeq Sd, Sn, Sm
	0b01011110, 0b00100000, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmeq Dd, Dn, Dm
	0b01011110, 0b01100000, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmeq Vd.8H, Vn.8H, Vm.8H
	// fcmeq Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmeq Vd.4S, Vn.4S, Vm.4S
	// fcmeq Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b00100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmeq Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b01100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmeq Hd, Hn, #0.0
	0b01011110, 0b11111000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmeq Sd, Sn, #0.0
	0b01011110, 0b10100000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmeq Dd, Dn, #0.0
	0b01011110, 0b11100000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmeq Vd.8H, Vn.8H, #0.0
	// fcmeq Vd.4H, Vn.4H, #0.0
	0b00001110, 0b11111000, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmeq Vd.4S, Vn.4S, #0.0
	// fcmeq Vd.2S, Vn.2S, #0.0
	0b00001110, 0b10100000, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmeq Vd.2D, Vn.2D, #0.0
	0b00001110, 0b11100000, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fcmge Hd, Hn, Hm
	0b01111110, 0b01000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmge Sd, Sn, Sm
	0b01111110, 0b00100000, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmge Dd, Dn, Dm
	0b01111110, 0b01100000, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmge Vd.8H, Vn.8H, Vm.8H
	// fcmge Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmge Vd.4S, Vn.4S, Vm.4S
	// fcmge Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b00100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmge Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b01100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmge Hd, Hn, #0.0
	0b01111110, 0b11111000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmge Sd, Sn, #0.0
	0b01111110, 0b10100000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmge Dd, Dn, #0.0
	0b01111110, 0b11100000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmge Vd.8H, Vn.8H, #0.0
	// fcmge Vd.4H, Vn.4H, #0.0
	0b00101110, 0b11111000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmge Vd.4S, Vn.4S, #0.0
	// fcmge Vd.2S, Vn.2S, #0.0
	0b00101110, 0b10100000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmge Vd.2D, Vn.2D, #0.0
	0b00101110, 0b11100000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fcmgt Hd, Hn, Hm
	0b01111110, 0b11000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmgt Sd, Sn, Sm
	0b01111110, 0b10100000, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmgt Dd, Dn, Dm
	0b01111110, 0b11100000, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fcmgt Vd.8H, Vn.8H, Vm.8H
	// fcmgt Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b11000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmgt Vd.4S, Vn.4S, Vm.4S
	// fcmgt Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmgt Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fcmgt Hd, Hn, #0.0
	0b01011110, 0b11111000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmgt Sd, Sn, #0.0
	0b01011110, 0b10100000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmgt Dd, Dn, #0.0
	0b01011110, 0b11100000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmgt Vd.8H, Vn.8H, #0.0
	// fcmgt Vd.4H, Vn.4H, #0.0
	0b00001110, 0b11111000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmgt Vd.4S, Vn.4S, #0.0
	// fcmgt Vd.2S, Vn.2S, #0.0
	0b00001110, 0b10100000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmgt Vd.2D, Vn.2D, #0.0
	0b00001110, 0b11100000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fcmla Vd.4H, Vn.4H, Vm.H[i], #imm  ·································  (imm in [0, 90, 180, 270])
	0b00101111, 0b01000000, 0b00010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields21, CmdUAlt4, 13, 2,
	// fcmla Vd.8H, Vn.8H, Vm.H[i], #imm  ·································  (imm in [0, 90, 180, 270])
	0b01101111, 0b01000000, 0b00010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdUAlt4, 13, 2,
	// fcmla Vd.4S, Vn.4S, Vm.S[i], #imm  ·································  (imm in [0, 90, 180, 270])
	0b00101111, 0b10000000, 0b00010000, 0b00000000, 6, CmdR0, CmdR5, CmdR16, CmdUfields11, 1, CmdUAlt4, 13, 2, CmdRwidth30,
	// fcmla Vd.8H, Vn.8H, Vm.8H, #imm  ···································  (imm in [0, 90, 180, 270])
	// fcmla Vd.4H, Vn.4H, Vm.4H, #imm  ···································  (imm in [0, 90, 180, 270])
	0b00101110, 0b01000000, 0b11000100, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUAlt4, 11, 2, CmdRwidth30,
	// fcmla Vd.4S, Vn.4S, Vm.4S, #imm  ···································  (imm in [0, 90, 180, 270])
	// fcmla Vd.2S, Vn.2S, Vm.2S, #imm  ···································  (imm in [0, 90, 180, 270])
	0b00101110, 0b10000000, 0b11000100, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUAlt4, 11, 2, CmdRwidth30,
	// fcmla Vd.2D, Vn.2D, Vm.2D, #imm  ···································  (imm in [0, 90, 180, 270])
	0b00101110, 0b11000000, 0b11000100, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUAlt4, 11, 2, CmdRwidth30,

	// fcmle Hd, Hn, #0.0
	0b01111110, 0b11111000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmle Sd, Sn, #0.0
	0b01111110, 0b10100000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmle Dd, Dn, #0.0
	0b01111110, 0b11100000, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmle Vd.8H, Vn.8H, #0.0
	// fcmle Vd.4H, Vn.4H, #0.0
	0b00101110, 0b11111000, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmle Vd.4S, Vn.4S, #0.0
	// fcmle Vd.2S, Vn.2S, #0.0
	0b00101110, 0b10100000, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmle Vd.2D, Vn.2D, #0.0
	0b00101110, 0b11100000, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fcmlt Hd, Hn, #0.0
	0b01011110, 0b11111000, 0b11101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmlt Sd, Sn, #0.0
	0b01011110, 0b10100000, 0b11101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmlt Dd, Dn, #0.0
	0b01011110, 0b11100000, 0b11101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcmlt Vd.8H, Vn.8H, #0.0
	// fcmlt Vd.4H, Vn.4H, #0.0
	0b00001110, 0b11111000, 0b11101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmlt Vd.4S, Vn.4S, #0.0
	// fcmlt Vd.2S, Vn.2S, #0.0
	0b00001110, 0b10100000, 0b11101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcmlt Vd.2D, Vn.2D, #0.0
	0b00001110, 0b11100000, 0b11101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fcmp Hd, Hn
	0b00011110, 0b11100000, 0b00100000, 0b00000000, 2, CmdR5, CmdR16,
	// fcmp Hd, #0.0
	0b00011110, 0b11100000, 0b00100000, 0b00001000, 1, CmdR5,
	// fcmp Sd, Sn
	0b00011110, 0b00100000, 0b00100000, 0b00000000, 2, CmdR5, CmdR16,
	// fcmp Sd, #0.0
	0b00011110, 0b00100000, 0b00100000, 0b00001000, 1, CmdR5,
	// fcmp Dd, Dn
	0b00011110, 0b01100000, 0b00100000, 0b00000000, 2, CmdR5, CmdR16,
	// fcmp Dd, #0.0
	0b00011110, 0b01100000, 0b00100000, 0b00001000, 1, CmdR5,

	// fcmpe Hd, Hn
	0b00011110, 0b11100000, 0b00100000, 0b00010000, 2, CmdR5, CmdR16,
	// fcmpe Hd, #0.0
	0b00011110, 0b11100000, 0b00100000, 0b00011000, 1, CmdR5,
	// fcmpe Sd, Sn
	0b00011110, 0b00100000, 0b00100000, 0b00010000, 2, CmdR5, CmdR16,
	// fcmpe Sd, #0.0
	0b00011110, 0b00100000, 0b00100000, 0b00011000, 1, CmdR5,
	// fcmpe Dd, Dn
	0b00011110, 0b01100000, 0b00100000, 0b00010000, 2, CmdR5, CmdR16,
	// fcmpe Dd, #0.0
	0b00011110, 0b01100000, 0b00100000, 0b00011000, 1, CmdR5,

	// fcsel Hd, Hn, Hm, <cond>
	0b00011110, 0b11100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,
	// fcsel Sd, Sn, Sm, <cond>
	0b00011110, 0b00100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,
	// fcsel Dd, Dn, Dm, <cond>
	0b00011110, 0b01100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdCond, 12,

	// fcvt Sd, Hn
	0b00011110, 0b11100010, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvt Dd, Hn
	0b00011110, 0b11100010, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvt Hd, Sn
	0b00011110, 0b00100011, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvt Dd, Sn
	0b00011110, 0b00100010, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvt Hd, Dn
	0b00011110, 0b01100011, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvt Sd, Dn
	0b00011110, 0b01100010, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtas Hd, Hn
	0b01011110, 0b01111001, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtas Sd, Sn
	0b01011110, 0b00100001, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtas Dd, Dn
	0b01011110, 0b01100001, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtas Vd.8H, Vn.8H
	// fcvtas Vd.4H, Vn.4H
	0b00001110, 0b01111001, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtas Vd.4S, Vn.4S
	// fcvtas Vd.2S, Vn.2S
	0b00001110, 0b00100001, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtas Vd.2D, Vn.2D
	0b00001110, 0b01100001, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtas Wd, Hn
	0b00011110, 0b11100100, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtas Xd, Hn
	0b10011110, 0b11100100, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtas Wd, Sn
	0b00011110, 0b00100100, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtas Xd, Sn
	0b10011110, 0b00100100, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtas Wd, Dn
	0b00011110, 0b01100100, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtas Xd, Dn
	0b10011110, 0b01100100, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtau Hd, Hn
	0b01111110, 0b01111001, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtau Sd, Sn
	0b01111110, 0b00100001, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtau Dd, Dn
	0b01111110, 0b01100001, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtau Vd.8H, Vn.8H
	// fcvtau Vd.4H, Vn.4H
	0b00101110, 0b01111001, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtau Vd.4S, Vn.4S
	// fcvtau Vd.2S, Vn.2S
	0b00101110, 0b00100001, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtau Vd.2D, Vn.2D
	0b00101110, 0b01100001, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtau Wd, Hn
	0b00011110, 0b11100101, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtau Xd, Hn
	0b10011110, 0b11100101, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtau Wd, Sn
	0b00011110, 0b00100101, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtau Xd, Sn
	0b10011110, 0b00100101, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtau Wd, Dn
	0b00011110, 0b01100101, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtau Xd, Dn
	0b10011110, 0b01100101, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtl Vd.4S, Vn.4H
	0b00001110, 0b00100001, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtl Vd.2D, Vn.2S
	0b00001110, 0b01100001, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtl2 Vd.4S, Vn.8H
	0b01001110, 0b00100001, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtl2 Vd.2D, Vn.4S
	0b01001110, 0b01100001, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtms Hd, Hn
	0b01011110, 0b01111001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtms Sd, Sn
	0b01011110, 0b00100001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtms Dd, Dn
	0b01011110, 0b01100001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtms Vd.8H, Vn.8H
	// fcvtms Vd.4H, Vn.4H
	0b00001110, 0b01111001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtms Vd.4S, Vn.4S
	// fcvtms Vd.2S, Vn.2S
	0b00001110, 0b00100001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtms Vd.2D, Vn.2D
	0b00001110, 0b01100001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtms Wd, Hn
	0b00011110, 0b11110000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtms Xd, Hn
	0b10011110, 0b11110000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtms Wd, Sn
	0b00011110, 0b00110000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtms Xd, Sn
	0b10011110, 0b00110000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtms Wd, Dn
	0b00011110, 0b01110000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtms Xd, Dn
	0b10011110, 0b01110000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtmu Hd, Hn
	0b01111110, 0b01111001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtmu Sd, Sn
	0b01111110, 0b00100001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtmu Dd, Dn
	0b01111110, 0b01100001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtmu Vd.8H, Vn.8H
	// fcvtmu Vd.4H, Vn.4H
	0b00101110, 0b01111001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtmu Vd.4S, Vn.4S
	// fcvtmu Vd.2S, Vn.2S
	0b00101110, 0b00100001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtmu Vd.2D, Vn.2D
	0b00101110, 0b01100001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtmu Wd, Hn
	0b00011110, 0b11110001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtmu Xd, Hn
	0b10011110, 0b11110001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtmu Wd, Sn
	0b00011110, 0b00110001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtmu Xd, Sn
	0b10011110, 0b00110001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtmu Wd, Dn
	0b00011110, 0b01110001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtmu Xd, Dn
	0b10011110, 0b01110001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtn Vd.2S, Vn.2D
	0b00001110, 0b01100001, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtn2 Vd.4S, Vn.2D
	0b01001110, 0b01100001, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtns Hd, Hn
	0b01011110, 0b01111001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtns Sd, Sn
	0b01011110, 0b00100001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtns Dd, Dn
	0b01011110, 0b01100001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtns Vd.8H, Vn.8H
	// fcvtns Vd.4H, Vn.4H
	0b00001110, 0b01111001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtns Vd.4S, Vn.4S
	// fcvtns Vd.2S, Vn.2S
	0b00001110, 0b00100001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtns Vd.2D, Vn.2D
	0b00001110, 0b01100001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtns Wd, Hn
	0b00011110, 0b11100000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtns Xd, Hn
	0b10011110, 0b11100000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtns Wd, Sn
	0b00011110, 0b00100000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtns Xd, Sn
	0b10011110, 0b00100000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtns Wd, Dn
	0b00011110, 0b01100000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtns Xd, Dn
	0b10011110, 0b01100000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtnu Hd, Hn
	0b01111110, 0b01111001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtnu Sd, Sn
	0b01111110, 0b00100001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtnu Dd, Dn
	0b01111110, 0b01100001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtnu Vd.8H, Vn.8H
	// fcvtnu Vd.4H, Vn.4H
	0b00101110, 0b01111001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtnu Vd.4S, Vn.4S
	// fcvtnu Vd.2S, Vn.2S
	0b00101110, 0b00100001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtnu Vd.2D, Vn.2D
	0b00101110, 0b01100001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtnu Wd, Hn
	0b00011110, 0b11100001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtnu Xd, Hn
	0b10011110, 0b11100001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtnu Wd, Sn
	0b00011110, 0b00100001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtnu Xd, Sn
	0b10011110, 0b00100001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtnu Wd, Dn
	0b00011110, 0b01100001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtnu Xd, Dn
	0b10011110, 0b01100001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtps Hd, Hn
	0b01011110, 0b11111001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtps Sd, Sn
	0b01011110, 0b10100001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtps Dd, Dn
	0b01011110, 0b11100001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtps Vd.8H, Vn.8H
	// fcvtps Vd.4H, Vn.4H
	0b00001110, 0b11111001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtps Vd.4S, Vn.4S
	// fcvtps Vd.2S, Vn.2S
	0b00001110, 0b10100001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtps Vd.2D, Vn.2D
	0b00001110, 0b11100001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtps Wd, Hn
	0b00011110, 0b11101000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtps Xd, Hn
	0b10011110, 0b11101000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtps Wd, Sn
	0b00011110, 0b00101000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtps Xd, Sn
	0b10011110, 0b00101000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtps Wd, Dn
	0b00011110, 0b01101000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtps Xd, Dn
	0b10011110, 0b01101000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtpu Hd, Hn
	0b01111110, 0b11111001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtpu Sd, Sn
	0b01111110, 0b10100001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtpu Dd, Dn
	0b01111110, 0b11100001, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtpu Vd.8H, Vn.8H
	// fcvtpu Vd.4H, Vn.4H
	0b00101110, 0b11111001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtpu Vd.4S, Vn.4S
	// fcvtpu Vd.2S, Vn.2S
	0b00101110, 0b10100001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtpu Vd.2D, Vn.2D
	0b00101110, 0b11100001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtpu Wd, Hn
	0b00011110, 0b11101001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtpu Xd, Hn
	0b10011110, 0b11101001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtpu Wd, Sn
	0b00011110, 0b00101001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtpu Xd, Sn
	0b10011110, 0b00101001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtpu Wd, Dn
	0b00011110, 0b01101001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtpu Xd, Dn
	0b10011110, 0b01101001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtxn Sd, Dn
	0b01111110, 0b01100001, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtxn Vd.2S, Vn.2D
	0b00101110, 0b01100001, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtxn2 Vd.4S, Vn.2D
	0b01101110, 0b01100001, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtzs Hd, Hn, #imm  ··························································  (0 < imm <= 16)
	0b01011111, 0b00000000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// fcvtzs Sd, Sn, #imm  ··························································  (0 < imm <= 32)
	0b01011111, 0b00000000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// fcvtzs Dd, Dn, #imm  ··························································  (0 < imm <= 64)
	0b01011111, 0b00000000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// fcvtzs Vd.8H, Vn.8H, #imm  ····················································  (0 < imm <= 16)
	// fcvtzs Vd.4H, Vn.4H, #imm  ····················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// fcvtzs Vd.4S, Vn.4S, #imm  ····················································  (0 < imm <= 32)
	// fcvtzs Vd.2S, Vn.2S, #imm  ····················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// fcvtzs Vd.2D, Vn.2D, #imm  ····················································  (0 < imm <= 64)
	0b00001111, 0b01000000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,
	// fcvtzs Hd, Hn
	0b01011110, 0b11111001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzs Sd, Sn
	0b01011110, 0b10100001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzs Dd, Dn
	0b01011110, 0b11100001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzs Vd.8H, Vn.8H
	// fcvtzs Vd.4H, Vn.4H
	0b00001110, 0b11111001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtzs Vd.4S, Vn.4S
	// fcvtzs Vd.2S, Vn.2S
	0b00001110, 0b10100001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtzs Vd.2D, Vn.2D
	0b00001110, 0b11100001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtzs Wd, Hn, #imm  ··························································  (0 < imm <= 32)
	0b00011110, 0b11011000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// fcvtzs Xd, Hn, #imm  ··························································  (0 < imm <= 64)
	0b10011110, 0b11011000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// fcvtzs Wd, Sn, #imm  ··························································  (0 < imm <= 32)
	0b00011110, 0b00011000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// fcvtzs Xd, Sn, #imm  ··························································  (0 < imm <= 64)
	0b10011110, 0b00011000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// fcvtzs Wd, Dn, #imm  ··························································  (0 < imm <= 32)
	0b00011110, 0b01011000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// fcvtzs Xd, Dn, #imm  ··························································  (0 < imm <= 64)
	0b10011110, 0b01011000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// fcvtzs Wd, Hn
	0b00011110, 0b11111000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzs Xd, Hn
	0b10011110, 0b11111000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzs Wd, Sn
	0b00011110, 0b00111000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzs Xd, Sn
	0b10011110, 0b00111000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzs Wd, Dn
	0b00011110, 0b01111000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzs Xd, Dn
	0b10011110, 0b01111000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fcvtzu Hd, Hn, #imm  ··························································  (0 < imm <= 16)
	0b01111111, 0b00000000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// fcvtzu Sd, Sn, #imm  ··························································  (0 < imm <= 32)
	0b01111111, 0b00000000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// fcvtzu Dd, Dn, #imm  ··························································  (0 < imm <= 64)
	0b01111111, 0b00000000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// fcvtzu Vd.8H, Vn.8H, #imm  ····················································  (0 < imm <= 16)
	// fcvtzu Vd.4H, Vn.4H, #imm  ····················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// fcvtzu Vd.4S, Vn.4S, #imm  ····················································  (0 < imm <= 32)
	// fcvtzu Vd.2S, Vn.2S, #imm  ····················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// fcvtzu Vd.2D, Vn.2D, #imm  ····················································  (0 < imm <= 64)
	0b00101111, 0b01000000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,
	// fcvtzu Hd, Hn
	0b01111110, 0b11111001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzu Sd, Sn
	0b01111110, 0b10100001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzu Dd, Dn
	0b01111110, 0b11100001, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzu Vd.8H, Vn.8H
	// fcvtzu Vd.4H, Vn.4H
	0b00101110, 0b11111001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtzu Vd.4S, Vn.4S
	// fcvtzu Vd.2S, Vn.2S
	0b00101110, 0b10100001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtzu Vd.2D, Vn.2D
	0b00101110, 0b11100001, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fcvtzu Wd, Hn, #imm  ··························································  (0 < imm <= 32)
	0b00011110, 0b11011001, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// fcvtzu Xd, Hn, #imm  ··························································  (0 < imm <= 64)
	0b10011110, 0b11011001, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// fcvtzu Wd, Sn, #imm  ··························································  (0 < imm <= 32)
	0b00011110, 0b00011001, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// fcvtzu Xd, Sn, #imm  ··························································  (0 < imm <= 64)
	0b10011110, 0b00011001, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// fcvtzu Wd, Dn, #imm  ··························································  (0 < imm <= 32)
	0b00011110, 0b01011001, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// fcvtzu Xd, Dn, #imm  ··························································  (0 < imm <= 64)
	0b10011110, 0b01011001, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// fcvtzu Wd, Hn
	0b00011110, 0b11111001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzu Xd, Hn
	0b10011110, 0b11111001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzu Wd, Sn
	0b00011110, 0b00111001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzu Xd, Sn
	0b10011110, 0b00111001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzu Wd, Dn
	0b00011110, 0b01111001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fcvtzu Xd, Dn
	0b10011110, 0b01111001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fdiv Vd.8H, Vn.8H, Vm.8H
	// fdiv Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fdiv Vd.4S, Vn.4S, Vm.4S
	// fdiv Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b00100000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fdiv Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b01100000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fdiv Hd, Hn, Hm
	0b00011110, 0b11100000, 0b00011000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fdiv Sd, Sn, Sm
	0b00011110, 0b00100000, 0b00011000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fdiv Dd, Dn, Dm
	0b00011110, 0b01100000, 0b00011000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fjcvtzs Wd, Dn
	0b00011110, 0b01111110, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// fmadd Hd, Hn, Hm, Ha
	0b00011111, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// fmadd Sd, Sn, Sm, Sa
	0b00011111, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// fmadd Dd, Dn, Dm, Da
	0b00011111, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// fmax Vd.8H, Vn.8H, Vm.8H
	// fmax Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmax Vd.4S, Vn.4S, Vm.4S
	// fmax Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b00100000, 0b11110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmax Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b01100000, 0b11110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmax Hd, Hn, Hm
	0b00011110, 0b11100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmax Sd, Sn, Sm
	0b00011110, 0b00100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmax Dd, Dn, Dm
	0b00011110, 0b01100000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fmaxnm Vd.8H, Vn.8H, Vm.8H
	// fmaxnm Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmaxnm Vd.4S, Vn.4S, Vm.4S
	// fmaxnm Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b00100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmaxnm Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b01100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmaxnm Hd, Hn, Hm
	0b00011110, 0b11100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmaxnm Sd, Sn, Sm
	0b00011110, 0b00100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmaxnm Dd, Dn, Dm
	0b00011110, 0b01100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fmaxnmp Hd, Vn.2H
	0b01011110, 0b00110000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fmaxnmp Sd, Vn.2S
	0b01111110, 0b00110000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fmaxnmp Dd, Vn.2D
	0b01111110, 0b01110000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fmaxnmp Vd.8H, Vn.8H, Vm.8H
	// fmaxnmp Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmaxnmp Vd.4S, Vn.4S, Vm.4S
	// fmaxnmp Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b00100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmaxnmp Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b01100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fmaxnmv Hd, Vn.8H
	// fmaxnmv Hd, Vn.4H
	0b00001110, 0b00110000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fmaxnmv Sd, Vn.4S
	0b00101110, 0b00110000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fmaxp Hd, Vn.2H
	0b01011110, 0b00110000, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,
	// fmaxp Sd, Vn.2S
	0b01111110, 0b00110000, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,
	// fmaxp Dd, Vn.2D
	0b01111110, 0b01110000, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,
	// fmaxp Vd.8H, Vn.8H, Vm.8H
	// fmaxp Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmaxp Vd.4S, Vn.4S, Vm.4S
	// fmaxp Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b00100000, 0b11110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmaxp Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b01100000, 0b11110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fmaxv Hd, Vn.8H
	// fmaxv Hd, Vn.4H
	0b00001110, 0b00110000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fmaxv Sd, Vn.4S
	0b00101110, 0b00110000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fmin Vd.8H, Vn.8H, Vm.8H
	// fmin Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b11000000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmin Vd.4S, Vn.4S, Vm.4S
	// fmin Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b11110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmin Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b11110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmin Hd, Hn, Hm
	0b00011110, 0b11100000, 0b01011000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmin Sd, Sn, Sm
	0b00011110, 0b00100000, 0b01011000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmin Dd, Dn, Dm
	0b00011110, 0b01100000, 0b01011000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fminnm Vd.8H, Vn.8H, Vm.8H
	// fminnm Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b11000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fminnm Vd.4S, Vn.4S, Vm.4S
	// fminnm Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fminnm Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fminnm Hd, Hn, Hm
	0b00011110, 0b11100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fminnm Sd, Sn, Sm
	0b00011110, 0b00100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fminnm Dd, Dn, Dm
	0b00011110, 0b01100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fminnmp Hd, Vn.2H
	0b01011110, 0b10110000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fminnmp Sd, Vn.2S
	0b01111110, 0b10110000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fminnmp Dd, Vn.2D
	0b01111110, 0b11110000, 0b11001000, 0b00000000, 2, CmdR0, CmdR5,
	// fminnmp Vd.8H, Vn.8H, Vm.8H
	// fminnmp Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b11000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fminnmp Vd.4S, Vn.4S, Vm.4S
	// fminnmp Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fminnmp Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fminnmv Hd, Vn.8H
	// fminnmv Hd, Vn.4H
	0b00001110, 0b10110000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fminnmv Sd, Vn.4S
	0b00101110, 0b10110000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fminp Hd, Vn.2H
	0b01011110, 0b10110000, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,
	// fminp Sd, Vn.2S
	0b01111110, 0b10110000, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,
	// fminp Dd, Vn.2D
	0b01111110, 0b11110000, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,
	// fminp Vd.8H, Vn.8H, Vm.8H
	// fminp Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b11000000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fminp Vd.4S, Vn.4S, Vm.4S
	// fminp Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b11110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fminp Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b11110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fminv Hd, Vn.8H
	// fminv Hd, Vn.4H
	0b00001110, 0b10110000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fminv Sd, Vn.4S
	0b00101110, 0b10110000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// fmla Hd, Hn, Vm.H[i]  ································································  (m < 16)
	0b01011111, 0b00000000, 0b00010000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmla Sd, Sn, Vm.S[i]
	0b01011111, 0b10000000, 0b00010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// fmla Dd, Dn, Vm.D[i]
	0b01011111, 0b11000000, 0b00010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 1,
	// fmla Vd.8H, Vn.8H, Vm.H[i]  ··························································  (m < 16)
	// fmla Vd.4H, Vn.4H, Vm.H[i]  ··························································  (m < 16)
	0b00001111, 0b00000000, 0b00010000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// fmla Vd.4S, Vn.4S, Vm.S[i]
	// fmla Vd.2S, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b00010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// fmla Vd.2D, Vn.2D, Vm.D[i]
	0b00001111, 0b11000000, 0b00010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 1, CmdRwidth30,
	// fmla Vd.8H, Vn.8H, Vm.8H
	// fmla Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmla Vd.4S, Vn.4S, Vm.4S
	// fmla Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b00100000, 0b11001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmla Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b01100000, 0b11001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fmlal Vd.2S, Vn.2H, Vm.H[i]  ·························································  (m < 16)
	0b00001111, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmlal Vd.4S, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b01001111, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmlal Vd.2S, Vn.2H, Vm.2H
	0b00001110, 0b00100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmlal Vd.4S, Vn.4H, Vm.4H
	0b01001110, 0b00100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fmlal2 Vd.2S, Vn.2H, Vm.H[i]  ························································  (m < 16)
	0b00101111, 0b10000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmlal2 Vd.4S, Vn.4H, Vm.H[i]  ························································  (m < 16)
	0b01101111, 0b10000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmlal2 Vd.2S, Vn.2H, Vm.2H
	0b00101110, 0b00100000, 0b11001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmlal2 Vd.4S, Vn.4H, Vm.4H
	0b01101110, 0b00100000, 0b11001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fmls Hd, Hn, Vm.H[i]  ································································  (m < 16)
	0b01011111, 0b00000000, 0b01010000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmls Sd, Sn, Vm.S[i]
	0b01011111, 0b10000000, 0b01010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// fmls Dd, Dn, Vm.D[i]
	0b01011111, 0b11000000, 0b01010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 1,
	// fmls Vd.8H, Vn.8H, Vm.H[i]  ··························································  (m < 16)
	// fmls Vd.4H, Vn.4H, Vm.H[i]  ··························································  (m < 16)
	0b00001111, 0b00000000, 0b01010000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// fmls Vd.4S, Vn.4S, Vm.S[i]
	// fmls Vd.2S, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b01010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// fmls Vd.2D, Vn.2D, Vm.D[i]
	0b00001111, 0b11000000, 0b01010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 1, CmdRwidth30,
	// fmls Vd.8H, Vn.8H, Vm.8H
	// fmls Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b11000000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmls Vd.4S, Vn.4S, Vm.4S
	// fmls Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b11001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmls Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b11001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fmlsl Vd.2S, Vn.2H, Vm.H[i]  ·························································  (m < 16)
	0b00001111, 0b10000000, 0b01000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmlsl Vd.4S, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b01001111, 0b10000000, 0b01000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmlsl Vd.2S, Vn.2H, Vm.2H
	0b00001110, 0b10100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmlsl Vd.4S, Vn.4H, Vm.4H
	0b01001110, 0b10100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fmlsl2 Vd.2S, Vn.2H, Vm.H[i]  ························································  (m < 16)
	0b00101111, 0b10000000, 0b11000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmlsl2 Vd.4S, Vn.4H, Vm.H[i]  ························································  (m < 16)
	0b01101111, 0b10000000, 0b11000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmlsl2 Vd.2S, Vn.2H, Vm.2H
	0b00101110, 0b10100000, 0b11001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmlsl2 Vd.4S, Vn.4H, Vm.4H
	0b01101110, 0b10100000, 0b11001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fmov Vd.8H, #imm  ························································  (imm is split float)
	// fmov Vd.4H, #imm  ························································  (imm is split float)
	0b00001111, 0b00000000, 0b11111100, 0b00000000, 3, CmdR0, CmdSpecial, 5, SpecialImmFloatSplit, CmdRwidth30,
	// fmov Vd.4S, #imm  ························································  (imm is split float)
	// fmov Vd.2S, #imm  ························································  (imm is split float)
	0b00001111, 0b00000000, 0b11110100, 0b00000000, 3, CmdR0, CmdSpecial, 5, SpecialImmFloatSplit, CmdRwidth30,
	// fmov Vd.2D, #imm  ························································  (imm is split float)
	0b01101111, 0b00000000, 0b11110100, 0b00000000, 2, CmdR0, CmdSpecial, 5, SpecialImmFloatSplit,
	// fmov Hd, Hn
	0b00011110, 0b11100000, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Sd, Sn
	0b00011110, 0b00100000, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Dd, Dn
	0b00011110, 0b01100000, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Wd, Hn
	0b00011110, 0b11100110, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Xd, Hn
	0b10011110, 0b11100110, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Hd, Wn
	0b00011110, 0b11100111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Sd, Wn
	0b00011110, 0b00100111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Wd, Sn
	0b00011110, 0b00100110, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Hd, Xn
	0b10011110, 0b11100111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Dd, Xn
	0b10011110, 0b01100111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Vd.D[1], Xn
	0b10011110, 0b10101111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Xd, Dn
	0b10011110, 0b01100110, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Xd, Vn.D[1]
	0b10011110, 0b10101110, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// fmov Hd, #imm  ·································································  (imm is float)
	0b00011110, 0b11100000, 0b00010000, 0b00000000, 2, CmdR0, CmdSpecial, 13, SpecialImmFloat,
	// fmov Sd, #imm  ·································································  (imm is float)
	0b00011110, 0b00100000, 0b00010000, 0b00000000, 2, CmdR0, CmdSpecial, 13, SpecialImmFloat,
	// fmov Dd, #imm  ·································································  (imm is float)
	0b00011110, 0b01100000, 0b00010000, 0b00000000, 2, CmdR0, CmdSpecial, 13, SpecialImmFloat,

	// fmsub Hd, Hn, Hm, Ha
	0b00011111, 0b11000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// fmsub Sd, Sn, Sm, Sa
	0b00011111, 0b00000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// fmsub Dd, Dn, Dm, Da
	0b00011111, 0b01000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// fmul Hd, Hn, Vm.H[i]  ································································  (m < 16)
	0b01011111, 0b00000000, 0b10010000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmul Sd, Sn, Vm.S[i]
	0b01011111, 0b10000000, 0b10010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// fmul Dd, Dn, Vm.D[i]
	0b01011111, 0b11000000, 0b10010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 1,
	// fmul Vd.8H, Vn.8H, Vm.H[i]  ··························································  (m < 16)
	// fmul Vd.4H, Vn.4H, Vm.H[i]  ··························································  (m < 16)
	0b00001111, 0b00000000, 0b10010000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// fmul Vd.4S, Vn.4S, Vm.S[i]
	// fmul Vd.2S, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b10010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// fmul Vd.2D, Vn.2D, Vm.D[i]
	0b00001111, 0b11000000, 0b10010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 1, CmdRwidth30,
	// fmul Vd.8H, Vn.8H, Vm.8H
	// fmul Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmul Vd.4S, Vn.4S, Vm.4S
	// fmul Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b00100000, 0b11011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmul Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b01100000, 0b11011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmul Hd, Hn, Hm
	0b00011110, 0b11100000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmul Sd, Sn, Sm
	0b00011110, 0b00100000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmul Dd, Dn, Dm
	0b00011110, 0b01100000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// fmulx Hd, Hn, Vm.H[i]  ·······························································  (m < 16)
	0b01111111, 0b00000000, 0b10010000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// fmulx Sd, Sn, Vm.S[i]
	0b01111111, 0b10000000, 0b10010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// fmulx Dd, Dn, Vm.D[i]
	0b01111111, 0b11000000, 0b10010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 1,
	// fmulx Vd.8H, Vn.8H, Vm.H[i]  ·························································  (m < 16)
	// fmulx Vd.4H, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b00101111, 0b00000000, 0b10010000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// fmulx Vd.4S, Vn.4S, Vm.S[i]
	// fmulx Vd.2S, Vn.2S, Vm.S[i]
	0b00101111, 0b10000000, 0b10010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// fmulx Vd.2D, Vn.2D, Vm.D[i]
	0b00101111, 0b11000000, 0b10010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 1, CmdRwidth30,
	// fmulx Hd, Hn, Hm
	0b01011110, 0b01000000, 0b00011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmulx Sd, Sn, Sm
	0b01011110, 0b00100000, 0b11011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmulx Dd, Dn, Dm
	0b01011110, 0b01100000, 0b11011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fmulx Vd.8H, Vn.8H, Vm.8H
	// fmulx Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmulx Vd.4S, Vn.4S, Vm.4S
	// fmulx Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b00100000, 0b11011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fmulx Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b01100000, 0b11011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fneg Vd.8H, Vn.8H
	// fneg Vd.4H, Vn.4H
	0b00101110, 0b11111000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fneg Vd.4S, Vn.4S
	// fneg Vd.2S, Vn.2S
	0b00101110, 0b10100000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fneg Vd.2D, Vn.2D
	0b00101110, 0b11100000, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fneg Hd, Hn
	0b00011110, 0b11100001, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// fneg Sd, Sn
	0b00011110, 0b00100001, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// fneg Dd, Dn
	0b00011110, 0b01100001, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,

	// fnmadd Hd, Hn, Hm, Ha
	0b00011111, 0b11100000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// fnmadd Sd, Sn, Sm, Sa
	0b00011111, 0b00100000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// fnmadd Dd, Dn, Dm, Da
	0b00011111, 0b01100000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// fnmsub Hd, Hn, Hm, Ha
	0b00011111, 0b11100000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// fnmsub Sd, Sn, Sm, Sa
	0b00011111, 0b00100000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// fnmsub Dd, Dn, Dm, Da
	0b00011111, 0b01100000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// fnmul Hd, Hn, Hm
	0b00011110, 0b11100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fnmul Sd, Sn, Sm
	0b00011110, 0b00100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fnmul Dd, Dn, Dm
	0b00011110, 0b01100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// frecpe Hd, Hn
	0b01011110, 0b11111001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// frecpe Sd, Sn
	0b01011110, 0b10100001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// frecpe Dd, Dn
	0b01011110, 0b11100001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// frecpe Vd.8H, Vn.8H
	// frecpe Vd.4H, Vn.4H
	0b00001110, 0b11111001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frecpe Vd.4S, Vn.4S
	// frecpe Vd.2S, Vn.2S
	0b00001110, 0b10100001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frecpe Vd.2D, Vn.2D
	0b00001110, 0b11100001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// frecps Hd, Hn, Hm
	0b01011110, 0b01000000, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// frecps Sd, Sn, Sm
	0b01011110, 0b00100000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// frecps Dd, Dn, Dm
	0b01011110, 0b01100000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// frecps Vd.8H, Vn.8H, Vm.8H
	// frecps Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// frecps Vd.4S, Vn.4S, Vm.4S
	// frecps Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b00100000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// frecps Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b01100000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// frecpx Hd, Hn
	0b01011110, 0b11111001, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,
	// frecpx Sd, Sn
	0b01011110, 0b10100001, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,
	// frecpx Dd, Dn
	0b01011110, 0b11100001, 0b11111000, 0b00000000, 2, CmdR0, CmdR5,

	// frinta Vd.8H, Vn.8H
	// frinta Vd.4H, Vn.4H
	0b00101110, 0b01111001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frinta Vd.4S, Vn.4S
	// frinta Vd.2S, Vn.2S
	0b00101110, 0b00100001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frinta Vd.2D, Vn.2D
	0b00101110, 0b01100001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frinta Hd, Hn
	0b00011110, 0b11100110, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// frinta Sd, Sn
	0b00011110, 0b00100110, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// frinta Dd, Dn
	0b00011110, 0b01100110, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,

	// frinti Vd.8H, Vn.8H
	// frinti Vd.4H, Vn.4H
	0b00101110, 0b11111001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frinti Vd.4S, Vn.4S
	// frinti Vd.2S, Vn.2S
	0b00101110, 0b10100001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frinti Vd.2D, Vn.2D
	0b00101110, 0b11100001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frinti Hd, Hn
	0b00011110, 0b11100111, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// frinti Sd, Sn
	0b00011110, 0b00100111, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// frinti Dd, Dn
	0b00011110, 0b01100111, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,

	// frintm Vd.8H, Vn.8H
	// frintm Vd.4H, Vn.4H
	0b00001110, 0b01111001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintm Vd.4S, Vn.4S
	// frintm Vd.2S, Vn.2S
	0b00001110, 0b00100001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintm Vd.2D, Vn.2D
	0b00001110, 0b01100001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintm Hd, Hn
	0b00011110, 0b11100101, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintm Sd, Sn
	0b00011110, 0b00100101, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintm Dd, Dn
	0b00011110, 0b01100101, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,

	// frintn Vd.8H, Vn.8H
	// frintn Vd.4H, Vn.4H
	0b00001110, 0b01111001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintn Vd.4S, Vn.4S
	// frintn Vd.2S, Vn.2S
	0b00001110, 0b00100001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintn Vd.2D, Vn.2D
	0b00001110, 0b01100001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintn Hd, Hn
	0b00011110, 0b11100100, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintn Sd, Sn
	0b00011110, 0b00100100, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintn Dd, Dn
	0b00011110, 0b01100100, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,

	// frintp Vd.8H, Vn.8H
	// frintp Vd.4H, Vn.4H
	0b00001110, 0b11111001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintp Vd.4S, Vn.4S
	// frintp Vd.2S, Vn.2S
	0b00001110, 0b10100001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintp Vd.2D, Vn.2D
	0b00001110, 0b11100001, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintp Hd, Hn
	0b00011110, 0b11100100, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintp Sd, Sn
	0b00011110, 0b00100100, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintp Dd, Dn
	0b00011110, 0b01100100, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,

	// frintx Vd.8H, Vn.8H
	// frintx Vd.4H, Vn.4H
	0b00101110, 0b01111001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintx Vd.4S, Vn.4S
	// frintx Vd.2S, Vn.2S
	0b00101110, 0b00100001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintx Vd.2D, Vn.2D
	0b00101110, 0b01100001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintx Hd, Hn
	0b00011110, 0b11100111, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintx Sd, Sn
	0b00011110, 0b00100111, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintx Dd, Dn
	0b00011110, 0b01100111, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,

	// frintz Vd.8H, Vn.8H
	// frintz Vd.4H, Vn.4H
	0b00001110, 0b11111001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintz Vd.4S, Vn.4S
	// frintz Vd.2S, Vn.2S
	0b00001110, 0b10100001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintz Vd.2D, Vn.2D
	0b00001110, 0b11100001, 0b10011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frintz Hd, Hn
	0b00011110, 0b11100101, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintz Sd, Sn
	0b00011110, 0b00100101, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// frintz Dd, Dn
	0b00011110, 0b01100101, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,

	// frsqrte Hd, Hn
	0b01111110, 0b11111001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// frsqrte Sd, Sn
	0b01111110, 0b10100001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// frsqrte Dd, Dn
	0b01111110, 0b11100001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// frsqrte Vd.8H, Vn.8H
	// frsqrte Vd.4H, Vn.4H
	0b00101110, 0b11111001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frsqrte Vd.4S, Vn.4S
	// frsqrte Vd.2S, Vn.2S
	0b00101110, 0b10100001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// frsqrte Vd.2D, Vn.2D
	0b00101110, 0b11100001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// frsqrts Hd, Hn, Hm
	0b01011110, 0b11000000, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// frsqrts Sd, Sn, Sm
	0b01011110, 0b10100000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// frsqrts Dd, Dn, Dm
	0b01011110, 0b11100000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// frsqrts Vd.8H, Vn.8H, Vm.8H
	// frsqrts Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b11000000, 0b00111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// frsqrts Vd.4S, Vn.4S, Vm.4S
	// frsqrts Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// frsqrts Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b11111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// fsqrt Vd.8H, Vn.8H
	// fsqrt Vd.4H, Vn.4H
	0b00101110, 0b11111001, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fsqrt Vd.4S, Vn.4S
	// fsqrt Vd.2S, Vn.2S
	0b00101110, 0b10100001, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fsqrt Vd.2D, Vn.2D
	0b00101110, 0b11100001, 0b11111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// fsqrt Hd, Hn
	0b00011110, 0b11100001, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// fsqrt Sd, Sn
	0b00011110, 0b00100001, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// fsqrt Dd, Dn
	0b00011110, 0b01100001, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,

	// fsub Vd.8H, Vn.8H, Vm.8H
	// fsub Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b11000000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fsub Vd.4S, Vn.4S, Vm.4S
	// fsub Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b11010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fsub Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b11010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// fsub Hd, Hn, Hm
	0b00011110, 0b11100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fsub Sd, Sn, Sm
	0b00011110, 0b00100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// fsub Dd, Dn, Dm
	0b00011110, 0b01100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// hint #imm  ···································································  (0 <= imm < 128)
	0b11010101, 0b00000011, 0b00100000, 0b00011111, 1, CmdUbits, 5, 7,

	// hlt #imm  ··································································  (0 <= imm < 65536)
	0b11010100, 0b01000000, 0b00000000, 0b00000000, 1, CmdUbits, 5, 16,

	// hvc #imm  ··································································  (0 <= imm < 65536)
	0b11010100, 0b00000000, 0b00000000, 0b00000010, 1, CmdUbits, 5, 16,

	// ic IVAU, Xn
	0b11010101, 0b00001011, 0b01110101, 0b00100000, 1, CmdR0,
	// ic <symbol>
	0b11010101, 0b00001000, 0b01110000, 0b00011111, 1, CmdLitList, 5, SymICOPS,

	// ins Vd.B[i], Vn.B[i]
	0b01101110, 0b00000001, 0b00000100, 0b00000000, 4, CmdR0, CmdUbits, 17, 4, CmdR5, CmdUbits, 11, 4,
	// ins Vd.H[i], Vn.H[i]
	0b01101110, 0b00000010, 0b00000100, 0b00000000, 4, CmdR0, CmdUbits, 18, 3, CmdR5, CmdUbits, 12, 3,
	// ins Vd.S[i], Vn.S[i]
	0b01101110, 0b00000100, 0b00000100, 0b00000000, 4, CmdR0, CmdUbits, 19, 2, CmdR5, CmdUbits, 13, 2,
	// ins Vd.D[i], Vn.D[i]
	0b01101110, 0b00001000, 0b00000100, 0b00000000, 4, CmdR0, CmdUbits, 20, 1, CmdR5, CmdUbits, 14, 1,
	// ins Vd.B[i], Wn
	0b01001110, 0b00000001, 0b00011100, 0b00000000, 3, CmdR0, CmdUbits, 17, 4, CmdR5,
	// ins Vd.H[i], Wn
	0b01001110, 0b00000010, 0b00011100, 0b00000000, 3, CmdR0, CmdUbits, 18, 3, CmdR5,
	// ins Vd.S[i], Wn
	0b01001110, 0b00000100, 0b00011100, 0b00000000, 3, CmdR0, CmdUbits, 19, 2, CmdR5,
	// ins Vd.D[i], Xn
	0b01001110, 0b00001000, 0b00011100, 0b00000000, 3, CmdR0, CmdUbits, 20, 1, CmdR5,

	// isb SY
	0b11010101, 0b00000011, 0b00111111, 0b11011111, 0,
	// isb #imm  ·····································································  (0 <= imm < 16)
	0b11010101, 0b00000011, 0b00110000, 0b11011111, 1, CmdUbits, 8, 4,
	// isb
	0b11010101, 0b00000011, 0b00111111, 0b11011111, 0,

	// ld1 {Vd.16B * 1}, [Xn|SP]
	// ld1 {Vd.8B * 1}, [Xn|SP]
	0b00001100, 0b01000000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.8H * 1}, [Xn|SP]
	// ld1 {Vd.4H * 1}, [Xn|SP]
	0b00001100, 0b01000000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.4S * 1}, [Xn|SP]
	// ld1 {Vd.2S * 1}, [Xn|SP]
	0b00001100, 0b01000000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.2D * 1}, [Xn|SP]
	// ld1 {Vd.1D * 1}, [Xn|SP]
	0b00001100, 0b01000000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.16B * 2}, [Xn|SP]
	// ld1 {Vd.8B * 2}, [Xn|SP]
	0b00001100, 0b01000000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.8H * 2}, [Xn|SP]
	// ld1 {Vd.4H * 2}, [Xn|SP]
	0b00001100, 0b01000000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.4S * 2}, [Xn|SP]
	// ld1 {Vd.2S * 2}, [Xn|SP]
	0b00001100, 0b01000000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.2D * 2}, [Xn|SP]
	// ld1 {Vd.1D * 2}, [Xn|SP]
	0b00001100, 0b01000000, 0b10101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.16B * 3}, [Xn|SP]
	// ld1 {Vd.8B * 3}, [Xn|SP]
	0b00001100, 0b01000000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.8H * 3}, [Xn|SP]
	// ld1 {Vd.4H * 3}, [Xn|SP]
	0b00001100, 0b01000000, 0b01100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.4S * 3}, [Xn|SP]
	// ld1 {Vd.2S * 3}, [Xn|SP]
	0b00001100, 0b01000000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.2D * 3}, [Xn|SP]
	// ld1 {Vd.1D * 3}, [Xn|SP]
	0b00001100, 0b01000000, 0b01101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.16B * 4}, [Xn|SP]
	// ld1 {Vd.8B * 4}, [Xn|SP]
	0b00001100, 0b01000000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.8H * 4}, [Xn|SP]
	// ld1 {Vd.4H * 4}, [Xn|SP]
	0b00001100, 0b01000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.4S * 4}, [Xn|SP]
	// ld1 {Vd.2S * 4}, [Xn|SP]
	0b00001100, 0b01000000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.2D * 4}, [Xn|SP]
	// ld1 {Vd.1D * 4}, [Xn|SP]
	0b00001100, 0b01000000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1 {Vd.8B * 1}, [Xn|SP], #8
	0b00001100, 0b11011111, 0b01110000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.4H * 1}, [Xn|SP], #8
	0b00001100, 0b11011111, 0b01110100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.2S * 1}, [Xn|SP], #8
	0b00001100, 0b11011111, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.1D * 1}, [Xn|SP], #8
	0b00001100, 0b11011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.16B * 1}, [Xn|SP], #16
	0b01001100, 0b11011111, 0b01110000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.8H * 1}, [Xn|SP], #16
	0b01001100, 0b11011111, 0b01110100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.4S * 1}, [Xn|SP], #16
	0b01001100, 0b11011111, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.2D * 1}, [Xn|SP], #16
	0b01001100, 0b11011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.16B * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld1 {Vd.8B * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.8H * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.4H * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.4S * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.2S * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01111000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.2D * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.1D * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01111100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.8B * 2}, [Xn|SP], #16
	0b00001100, 0b11011111, 0b10100000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.4H * 2}, [Xn|SP], #16
	0b00001100, 0b11011111, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.2S * 2}, [Xn|SP], #16
	0b00001100, 0b11011111, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.1D * 2}, [Xn|SP], #16
	0b00001100, 0b11011111, 0b10101100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.16B * 2}, [Xn|SP], #32
	0b01001100, 0b11011111, 0b10100000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.8H * 2}, [Xn|SP], #32
	0b01001100, 0b11011111, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.4S * 2}, [Xn|SP], #32
	0b01001100, 0b11011111, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.2D * 2}, [Xn|SP], #32
	0b01001100, 0b11011111, 0b10101100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.16B * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld1 {Vd.8B * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.8H * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.4H * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b10100100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.4S * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.2S * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b10101000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.2D * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.1D * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b10101100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.8B * 3}, [Xn|SP], #24
	0b00001100, 0b11011111, 0b01100000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.4H * 3}, [Xn|SP], #24
	0b00001100, 0b11011111, 0b01100100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.2S * 3}, [Xn|SP], #24
	0b00001100, 0b11011111, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.1D * 3}, [Xn|SP], #24
	0b00001100, 0b11011111, 0b01101100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.16B * 3}, [Xn|SP], #48
	0b01001100, 0b11011111, 0b01100000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.8H * 3}, [Xn|SP], #48
	0b01001100, 0b11011111, 0b01100100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.4S * 3}, [Xn|SP], #48
	0b01001100, 0b11011111, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.2D * 3}, [Xn|SP], #48
	0b01001100, 0b11011111, 0b01101100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.16B * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld1 {Vd.8B * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.8H * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.4H * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.4S * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.2S * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01101000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.2D * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.1D * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01101100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.8B * 4}, [Xn|SP], #32
	0b00001100, 0b11011111, 0b00100000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.4H * 4}, [Xn|SP], #32
	0b00001100, 0b11011111, 0b00100100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.2S * 4}, [Xn|SP], #32
	0b00001100, 0b11011111, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.1D * 4}, [Xn|SP], #32
	0b00001100, 0b11011111, 0b00101100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.16B * 4}, [Xn|SP], #64
	0b01001100, 0b11011111, 0b00100000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.8H * 4}, [Xn|SP], #64
	0b01001100, 0b11011111, 0b00100100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.4S * 4}, [Xn|SP], #64
	0b01001100, 0b11011111, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.2D * 4}, [Xn|SP], #64
	0b01001100, 0b11011111, 0b00101100, 0b00000000, 2, CmdR0, CmdR5,
	// ld1 {Vd.16B * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld1 {Vd.8B * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.8H * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.4H * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.4S * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.2S * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b00101000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.2D * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld1 {Vd.1D * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1 {Vd.B * 1}[i], [Xn|SP]
	0b00001101, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// ld1 {Vd.H * 1}[i], [Xn|SP]
	0b00001101, 0b01000000, 0b01000000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// ld1 {Vd.S * 1}[i], [Xn|SP]
	0b00001101, 0b01000000, 0b10000000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// ld1 {Vd.D * 1}[i], [Xn|SP]
	0b00001101, 0b01000000, 0b10000100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// ld1 {Vd.B * 1}[i], [Xn|SP], #1
	0b00001101, 0b11011111, 0b00000000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// ld1 {Vd.B * 1}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdUfields30, 4, CmdR5, CmdRNz16,
	// ld1 {Vd.H * 1}[i], [Xn|SP], #2
	0b00001101, 0b11011111, 0b01000000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// ld1 {Vd.H * 1}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11000000, 0b01000000, 0b00000000, 4, CmdR0, CmdUfields30, 3, CmdR5, CmdRNz16,
	// ld1 {Vd.S * 1}[i], [Xn|SP], #4
	0b00001101, 0b11011111, 0b10000000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// ld1 {Vd.S * 1}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11000000, 0b10000000, 0b00000000, 4, CmdR0, CmdUfields30, 2, CmdR5, CmdRNz16,
	// ld1 {Vd.D * 1}[i], [Xn|SP], #8
	0b00001101, 0b11011111, 0b10000100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// ld1 {Vd.D * 1}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11000000, 0b10000100, 0b00000000, 4, CmdR0, CmdUfields30, 1, CmdR5, CmdRNz16,

	// ld1r {Vd.16B * 1}, [Xn|SP]
	// ld1r {Vd.8B * 1}, [Xn|SP]
	0b00001101, 0b01000000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1r {Vd.8H * 1}, [Xn|SP]
	// ld1r {Vd.4H * 1}, [Xn|SP]
	0b00001101, 0b01000000, 0b11000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1r {Vd.4S * 1}, [Xn|SP]
	// ld1r {Vd.2S * 1}, [Xn|SP]
	0b00001101, 0b01000000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1r {Vd.2D * 1}, [Xn|SP]
	// ld1r {Vd.1D * 1}, [Xn|SP]
	0b00001101, 0b01000000, 0b11001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1r {Vd.16B * 1}, [Xn|SP], #1
	// ld1r {Vd.8B * 1}, [Xn|SP], #1
	0b00001101, 0b11011111, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1r {Vd.8H * 1}, [Xn|SP], #2
	// ld1r {Vd.4H * 1}, [Xn|SP], #2
	0b00001101, 0b11011111, 0b11000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1r {Vd.4S * 1}, [Xn|SP], #4
	// ld1r {Vd.2S * 1}, [Xn|SP], #4
	0b00001101, 0b11011111, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1r {Vd.2D * 1}, [Xn|SP], #8
	// ld1r {Vd.1D * 1}, [Xn|SP], #8
	0b00001101, 0b11011111, 0b11001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld1r {Vd.16B * 1}, [Xn|SP], Xm  ·····················································  (m != 31)
	// ld1r {Vd.8B * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11000000, 0b11000000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1r {Vd.8H * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld1r {Vd.4H * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11000000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1r {Vd.4S * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld1r {Vd.2S * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11000000, 0b11001000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld1r {Vd.2D * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld1r {Vd.1D * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11000000, 0b11001100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,

	// ld2 {Vd.16B * 2}, [Xn|SP]
	// ld2 {Vd.8B * 2}, [Xn|SP]
	0b00001100, 0b01000000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2 {Vd.8H * 2}, [Xn|SP]
	// ld2 {Vd.4H * 2}, [Xn|SP]
	0b00001100, 0b01000000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2 {Vd.4S * 2}, [Xn|SP]
	// ld2 {Vd.2S * 2}, [Xn|SP]
	0b00001100, 0b01000000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2 {Vd.2D * 2}, [Xn|SP]
	0b00001100, 0b01000000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2 {Vd.8B * 2}, [Xn|SP], #16
	0b00001100, 0b11011111, 0b10000000, 0b00000000, 2, CmdR0, CmdR5,
	// ld2 {Vd.4H * 2}, [Xn|SP], #16
	0b00001100, 0b11011111, 0b10000100, 0b00000000, 2, CmdR0, CmdR5,
	// ld2 {Vd.2S * 2}, [Xn|SP], #16
	0b00001100, 0b11011111, 0b10001000, 0b00000000, 2, CmdR0, CmdR5,
	// ld2 {Vd.16B * 2}, [Xn|SP], #32
	0b01001100, 0b11011111, 0b10000000, 0b00000000, 2, CmdR0, CmdR5,
	// ld2 {Vd.8H * 2}, [Xn|SP], #32
	0b01001100, 0b11011111, 0b10000100, 0b00000000, 2, CmdR0, CmdR5,
	// ld2 {Vd.4S * 2}, [Xn|SP], #32
	0b01001100, 0b11011111, 0b10001000, 0b00000000, 2, CmdR0, CmdR5,
	// ld2 {Vd.2D * 2}, [Xn|SP], #32
	0b01001100, 0b11011111, 0b10001100, 0b00000000, 2, CmdR0, CmdR5,
	// ld2 {Vd.16B * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld2 {Vd.8B * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld2 {Vd.8H * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld2 {Vd.4H * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld2 {Vd.4S * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld2 {Vd.2S * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b10001000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld2 {Vd.2D * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld2 {Vd.B * 2}[i], [Xn|SP]
	0b00001101, 0b01100000, 0b00000000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// ld2 {Vd.H * 2}[i], [Xn|SP]
	0b00001101, 0b01100000, 0b01000000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// ld2 {Vd.S * 2}[i], [Xn|SP]
	0b00001101, 0b01100000, 0b10000000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// ld2 {Vd.D * 2}[i], [Xn|SP]
	0b00001101, 0b01100000, 0b10000100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// ld2 {Vd.B * 2}[i], [Xn|SP], #2
	0b00001101, 0b11111111, 0b00000000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// ld2 {Vd.B * 2}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11100000, 0b00000000, 0b00000000, 4, CmdR0, CmdUfields30, 4, CmdR5, CmdRNz16,
	// ld2 {Vd.H * 2}[i], [Xn|SP], #4
	0b00001101, 0b11111111, 0b01000000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// ld2 {Vd.H * 2}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11100000, 0b01000000, 0b00000000, 4, CmdR0, CmdUfields30, 3, CmdR5, CmdRNz16,
	// ld2 {Vd.S * 2}[i], [Xn|SP], #8
	0b00001101, 0b11111111, 0b10000000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// ld2 {Vd.S * 2}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11100000, 0b10000000, 0b00000000, 4, CmdR0, CmdUfields30, 2, CmdR5, CmdRNz16,
	// ld2 {Vd.D * 2}[i], [Xn|SP], #16
	0b00001101, 0b11111111, 0b10000100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// ld2 {Vd.D * 2}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11100000, 0b10000100, 0b00000000, 4, CmdR0, CmdUfields30, 1, CmdR5, CmdRNz16,

	// ld2r {Vd.16B * 2}, [Xn|SP]
	// ld2r {Vd.8B * 2}, [Xn|SP]
	0b00001101, 0b01100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2r {Vd.8H * 2}, [Xn|SP]
	// ld2r {Vd.4H * 2}, [Xn|SP]
	0b00001101, 0b01100000, 0b11000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2r {Vd.4S * 2}, [Xn|SP]
	// ld2r {Vd.2S * 2}, [Xn|SP]
	0b00001101, 0b01100000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2r {Vd.2D * 2}, [Xn|SP]
	// ld2r {Vd.1D * 2}, [Xn|SP]
	0b00001101, 0b01100000, 0b11001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2r {Vd.16B * 2}, [Xn|SP], #2
	// ld2r {Vd.8B * 2}, [Xn|SP], #2
	0b00001101, 0b11111111, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2r {Vd.8H * 2}, [Xn|SP], #4
	// ld2r {Vd.4H * 2}, [Xn|SP], #4
	0b00001101, 0b11111111, 0b11000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2r {Vd.4S * 2}, [Xn|SP], #8
	// ld2r {Vd.2S * 2}, [Xn|SP], #8
	0b00001101, 0b11111111, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2r {Vd.2D * 2}, [Xn|SP], #16
	// ld2r {Vd.1D * 2}, [Xn|SP], #16
	0b00001101, 0b11111111, 0b11001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld2r {Vd.16B * 2}, [Xn|SP], Xm  ·····················································  (m != 31)
	// ld2r {Vd.8B * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11100000, 0b11000000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld2r {Vd.8H * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld2r {Vd.4H * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11100000, 0b11000100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld2r {Vd.4S * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld2r {Vd.2S * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11100000, 0b11001000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld2r {Vd.2D * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld2r {Vd.1D * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11100000, 0b11001100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,

	// ld3 {Vd.16B * 3}, [Xn|SP]
	// ld3 {Vd.8B * 3}, [Xn|SP]
	0b00001100, 0b01000000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3 {Vd.8H * 3}, [Xn|SP]
	// ld3 {Vd.4H * 3}, [Xn|SP]
	0b00001100, 0b01000000, 0b01000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3 {Vd.4S * 3}, [Xn|SP]
	// ld3 {Vd.2S * 3}, [Xn|SP]
	0b00001100, 0b01000000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3 {Vd.2D * 3}, [Xn|SP]
	0b00001100, 0b01000000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3 {Vd.8B * 3}, [Xn|SP], #24
	0b00001100, 0b11011111, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// ld3 {Vd.4H * 3}, [Xn|SP], #24
	0b00001100, 0b11011111, 0b01000100, 0b00000000, 2, CmdR0, CmdR5,
	// ld3 {Vd.2S * 3}, [Xn|SP], #24
	0b00001100, 0b11011111, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// ld3 {Vd.16B * 3}, [Xn|SP], #48
	0b01001100, 0b11011111, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// ld3 {Vd.8H * 3}, [Xn|SP], #48
	0b01001100, 0b11011111, 0b01000100, 0b00000000, 2, CmdR0, CmdR5,
	// ld3 {Vd.4S * 3}, [Xn|SP], #48
	0b01001100, 0b11011111, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// ld3 {Vd.2D * 3}, [Xn|SP], #48
	0b01001100, 0b11011111, 0b01001100, 0b00000000, 2, CmdR0, CmdR5,
	// ld3 {Vd.16B * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld3 {Vd.8B * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01000000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld3 {Vd.8H * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld3 {Vd.4H * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld3 {Vd.4S * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld3 {Vd.2S * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01001000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld3 {Vd.2D * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld3 {Vd.B * 3}[i], [Xn|SP]
	0b00001101, 0b01000000, 0b00100000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// ld3 {Vd.H * 3}[i], [Xn|SP]
	0b00001101, 0b01000000, 0b01100000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// ld3 {Vd.S * 3}[i], [Xn|SP]
	0b00001101, 0b01000000, 0b10100000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// ld3 {Vd.D * 3}[i], [Xn|SP]
	0b00001101, 0b01000000, 0b10100100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// ld3 {Vd.B * 3}[i], [Xn|SP], #3
	0b00001101, 0b11011111, 0b00100000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// ld3 {Vd.B * 3}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11000000, 0b00100000, 0b00000000, 4, CmdR0, CmdUfields30, 4, CmdR5, CmdRNz16,
	// ld3 {Vd.H * 3}[i], [Xn|SP], #6
	0b00001101, 0b11011111, 0b01100000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// ld3 {Vd.H * 3}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11000000, 0b01100000, 0b00000000, 4, CmdR0, CmdUfields30, 3, CmdR5, CmdRNz16,
	// ld3 {Vd.S * 3}[i], [Xn|SP], #12
	0b00001101, 0b11011111, 0b10100000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// ld3 {Vd.S * 3}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11000000, 0b10100000, 0b00000000, 4, CmdR0, CmdUfields30, 2, CmdR5, CmdRNz16,
	// ld3 {Vd.D * 3}[i], [Xn|SP], #24
	0b00001101, 0b11011111, 0b10100100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// ld3 {Vd.D * 3}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11000000, 0b10100100, 0b00000000, 4, CmdR0, CmdUfields30, 1, CmdR5, CmdRNz16,

	// ld3r {Vd.16B * 3}, [Xn|SP]
	// ld3r {Vd.8B * 3}, [Xn|SP]
	0b00001101, 0b01000000, 0b11100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3r {Vd.8H * 3}, [Xn|SP]
	// ld3r {Vd.4H * 3}, [Xn|SP]
	0b00001101, 0b01000000, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3r {Vd.4S * 3}, [Xn|SP]
	// ld3r {Vd.2S * 3}, [Xn|SP]
	0b00001101, 0b01000000, 0b11101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3r {Vd.2D * 3}, [Xn|SP]
	// ld3r {Vd.1D * 3}, [Xn|SP]
	0b00001101, 0b01000000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3r {Vd.16B * 3}, [Xn|SP], #3
	// ld3r {Vd.8B * 3}, [Xn|SP], #3
	0b00001101, 0b11011111, 0b11100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3r {Vd.8H * 3}, [Xn|SP], #6
	// ld3r {Vd.4H * 3}, [Xn|SP], #6
	0b00001101, 0b11011111, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3r {Vd.4S * 3}, [Xn|SP], #12
	// ld3r {Vd.2S * 3}, [Xn|SP], #12
	0b00001101, 0b11011111, 0b11101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3r {Vd.2D * 3}, [Xn|SP], #24
	// ld3r {Vd.1D * 3}, [Xn|SP], #24
	0b00001101, 0b11011111, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld3r {Vd.16B * 3}, [Xn|SP], Xm  ·····················································  (m != 31)
	// ld3r {Vd.8B * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11000000, 0b11100000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld3r {Vd.8H * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld3r {Vd.4H * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld3r {Vd.4S * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld3r {Vd.2S * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11000000, 0b11101000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld3r {Vd.2D * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld3r {Vd.1D * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11000000, 0b11101100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,

	// ld4 {Vd.16B * 4}, [Xn|SP]
	// ld4 {Vd.8B * 4}, [Xn|SP]
	0b00001100, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4 {Vd.8H * 4}, [Xn|SP]
	// ld4 {Vd.4H * 4}, [Xn|SP]
	0b00001100, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4 {Vd.4S * 4}, [Xn|SP]
	// ld4 {Vd.2S * 4}, [Xn|SP]
	0b00001100, 0b01000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4 {Vd.2D * 4}, [Xn|SP]
	0b00001100, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4 {Vd.8B * 4}, [Xn|SP], #32
	0b00001100, 0b11011111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// ld4 {Vd.4H * 4}, [Xn|SP], #32
	0b00001100, 0b11011111, 0b00000100, 0b00000000, 2, CmdR0, CmdR5,
	// ld4 {Vd.2S * 4}, [Xn|SP], #32
	0b00001100, 0b11011111, 0b00001000, 0b00000000, 2, CmdR0, CmdR5,
	// ld4 {Vd.16B * 4}, [Xn|SP], #64
	0b01001100, 0b11011111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// ld4 {Vd.8H * 4}, [Xn|SP], #64
	0b01001100, 0b11011111, 0b00000100, 0b00000000, 2, CmdR0, CmdR5,
	// ld4 {Vd.4S * 4}, [Xn|SP], #64
	0b01001100, 0b11011111, 0b00001000, 0b00000000, 2, CmdR0, CmdR5,
	// ld4 {Vd.2D * 4}, [Xn|SP], #64
	0b01001100, 0b11011111, 0b00001100, 0b00000000, 2, CmdR0, CmdR5,
	// ld4 {Vd.16B * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld4 {Vd.8B * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld4 {Vd.8H * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld4 {Vd.4H * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld4 {Vd.4S * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// ld4 {Vd.2S * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b00001000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld4 {Vd.2D * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b11000000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld4 {Vd.B * 4}[i], [Xn|SP]
	0b00001101, 0b01100000, 0b00100000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// ld4 {Vd.H * 4}[i], [Xn|SP]
	0b00001101, 0b01100000, 0b01100000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// ld4 {Vd.S * 4}[i], [Xn|SP]
	0b00001101, 0b01100000, 0b10100000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// ld4 {Vd.D * 4}[i], [Xn|SP]
	0b00001101, 0b01100000, 0b10100100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// ld4 {Vd.B * 4}[i], [Xn|SP], #4
	0b00001101, 0b11111111, 0b00100000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// ld4 {Vd.B * 4}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11100000, 0b00100000, 0b00000000, 4, CmdR0, CmdUfields30, 4, CmdR5, CmdRNz16,
	// ld4 {Vd.H * 4}[i], [Xn|SP], #8
	0b00001101, 0b11111111, 0b01100000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// ld4 {Vd.H * 4}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11100000, 0b01100000, 0b00000000, 4, CmdR0, CmdUfields30, 3, CmdR5, CmdRNz16,
	// ld4 {Vd.S * 4}[i], [Xn|SP], #16
	0b00001101, 0b11111111, 0b10100000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// ld4 {Vd.S * 4}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11100000, 0b10100000, 0b00000000, 4, CmdR0, CmdUfields30, 2, CmdR5, CmdRNz16,
	// ld4 {Vd.D * 4}[i], [Xn|SP], #32
	0b00001101, 0b11111111, 0b10100100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// ld4 {Vd.D * 4}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b11100000, 0b10100100, 0b00000000, 4, CmdR0, CmdUfields30, 1, CmdR5, CmdRNz16,

	// ld4r {Vd.16B * 4}, [Xn|SP]
	// ld4r {Vd.8B * 4}, [Xn|SP]
	0b00001101, 0b01100000, 0b11100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4r {Vd.8H * 4}, [Xn|SP]
	// ld4r {Vd.4H * 4}, [Xn|SP]
	0b00001101, 0b01100000, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4r {Vd.4S * 4}, [Xn|SP]
	// ld4r {Vd.2S * 4}, [Xn|SP]
	0b00001101, 0b01100000, 0b11101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4r {Vd.2D * 4}, [Xn|SP]
	// ld4r {Vd.1D * 4}, [Xn|SP]
	0b00001101, 0b01100000, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4r {Vd.16B * 4}, [Xn|SP], #4
	// ld4r {Vd.8B * 4}, [Xn|SP], #4
	0b00001101, 0b11111111, 0b11100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4r {Vd.8H * 4}, [Xn|SP], #8
	// ld4r {Vd.4H * 4}, [Xn|SP], #8
	0b00001101, 0b11111111, 0b11100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4r {Vd.4S * 4}, [Xn|SP], #16
	// ld4r {Vd.2S * 4}, [Xn|SP], #16
	0b00001101, 0b11111111, 0b11101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4r {Vd.2D * 4}, [Xn|SP], #32
	// ld4r {Vd.1D * 4}, [Xn|SP], #32
	0b00001101, 0b11111111, 0b11101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ld4r {Vd.16B * 4}, [Xn|SP], Xm  ·····················································  (m != 31)
	// ld4r {Vd.8B * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11100000, 0b11100000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld4r {Vd.8H * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld4r {Vd.4H * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld4r {Vd.4S * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld4r {Vd.2S * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11100000, 0b11101000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// ld4r {Vd.2D * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	// ld4r {Vd.1D * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	0b00001101, 0b11100000, 0b11101100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,

	// ldadd Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldadd Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldadda Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldadda Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddal Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldaddal Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddalb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddalh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddh Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldaddl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddlb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldaddlh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b00000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldapr Wd, [Xn|SP]
	0b10111000, 0b10111111, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,
	// ldapr Xd, [Xn|SP]
	0b11111000, 0b10111111, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,

	// ldaprb Wd, [Xn|SP]
	0b00111000, 0b10111111, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,

	// ldaprh Wd, [Xn|SP]
	0b01111000, 0b10111111, 0b11000000, 0b00000000, 2, CmdR0, CmdR5,

	// ldapur Wd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b10011001, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldapur Xd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b11011001, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldapurb Wd, [Xn|SP {, #imm }]  ············································  (-256 <= imm < 256)
	0b00011001, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldapurh Wd, [Xn|SP {, #imm }]  ············································  (-256 <= imm < 256)
	0b01011001, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldapursb Wd, [Xn|SP {, #imm }]  ···········································  (-256 <= imm < 256)
	0b00011001, 0b11000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldapursb Xd, [Xn|SP {, #imm }]  ···········································  (-256 <= imm < 256)
	0b00011001, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldapursh Wd, [Xn|SP {, #imm }]  ···········································  (-256 <= imm < 256)
	0b01011001, 0b11000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldapursh Xd, [Xn|SP {, #imm }]  ···········································  (-256 <= imm < 256)
	0b01011001, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldapursw Xd, [Xn|SP {, #imm }]  ···········································  (-256 <= imm < 256)
	0b10011001, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldar Wd, [Xn|SP]
	0b10001000, 0b11011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,
	// ldar Xd, [Xn|SP]
	0b11001000, 0b11011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldarb Wd, [Xn|SP]
	0b00001000, 0b11011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldarh Wd, [Xn|SP]
	0b01001000, 0b11011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldaxp Wd, Wn, [Xm|SP]
	0b10001000, 0b01111111, 0b10000000, 0b00000000, 3, CmdR0, CmdR10, CmdR5,
	// ldaxp Xd, Xn, [Xm|SP]
	0b11001000, 0b01111111, 0b10000000, 0b00000000, 3, CmdR0, CmdR10, CmdR5,

	// ldaxr Wd, [Xn|SP]
	0b10001000, 0b01011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,
	// ldaxr Xd, [Xn|SP]
	0b11001000, 0b01011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldaxrb Wd, [Xn|SP]
	0b00001000, 0b01011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldaxrh Wd, [Xn|SP]
	0b01001000, 0b01011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldclr Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldclr Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclra Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldclra Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclrab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclrah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclral Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldclral Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclralb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclralh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclrb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclrh Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclrl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldclrl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclrlb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldclrlh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b00010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeor Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldeor Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeora Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldeora Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeorab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeorah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeoral Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldeoral Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeoralb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeoralh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeorb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeorh Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeorl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldeorl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeorlb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldeorlh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b00100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldlar Wd, [Xn|SP]
	0b10001000, 0b11011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,
	// ldlar Xd, [Xn|SP]
	0b11001000, 0b11011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldlarb Wd, [Xn|SP]
	0b00001000, 0b11011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldlarh Wd, [Xn|SP]
	0b01001000, 0b11011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldnp Sd, Sn, [Xm|SP {, #imm }]  ·································  (-256 <= imm < 256, imm >> 2)
	0b00101100, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldnp Dd, Dn, [Xm|SP {, #imm }]  ·································  (-512 <= imm < 512, imm >> 3)
	0b01101100, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// ldnp Qd, Qn, [Xm|SP {, #imm }]  ·······························  (-1024 <= imm < 1024, imm >> 4)
	0b10101100, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 4,
	// ldnp Wd, Wn, [Xm|SP {, #imm }]  ·································  (-256 <= imm < 256, imm >> 2)
	0b00101000, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldnp Xd, Xn, [Xm|SP {, #imm }]  ·································  (-512 <= imm < 512, imm >> 3)
	0b10101000, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,

	// ldp Sd, Sn, [Xm|SP], #imm  ······································  (-256 <= imm < 256, imm >> 2)
	0b00101100, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldp Dd, Dn, [Xm|SP], #imm  ······································  (-512 <= imm < 512, imm >> 3)
	0b01101100, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// ldp Qd, Qn, [Xm|SP], #imm  ····································  (-1024 <= imm < 1024, imm >> 4)
	0b10101100, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 4,
	// ldp Sd, Sn, [Xm|SP, #imm]!  ·····································  (-256 <= imm < 256, imm >> 2)
	0b00101101, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldp Dd, Dn, [Xm|SP, #imm]!  ·····································  (-512 <= imm < 512, imm >> 3)
	0b01101101, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// ldp Qd, Qn, [Xm|SP, #imm]!  ···································  (-1024 <= imm < 1024, imm >> 4)
	0b10101101, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 4,
	// ldp Sd, Sn, [Xm|SP {, #imm }]  ··································  (-256 <= imm < 256, imm >> 2)
	0b00101101, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldp Dd, Dn, [Xm|SP {, #imm }]  ··································  (-512 <= imm < 512, imm >> 3)
	0b01101101, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// ldp Qd, Qn, [Xm|SP {, #imm }]  ································  (-1024 <= imm < 1024, imm >> 4)
	0b10101101, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 4,
	// ldp Wd, Wn, [Xm|SP], #imm  ······································  (-256 <= imm < 256, imm >> 2)
	0b00101000, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldp Xd, Xn, [Xm|SP], #imm  ······································  (-512 <= imm < 512, imm >> 3)
	0b10101000, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// ldp Wd, Wn, [Xm|SP, #imm]!  ·····································  (-256 <= imm < 256, imm >> 2)
	0b00101001, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldp Xd, Xn, [Xm|SP, #imm]!  ·····································  (-512 <= imm < 512, imm >> 3)
	0b10101001, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// ldp Wd, Wn, [Xm|SP {, #imm }]  ··································  (-256 <= imm < 256, imm >> 2)
	0b00101001, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldp Xd, Xn, [Xm|SP {, #imm }]  ··································  (-512 <= imm < 512, imm >> 3)
	0b10101001, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,

	// ldpsw Xd, Xn, [Xm|SP], #imm  ····································  (-256 <= imm < 256, imm >> 2)
	0b01101000, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldpsw Xd, Xn, [Xm|SP, #imm]!  ···································  (-256 <= imm < 256, imm >> 2)
	0b01101001, 0b11000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// ldpsw Xd, Xn, [Xm|SP {, #imm }]  ································  (-256 <= imm < 256, imm >> 2)
	0b01101001, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,

	// ldr Bd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b00111100, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Hd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b01111100, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Sd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b10111100, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Dd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b11111100, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Qd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b00111100, 0b11000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Bd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b00111100, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Hd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b01111100, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Sd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b10111100, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Dd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b11111100, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Qd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b00111100, 0b11000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Bd, [Xn|SP {, #imm }]  ··················································  (0 <= imm < 4096)
	0b00111101, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 10, 12,
	// ldr Hd, [Xn|SP {, #imm }]  ········································  (0 <= imm < 8192, imm >> 1)
	0b01111101, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 1,
	// ldr Sd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 16384, imm >> 2)
	0b10111101, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 2,
	// ldr Dd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 32768, imm >> 3)
	0b11111101, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 3,
	// ldr Qd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 65536, imm >> 4)
	0b00111101, 0b11000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 4,
	// ldr Wd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b10111000, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Xd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b11111000, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Wd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b10111000, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Xd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b11111000, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldr Wd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 16384, imm >> 2)
	0b10111001, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 2,
	// ldr Xd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 32768, imm >> 3)
	0b11111001, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 3,
	// ldr Sd, <offset>  ··········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b00011100, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,
	// ldr Dd, <offset>  ··········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b01011100, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,
	// ldr Qd, <offset>  ··········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b10011100, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,
	// ldr Wd, <offset>  ··········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b00011000, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,
	// ldr Xd, <offset>  ··········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b01011000, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,
	// ldr Bd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ·······························  (imm == 0)
	0b00111100, 0b01100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 0,
	// ldr Hd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 1])
	0b01111100, 0b01100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 1,
	// ldr Sd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 2])
	0b10111100, 0b01100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 2,
	// ldr Dd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 3])
	0b11111100, 0b01100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 3,
	// ldr Qd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 4])
	0b00111100, 0b11100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 4,
	// ldr Wd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 2])
	0b10111000, 0b01100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 2,
	// ldr Xd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 3])
	0b11111000, 0b01100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 3,

	// ldraa Xd, [Xn|SP {, #imm }]  ··································  (-4096 <= imm < 4096, imm >> 3)
	0b11111000, 0b00100000, 0b00000100, 0b00000000, 6, CmdR0, CmdR5, CmdChkSscaled, CmdSslice, 12, 9, 3, CmdSslice, 22, 1, 12, CmdAdv,
	// ldraa Xd, [Xn|SP, #imm]!  ·····································  (-4096 <= imm < 4096, imm >> 3)
	0b11111000, 0b00100000, 0b00001100, 0b00000000, 6, CmdR0, CmdR5, CmdChkSscaled, CmdSslice, 12, 9, 3, CmdSslice, 22, 1, 12, CmdAdv,

	// ldrab Xd, [Xn|SP {, #imm }]  ··································  (-4096 <= imm < 4096, imm >> 3)
	0b11111000, 0b10100000, 0b00000100, 0b00000000, 6, CmdR0, CmdR5, CmdChkSscaled, CmdSslice, 12, 9, 3, CmdSslice, 22, 1, 12, CmdAdv,
	// ldrab Xd, [Xn|SP, #imm]!  ·····································  (-4096 <= imm < 4096, imm >> 3)
	0b11111000, 0b10100000, 0b00001100, 0b00000000, 6, CmdR0, CmdR5, CmdChkSscaled, CmdSslice, 12, 9, 3, CmdSslice, 22, 1, 12, CmdAdv,

	// ldrb Wd, [Xn|SP], #imm  ···················································  (-256 <= imm < 256)
	0b00111000, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrb Wd, [Xn|SP, #imm]!  ··················································  (-256 <= imm < 256)
	0b00111000, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrb Wd, [Xn|SP {, #imm }]  ·················································  (0 <= imm < 4096)
	0b00111001, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 10, 12,
	// ldrb Wd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ······························  (imm == 0)
	0b00111000, 0b01100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 0,

	// ldrh Wd, [Xn|SP], #imm  ···················································  (-256 <= imm < 256)
	0b01111000, 0b01000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrh Wd, [Xn|SP, #imm]!  ··················································  (-256 <= imm < 256)
	0b01111000, 0b01000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrh Wd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 8192, imm >> 1)
	0b01111001, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 1,
	// ldrh Wd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ·························  (imm in [0, 1])
	0b01111000, 0b01100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 1,

	// ldrsb Wd, [Xn|SP], #imm  ··················································  (-256 <= imm < 256)
	0b00111000, 0b11000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsb Xd, [Xn|SP], #imm  ··················································  (-256 <= imm < 256)
	0b00111000, 0b10000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsb Wd, [Xn|SP, #imm]!  ·················································  (-256 <= imm < 256)
	0b00111000, 0b11000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsb Xd, [Xn|SP, #imm]!  ·················································  (-256 <= imm < 256)
	0b00111000, 0b10000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsb Wd, [Xn|SP {, #imm }]  ················································  (0 <= imm < 4096)
	0b00111001, 0b11000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 10, 12,
	// ldrsb Xd, [Xn|SP {, #imm }]  ················································  (0 <= imm < 4096)
	0b00111001, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 10, 12,
	// ldrsb Wd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ·····························  (imm == 0)
	0b00111000, 0b11100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 0,
	// ldrsb Xd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ·····························  (imm == 0)
	0b00111000, 0b10100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 0,

	// ldrsh Wd, [Xn|SP], #imm  ··················································  (-256 <= imm < 256)
	0b01111000, 0b11000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsh Xd, [Xn|SP], #imm  ··················································  (-256 <= imm < 256)
	0b01111000, 0b10000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsh Wd, [Xn|SP, #imm]!  ·················································  (-256 <= imm < 256)
	0b01111000, 0b11000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsh Xd, [Xn|SP, #imm]!  ·················································  (-256 <= imm < 256)
	0b01111000, 0b10000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsh Wd, [Xn|SP {, #imm }]  ······································  (0 <= imm < 8192, imm >> 1)
	0b01111001, 0b11000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 1,
	// ldrsh Xd, [Xn|SP {, #imm }]  ······································  (0 <= imm < 8192, imm >> 1)
	0b01111001, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 1,
	// ldrsh Wd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ························  (imm in [0, 1])
	0b01111000, 0b11100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 1,
	// ldrsh Xd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ························  (imm in [0, 1])
	0b01111000, 0b10100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 1,

	// ldrsw Xd, [Xn|SP], #imm  ··················································  (-256 <= imm < 256)
	0b10111000, 0b10000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsw Xd, [Xn|SP, #imm]!  ·················································  (-256 <= imm < 256)
	0b10111000, 0b10000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldrsw Xd, [Xn|SP {, #imm }]  ·····································  (0 <= imm < 16384, imm >> 2)
	0b10111001, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 2,
	// ldrsw Xd, <offset>  ········································  (offset >> 2 is 19-bit (+/- 1 MB))
	0b10011000, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdOffset, RelBCond,
	// ldrsw Xd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ························  (imm in [0, 2])
	0b10111000, 0b10100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 2,

	// ldset Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldset Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldseta Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldseta Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetal Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsetal Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetalb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetalh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldseth Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsetl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetlb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsetlh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b00110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmax Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsmax Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxa Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsmaxa Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxal Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsmaxal Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxalb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxalh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxh Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsmaxl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxlb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmaxlh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b01000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmin Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsmin Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsmina Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsmina Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminal Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsminal Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminalb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminalh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminh Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldsminl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminlb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldsminlh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b01010000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldtr Wd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b10111000, 0b01000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldtr Xd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b11111000, 0b01000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldtrb Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b00111000, 0b01000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldtrh Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b01111000, 0b01000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldtrsb Wd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b00111000, 0b11000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldtrsb Xd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b00111000, 0b10000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldtrsh Wd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b01111000, 0b11000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldtrsh Xd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b01111000, 0b10000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldtrsw Xd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b10111000, 0b10000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldumax Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldumax Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxa Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldumaxa Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxal Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldumaxal Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxalb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxalh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxh Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldumaxl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxlb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumaxlh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b01100000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumin Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldumin Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldumina Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// ldumina Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminal Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// lduminal Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminalb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminalh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminh Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// lduminl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminlb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// lduminlh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b01110000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// ldur Bd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b00111100, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldur Hd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b01111100, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldur Sd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b10111100, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldur Dd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b11111100, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldur Qd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b00111100, 0b11000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldur Wd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b10111000, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldur Xd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b11111000, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldurb Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b00111000, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldurh Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b01111000, 0b01000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldursb Wd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b00111000, 0b11000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldursb Xd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b00111000, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldursh Wd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b01111000, 0b11000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// ldursh Xd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b01111000, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldursw Xd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b10111000, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// ldxp Wd, Wn, [Xm|SP]
	0b10001000, 0b01111111, 0b00000000, 0b00000000, 3, CmdR0, CmdR10, CmdR5,
	// ldxp Xd, Xn, [Xm|SP]
	0b11001000, 0b01111111, 0b00000000, 0b00000000, 3, CmdR0, CmdR10, CmdR5,

	// ldxr Wd, [Xn|SP]
	0b10001000, 0b01011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,
	// ldxr Xd, [Xn|SP]
	0b11001000, 0b01011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldxrb Wd, [Xn|SP]
	0b00001000, 0b01011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// ldxrh Wd, [Xn|SP]
	0b01001000, 0b01011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// lsl Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// lsl Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// lsl Wd, Wn, #imm  ·····························································  (0 <= imm < 32)
	0b01010011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUnegmod, 16, 5, CmdBack, CmdUsub, 10, 5, 31,
	// lsl Xd, Xn, #imm  ·····························································  (0 <= imm < 64)
	0b11010011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUnegmod, 16, 6, CmdBack, CmdUsub, 10, 6, 63,

	// lslv Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// lslv Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// lsr Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// lsr Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// lsr Wd, Wn, #imm  ·····························································  (0 <= imm < 32)
	0b01010011, 0b00000000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,
	// lsr Xd, Xn, #imm  ·····························································  (0 <= imm < 64)
	0b11010011, 0b01000000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 6,

	// lsrv Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// lsrv Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// madd Wd, Wn, Wm, Wa
	0b00011011, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// madd Xd, Xn, Xm, Xa
	0b10011011, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// mla Vd.8H, Vn.8H, Vm.H[i]  ···························································  (m < 16)
	// mla Vd.4H, Vn.4H, Vm.H[i]  ···························································  (m < 16)
	0b00101111, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// mla Vd.4S, Vn.4S, Vm.S[i]
	// mla Vd.2S, Vn.2S, Vm.S[i]
	0b00101111, 0b10000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// mla Vd.16B, Vn.16B, Vm.16B
	// mla Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// mla Vd.8H, Vn.8H, Vm.8H
	// mla Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// mla Vd.4S, Vn.4S, Vm.4S
	// mla Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// mls Vd.8H, Vn.8H, Vm.H[i]  ···························································  (m < 16)
	// mls Vd.4H, Vn.4H, Vm.H[i]  ···························································  (m < 16)
	0b00101111, 0b01000000, 0b01000000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// mls Vd.4S, Vn.4S, Vm.S[i]
	// mls Vd.2S, Vn.2S, Vm.S[i]
	0b00101111, 0b10000000, 0b01000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// mls Vd.16B, Vn.16B, Vm.16B
	// mls Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// mls Vd.8H, Vn.8H, Vm.8H
	// mls Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// mls Vd.4S, Vn.4S, Vm.4S
	// mls Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// mneg Wd, Wn, Wm
	0b00011011, 0b00000000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// mneg Xd, Xn, Xm
	0b10011011, 0b00000000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// mov Wd, Wn
	0b00101010, 0b00000000, 0b00000011, 0b11100000, 2, CmdR0, CmdR16,
	// mov Xd, Xn
	0b10101010, 0b00000000, 0b00000011, 0b11100000, 2, CmdR0, CmdR16,
	// mov Wd|WSP, Wn|WSP
	0b00010001, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// mov Xd|SP, Xn|SP
	0b10010001, 0b00000000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// mov Bd, Vn.B[i]
	0b01011110, 0b00000001, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 17, 4,
	// mov Hd, Vn.H[i]
	0b01011110, 0b00000010, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 18, 3,
	// mov Sd, Vn.S[i]
	0b01011110, 0b00000100, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 19, 2,
	// mov Dd, Vn.D[i]
	0b01011110, 0b00001000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 20, 1,
	// mov Vd.B[i], Vn.B[i]
	0b01101110, 0b00000001, 0b00000100, 0b00000000, 4, CmdR0, CmdUbits, 17, 4, CmdR5, CmdUbits, 11, 4,
	// mov Vd.H[i], Vn.H[i]
	0b01101110, 0b00000010, 0b00000100, 0b00000000, 4, CmdR0, CmdUbits, 18, 3, CmdR5, CmdUbits, 12, 3,
	// mov Vd.S[i], Vn.S[i]
	0b01101110, 0b00000100, 0b00000100, 0b00000000, 4, CmdR0, CmdUbits, 19, 2, CmdR5, CmdUbits, 13, 2,
	// mov Vd.D[i], Vn.D[i]
	0b01101110, 0b00001000, 0b00000100, 0b00000000, 4, CmdR0, CmdUbits, 20, 1, CmdR5, CmdUbits, 14, 1,
	// mov Vd.B[i], Wn
	0b01001110, 0b00000001, 0b00011100, 0b00000000, 3, CmdR0, CmdUbits, 17, 4, CmdR5,
	// mov Vd.H[i], Wn
	0b01001110, 0b00000010, 0b00011100, 0b00000000, 3, CmdR0, CmdUbits, 18, 3, CmdR5,
	// mov Vd.S[i], Wn
	0b01001110, 0b00000100, 0b00011100, 0b00000000, 3, CmdR0, CmdUbits, 19, 2, CmdR5,
	// mov Vd.D[i], Xn
	0b01001110, 0b00001000, 0b00011100, 0b00000000, 3, CmdR0, CmdUbits, 20, 1, CmdR5,
	// mov INVERTED, Wn, #imm  ·········································  (imm is 32-bit inverted wide)
	0b00010010, 0b10000000, 0b00000000, 0b00000000, 2, CmdR0, CmdSpecial, 5, SpecialImmWideInv32,
	// mov INVERTED, Xn, #imm  ·········································  (imm is 64-bit inverted wide)
	0b10010010, 0b10000000, 0b00000000, 0b00000000, 2, CmdR0, CmdSpecial, 5, SpecialImmWideInv64,
	// mov Wd, #imm  ····························································  (imm is 32-bit wide)
	0b01010010, 0b10000000, 0b00000000, 0b00000000, 2, CmdR0, CmdSpecial, 5, SpecialImmWide32,
	// mov Xd, #imm  ····························································  (imm is 64-bit wide)
	0b11010010, 0b10000000, 0b00000000, 0b00000000, 2, CmdR0, CmdSpecial, 5, SpecialImmWide64,
	// mov Vd.16B, Vn.16B
	// mov Vd.8B, Vn.8B
	0b00001110, 0b10100000, 0b00011100, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdRwidth30,
	// mov LOGICAL, Wn|WSP, #imm  ············································  (imm is 32-bit logical)
	0b00110010, 0b00000000, 0b00000011, 0b11100000, 2, CmdR0, CmdSpecial, 10, SpecialImmLogical32,
	// mov LOGICAL, Xn|SP, #imm  ·············································  (imm is 64-bit logical)
	0b10110010, 0b00000000, 0b00000011, 0b11100000, 2, CmdR0, CmdSpecial, 10, SpecialImmLogical64,
	// mov Wd, Vn.S[i]
	0b00001110, 0b00000100, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 19, 2,
	// mov Xd, Vn.D[i]
	0b01001110, 0b00001000, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 20, 1,

	// movi Vd.16B, #imm1 {, LSL #imm2 }  ·······························  (0 <= imm1 < 256, imm2 == 0)
	// movi Vd.8B, #imm1 {, LSL #imm2 }  ································  (0 <= imm1 < 256, imm2 == 0)
	0b00001111, 0b00000000, 0b11100100, 0b00000000, 8, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdChkUbits, 0, CmdAdv, CmdRwidth30,
	// movi Vd.8H, #imm1 {, LSL #imm2 }  ···························  (0 <= imm1 < 256, imm2 in [0, 8])
	// movi Vd.4H, #imm1 {, LSL #imm2 }  ···························  (0 <= imm1 < 256, imm2 in [0, 8])
	0b00001111, 0b00000000, 0b10000100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt2, 13, 5, CmdRwidth30,
	// movi Vd.4S, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 256, imm2 in [0, 8, 16, 24])
	// movi Vd.2S, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 256, imm2 in [0, 8, 16, 24])
	0b00001111, 0b00000000, 0b00000100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt4, 13, 0, CmdRwidth30,
	// movi Vd.4S, #imm1, MSL #imm2  ······························  (0 <= imm1 < 256, imm2 in [8, 16])
	// movi Vd.2S, #imm1, MSL #imm2  ······························  (0 <= imm1 < 256, imm2 in [8, 16])
	0b00001111, 0b00000000, 0b11000100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt2, 12, 8, CmdRwidth30,
	// movi Dd, #imm  ·····························································  (imm is stretched)
	0b00101111, 0b00000000, 0b11100100, 0b00000000, 2, CmdR0, CmdSpecial, 5, SpecialImmStretched,
	// movi Vd.2D, #imm  ··························································  (imm is stretched)
	0b01101111, 0b00000000, 0b11100100, 0b00000000, 2, CmdR0, CmdSpecial, 5, SpecialImmStretched,

	// movk Wd, #imm1 {, LSL #imm2 }  ···························  (0 <= imm1 < 65536, imm2 in [0, 16])
	0b01110010, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUbits, 5, 16, CmdUAlt2, 21, 7,
	// movk Xd, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 65536, imm2 in [0, 16, 32, 48])
	0b11110010, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUbits, 5, 16, CmdUAlt4, 21, 1,

	// movn Wd, #imm1 {, LSL #imm2 }  ···························  (0 <= imm1 < 65536, imm2 in [0, 16])
	0b00010010, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUbits, 5, 16, CmdUAlt2, 21, 7,
	// movn Xd, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 65536, imm2 in [0, 16, 32, 48])
	0b10010010, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUbits, 5, 16, CmdUAlt4, 21, 1,

	// movz Wd, #imm1 {, LSL #imm2 }  ···························  (0 <= imm1 < 65536, imm2 in [0, 16])
	0b01010010, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUbits, 5, 16, CmdUAlt2, 21, 7,
	// movz Xd, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 65536, imm2 in [0, 16, 32, 48])
	0b11010010, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUbits, 5, 16, CmdUAlt4, 21, 1,

	// mrs Xd, #imm  ······························································  (0 <= imm < 32768)
	0b11010101, 0b00110000, 0b00000000, 0b00000000, 2, CmdR0, CmdUbits, 5, 15,

	// msr <symbol>, #imm  ···························································  (0 <= imm < 16)
	0b11010101, 0b00000000, 0b01000000, 0b00011111, 2, CmdLitList, 5, SymMSRIMMOPS, CmdUbits, 8, 4,
	// msr #imm, Xn  ······························································  (0 <= imm < 32768)
	0b11010101, 0b00010000, 0b00000000, 0b00000000, 2, CmdUbits, 5, 15, CmdR0,

	// msub Wd, Wn, Wm, Wa
	0b00011011, 0b00000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,
	// msub Xd, Xn, Xm, Xa
	0b10011011, 0b00000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// mul Vd.8H, Vn.8H, Vm.H[i]  ···························································  (m < 16)
	// mul Vd.4H, Vn.4H, Vm.H[i]  ···························································  (m < 16)
	0b00001111, 0b01000000, 0b10000000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// mul Vd.4S, Vn.4S, Vm.S[i]
	// mul Vd.2S, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b10000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// mul Vd.16B, Vn.16B, Vm.16B
	// mul Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// mul Vd.8H, Vn.8H, Vm.8H
	// mul Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// mul Vd.4S, Vn.4S, Vm.4S
	// mul Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// mul Wd, Wn, Wm
	0b00011011, 0b00000000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// mul Xd, Xn, Xm
	0b10011011, 0b00000000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// mvn Wd, Wn {, LSL|LSR|ASR #imm }  ·············································  (0 <= imm < 32)
	0b00101010, 0b00100000, 0b00000011, 0b11100000, 4, CmdR0, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// mvn Xd, Xn {, LSL|LSR|ASR #imm }  ·············································  (0 <= imm < 64)
	0b10101010, 0b00100000, 0b00000011, 0b11100000, 4, CmdR0, CmdR16, CmdRotates, CmdUbits, 10, 6,
	// mvn Vd.16B, Vn.16B
	// mvn Vd.8B, Vn.8B
	0b00101110, 0b00100000, 0b01011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// mvni Vd.8H, #imm1 {, LSL #imm2 }  ···························  (0 <= imm1 < 256, imm2 in [0, 8])
	// mvni Vd.4H, #imm1 {, LSL #imm2 }  ···························  (0 <= imm1 < 256, imm2 in [0, 8])
	0b00101111, 0b00000000, 0b10000100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt2, 13, 5, CmdRwidth30,
	// mvni Vd.4S, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 256, imm2 in [0, 8, 16, 24])
	// mvni Vd.2S, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 256, imm2 in [0, 8, 16, 24])
	0b00101111, 0b00000000, 0b00000100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt4, 13, 0, CmdRwidth30,
	// mvni Vd.4S, #imm1, MSL #imm2  ······························  (0 <= imm1 < 256, imm2 in [8, 16])
	// mvni Vd.2S, #imm1, MSL #imm2  ······························  (0 <= imm1 < 256, imm2 in [8, 16])
	0b00101111, 0b00000000, 0b11000100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt2, 12, 8, CmdRwidth30,

	// neg Wd, Wn {, LSL|LSR|ASR #imm }  ·············································  (0 <= imm < 32)
	0b01001011, 0b00000000, 0b00000011, 0b11100000, 4, CmdR0, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// neg Xd, Xn {, LSL|LSR|ASR #imm }  ·············································  (0 <= imm < 64)
	0b11001011, 0b00000000, 0b00000011, 0b11100000, 4, CmdR0, CmdR16, CmdRotates, CmdUbits, 10, 6,
	// neg Dd, Dn
	0b01111110, 0b11100000, 0b10111000, 0b00000000, 2, CmdR0, CmdR5,
	// neg Vd.16B, Vn.16B
	// neg Vd.8B, Vn.8B
	0b00101110, 0b00100000, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// neg Vd.8H, Vn.8H
	// neg Vd.4H, Vn.4H
	0b00101110, 0b01100000, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// neg Vd.4S, Vn.4S
	// neg Vd.2S, Vn.2S
	0b00101110, 0b10100000, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// neg Vd.2D, Vn.2D
	0b00101110, 0b11100000, 0b10111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// negs Wd, Wn {, LSL|LSR|ASR #imm }  ············································  (0 <= imm < 32)
	0b01101011, 0b00000000, 0b00000011, 0b11100000, 4, CmdR0, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// negs Xd, Xn {, LSL|LSR|ASR #imm }  ············································  (0 <= imm < 64)
	0b11101011, 0b00000000, 0b00000011, 0b11100000, 4, CmdR0, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// ngc Wd, Wn
	0b01011010, 0b00000000, 0b00000011, 0b11100000, 2, CmdR0, CmdR16,
	// ngc Xd, Xn
	0b11011010, 0b00000000, 0b00000011, 0b11100000, 2, CmdR0, CmdR16,

	// ngcs Wd, Wn
	0b01111010, 0b00000000, 0b00000011, 0b11100000, 2, CmdR0, CmdR16,
	// ngcs Xd, Xn
	0b11111010, 0b00000000, 0b00000011, 0b11100000, 2, CmdR0, CmdR16,

	// nop
	0b11010101, 0b00000011, 0b00100000, 0b00011111, 0,

	// not Vd.16B, Vn.16B
	// not Vd.8B, Vn.8B
	0b00101110, 0b00100000, 0b01011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// orn Vd.16B, Vn.16B, Vm.16B
	// orn Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b11100000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// orn Wd, Wn, Wm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 32)
	0b00101010, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// orn Xd, Xn, Xm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 64)
	0b10101010, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// orr Vd.8H, #imm1 {, LSL #imm2 }  ····························  (0 <= imm1 < 256, imm2 in [0, 8])
	// orr Vd.4H, #imm1 {, LSL #imm2 }  ····························  (0 <= imm1 < 256, imm2 in [0, 8])
	0b00001111, 0b00000000, 0b10010100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt2, 13, 5, CmdRwidth30,
	// orr Vd.4S, #imm1 {, LSL #imm2 }  ····················  (0 <= imm1 < 256, imm2 in [0, 8, 16, 24])
	// orr Vd.2S, #imm1 {, LSL #imm2 }  ····················  (0 <= imm1 < 256, imm2 in [0, 8, 16, 24])
	0b00001111, 0b00000000, 0b00010100, 0b00000000, 7, CmdR0, CmdChkUbits, 8, CmdUslice, 5, 5, 0, CmdUslice, 16, 3, 5, CmdAdv, CmdUAlt4, 13, 0, CmdRwidth30,
	// orr Vd.16B, Vn.16B, Vm.16B
	// orr Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b10100000, 0b00011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// orr Wd|WSP, Wn, #imm  ·················································  (imm is 32-bit logical)
	0b00110010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSpecial, 10, SpecialImmLogical32,
	// orr Xd|SP, Xn, #imm  ··················································  (imm is 64-bit logical)
	0b10110010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSpecial, 10, SpecialImmLogical64,
	// orr Wd, Wn, Wm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 32)
	0b00101010, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// orr Xd, Xn, Xm {, LSL|LSR|ASR|ROR #imm }  ·····································  (0 <= imm < 64)
	0b10101010, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// pacda Xd, Xn|SP
	0b11011010, 0b11000001, 0b00001000, 0b00000000, 2, CmdR0, CmdR5,

	// pacdb Xd, Xn|SP
	0b11011010, 0b11000001, 0b00001100, 0b00000000, 2, CmdR0, CmdR5,

	// pacdza Xd
	0b11011010, 0b11000001, 0b00101011, 0b11100000, 1, CmdR0,

	// pacdzb Xd
	0b11011010, 0b11000001, 0b00101111, 0b11100000, 1, CmdR0,

	// pacga Xd, Xn, Xm|SP
	0b10011010, 0b11000000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// pacia Xd, Xn|SP
	0b11011010, 0b11000001, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// pacia1716
	0b11010101, 0b00000011, 0b00100001, 0b00011111, 0,

	// paciasp
	0b11010101, 0b00000011, 0b00100011, 0b00111111, 0,

	// paciaz
	0b11010101, 0b00000011, 0b00100011, 0b00011111, 0,

	// pacib Xd, Xn|SP
	0b11011010, 0b11000001, 0b00000100, 0b00000000, 2, CmdR0, CmdR5,

	// pacib1716
	0b11010101, 0b00000011, 0b00100001, 0b01011111, 0,

	// pacibsp
	0b11010101, 0b00000011, 0b00100011, 0b01111111, 0,

	// pacibz
	0b11010101, 0b00000011, 0b00100011, 0b01011111, 0,

	// paciza Xd
	0b11011010, 0b11000001, 0b00100011, 0b11100000, 1, CmdR0,

	// pacizb Xd
	0b11011010, 0b11000001, 0b00100111, 0b11100000, 1, CmdR0,

	// pmul Vd.16B, Vn.16B, Vm.16B
	// pmul Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// pmull Vd.8H, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b11100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// pmull Vd.1Q, Vn.1D, Vm.1D
	0b00001110, 0b11100000, 0b11100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// pmull2 Vd.8H, Vn.16B, Vm.16B
	0b01001110, 0b00100000, 0b11100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// pmull2 Vd.1Q, Vn.2D, Vm.2D
	0b01001110, 0b11100000, 0b11100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// prfm #imm, <offset>  ························  (0 <= imm < 32, offset >> 2 is 19-bit (+/- 1 MB))
	0b11011000, 0b00000000, 0b00000000, 0b00000000, 2, CmdUbits, 0, 5, CmdOffset, RelBCond,
	// prfm #imm1, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm2 }]  ····  (0 <= imm1 < 32, imm2 in [0, 3])
	0b11111000, 0b10100000, 0b00001000, 0b00000000, 5, CmdUbits, 0, 5, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 3,

	// prfum #imm1, [Xn|SP {, #imm2 }]  ·························  (0 <= imm1 < 32, -256 <= imm2 < 256)
	0b11111000, 0b10000000, 0b00000000, 0b00000000, 3, CmdUbits, 0, 5, CmdR5, CmdSbits,

	// psb CSYNC
	0b11010101, 0b00000011, 0b00100010, 0b00111111, 0,

	// pssbb
	0b11010101, 0b00000011, 0b00110100, 0b10011111, 0,

	// raddhn Vd.8B, Vn.8H, Vm.8H
	0b00101110, 0b00100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// raddhn Vd.4H, Vn.4S, Vm.4S
	0b00101110, 0b01100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// raddhn Vd.2S, Vn.2D, Vm.2D
	0b00101110, 0b10100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// raddhn2 Vd.16B, Vn.8H, Vm.8H
	0b01101110, 0b00100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// raddhn2 Vd.8H, Vn.4S, Vm.4S
	0b01101110, 0b01100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// raddhn2 Vd.4S, Vn.2D, Vm.2D
	0b01101110, 0b10100000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// rax1 Vd.2D, Vn.2D, Vm.2D
	0b11001110, 0b01100000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// rbit Vd.16B, Vn.16B
	// rbit Vd.8B, Vn.8B
	0b00101110, 0b01100000, 0b01011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// rbit Wd, Wn
	0b01011010, 0b11000000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// rbit Xd, Xn
	0b11011010, 0b11000000, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// ret Xd
	0b11010110, 0b01011111, 0b00000000, 0b00000000, 1, CmdR5,
	// ret
	0b11010110, 0b01011111, 0b00000011, 0b11000000, 0,

	// retaa
	0b11010110, 0b01011111, 0b00001011, 0b11111111, 0,

	// retab
	0b11010110, 0b01011111, 0b00001111, 0b11111111, 0,

	// rev Wd, Wn
	0b01011010, 0b11000000, 0b00001000, 0b00000000, 2, CmdR0, CmdR5,
	// rev Xd, Xn
	0b11011010, 0b11000000, 0b00001100, 0b00000000, 2, CmdR0, CmdR5,

	// rev16 Vd.16B, Vn.16B
	// rev16 Vd.8B, Vn.8B
	0b00001110, 0b00100000, 0b00011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// rev16 Wd, Wn
	0b01011010, 0b11000000, 0b00000100, 0b00000000, 2, CmdR0, CmdR5,
	// rev16 Xd, Xn
	0b11011010, 0b11000000, 0b00000100, 0b00000000, 2, CmdR0, CmdR5,

	// rev32 Vd.16B, Vn.16B
	// rev32 Vd.8B, Vn.8B
	0b00101110, 0b00100000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// rev32 Vd.8H, Vn.8H
	// rev32 Vd.4H, Vn.4H
	0b00101110, 0b01100000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// rev32 Xd, Xn
	0b11011010, 0b11000000, 0b00001000, 0b00000000, 2, CmdR0, CmdR5,

	// rev64 Vd.16B, Vn.16B
	// rev64 Vd.8B, Vn.8B
	0b00001110, 0b00100000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// rev64 Vd.8H, Vn.8H
	// rev64 Vd.4H, Vn.4H
	0b00001110, 0b01100000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// rev64 Vd.4S, Vn.4S
	// rev64 Vd.2S, Vn.2S
	0b00001110, 0b10100000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// rev64 Xd, Xn
	0b11011010, 0b11000000, 0b00001100, 0b00000000, 2, CmdR0, CmdR5,

	// rmif Xd, #imm1, #imm2  ·······································  (0 <= imm1 < 64, 0 <= imm2 < 16)
	0b10111010, 0b00000000, 0b00000100, 0b00000000, 3, CmdR5, CmdUbits, 15, 6, CmdUbits, 0, 4,

	// ror Wd, Wn, #imm  ·····························································  (0 <= imm < 32)
	0b00010011, 0b10000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdUbits, 10, 5,
	// ror Xd, Xn, #imm  ·····························································  (0 <= imm < 64)
	0b10010011, 0b11000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdBack, CmdR16, CmdUbits, 10, 6,
	// ror Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ror Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// rorv Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// rorv Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// rshrn Vd.8B, Vn.8H, #imm  ······················································  (0 < imm <= 8)
	0b00001111, 0b00001000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// rshrn Vd.4H, Vn.4S, #imm  ·····················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// rshrn Vd.2S, Vn.2D, #imm  ·····················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// rshrn2 Vd.16B, Vn.8H, #imm  ····················································  (0 < imm <= 8)
	0b01001111, 0b00001000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// rshrn2 Vd.8H, Vn.4S, #imm  ····················································  (0 < imm <= 16)
	0b01001111, 0b00010000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// rshrn2 Vd.4S, Vn.2D, #imm  ····················································  (0 < imm <= 32)
	0b01001111, 0b00100000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// rsubhn Vd.8B, Vn.8H, Vm.8H
	0b00101110, 0b00100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// rsubhn Vd.4H, Vn.4S, Vm.4S
	0b00101110, 0b01100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// rsubhn Vd.2S, Vn.2D, Vm.2D
	0b00101110, 0b10100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// rsubhn2 Vd.16B, Vn.8H, Vm.8H
	0b01101110, 0b00100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// rsubhn2 Vd.8H, Vn.4S, Vm.4S
	0b01101110, 0b01100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// rsubhn2 Vd.4S, Vn.2D, Vm.2D
	0b01101110, 0b10100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// saba Vd.16B, Vn.16B, Vm.16B
	// saba Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// saba Vd.8H, Vn.8H, Vm.8H
	// saba Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// saba Vd.4S, Vn.4S, Vm.4S
	// saba Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sabal Vd.8H, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sabal Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sabal Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sabal2 Vd.8H, Vn.16B, Vm.16B
	0b01001110, 0b00100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sabal2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sabal2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sabd Vd.16B, Vn.16B, Vm.16B
	// sabd Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sabd Vd.8H, Vn.8H, Vm.8H
	// sabd Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sabd Vd.4S, Vn.4S, Vm.4S
	// sabd Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sabdl Vd.8H, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sabdl Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sabdl Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sabdl2 Vd.8H, Vn.16B, Vm.16B
	0b01001110, 0b00100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sabdl2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sabdl2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sadalp Vd.8H, Vn.16B
	// sadalp Vd.4H, Vn.8B
	0b00001110, 0b00100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sadalp Vd.4S, Vn.8H
	// sadalp Vd.2S, Vn.4H
	0b00001110, 0b01100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sadalp Vd.2D, Vn.4S
	// sadalp Vd.1D, Vn.2S
	0b00001110, 0b10100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// saddl Vd.8H, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// saddl Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// saddl Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// saddl2 Vd.8H, Vn.16B, Vm.16B
	0b01001110, 0b00100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// saddl2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// saddl2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// saddlp Vd.8H, Vn.16B
	// saddlp Vd.4H, Vn.8B
	0b00001110, 0b00100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// saddlp Vd.4S, Vn.8H
	// saddlp Vd.2S, Vn.4H
	0b00001110, 0b01100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// saddlp Vd.2D, Vn.4S
	// saddlp Vd.1D, Vn.2S
	0b00001110, 0b10100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// saddlv Hd, Vn.16B
	// saddlv Hd, Vn.8B
	0b00001110, 0b00110000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// saddlv Sd, Vn.8H
	// saddlv Sd, Vn.4H
	0b00001110, 0b01110000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// saddlv Dd, Vn.4S
	0b00001110, 0b10110000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// saddw Vd.8H, Vn.8H, Vm.8B
	0b00001110, 0b00100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// saddw Vd.4S, Vn.4S, Vm.4H
	0b00001110, 0b01100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// saddw Vd.2D, Vn.2D, Vm.2S
	0b00001110, 0b10100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// saddw2 Vd.8H, Vn.8H, Vm.16B
	0b01001110, 0b00100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// saddw2 Vd.4S, Vn.4S, Vm.8H
	0b01001110, 0b01100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// saddw2 Vd.2D, Vn.2D, Vm.4S
	0b01001110, 0b10100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sb
	0b11010101, 0b00000011, 0b00110000, 0b11111111, 0,

	// sbc Wd, Wn, Wm
	0b01011010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sbc Xd, Xn, Xm
	0b11011010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sbcs Wd, Wn, Wm
	0b01111010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sbcs Xd, Xn, Xm
	0b11111010, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sbfiz Wd, Wn, #imm1, #imm2  ···············  (0 <= imm1 < 32, 0 < imm2 <= 32, imm1 + imm2 <= 32)
	0b00010011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUnegmod, 16, 5, CmdChkUsum, 5, CmdUrange, 10, 1, 32,
	// sbfiz Xd, Xn, #imm1, #imm2  ···············  (0 <= imm1 < 64, 0 < imm2 <= 64, imm1 + imm2 <= 64)
	0b10010011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUnegmod, 16, 6, CmdChkUsum, 6, CmdUrange, 10, 1, 64,

	// sbfm Wd, Wn, #imm1, #imm2  ···································  (0 <= imm1 < 32, 0 <= imm2 < 32)
	0b00010011, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 5, CmdUbits, 10, 5,
	// sbfm Xd, Xn, #imm1, #imm2  ·················  (0 <= imm1 < 64, 0 < imm2 < 64, imm1 + imm2 <= 64)
	0b10010011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 6, CmdChkUsum, 6, CmdUbits, 10, 6,

	// sbfx Wd, Wn, #imm1, #imm2  ················  (0 <= imm1 < 32, 0 < imm2 <= 32, imm1 + imm2 <= 32)
	0b00010011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 5, CmdChkUsum, 5, CmdUsumdec, 10, 5,
	// sbfx Xd, Xn, #imm1, #imm2  ················  (0 <= imm1 < 64, 0 < imm2 <= 64, imm1 + imm2 <= 64)
	0b10010011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 6, CmdChkUsum, 6, CmdUsumdec, 10, 6,

	// scvtf Hd, Hn, #imm  ···························································  (0 < imm <= 16)
	0b01011111, 0b00000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// scvtf Sd, Sn, #imm  ···························································  (0 < imm <= 32)
	0b01011111, 0b00000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// scvtf Dd, Dn, #imm  ···························································  (0 < imm <= 64)
	0b01011111, 0b00000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// scvtf Vd.8H, Vn.8H, #imm  ·····················································  (0 < imm <= 16)
	// scvtf Vd.4H, Vn.4H, #imm  ·····················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// scvtf Vd.4S, Vn.4S, #imm  ·····················································  (0 < imm <= 32)
	// scvtf Vd.2S, Vn.2S, #imm  ·····················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// scvtf Vd.2D, Vn.2D, #imm  ·····················································  (0 < imm <= 64)
	0b00001111, 0b01000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,
	// scvtf Hd, Hn
	0b01011110, 0b01111001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// scvtf Sd, Sn
	0b01011110, 0b00100001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// scvtf Dd, Dn
	0b01011110, 0b01100001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// scvtf Vd.8H, Vn.8H
	// scvtf Vd.4H, Vn.4H
	0b00001110, 0b01111001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// scvtf Vd.4S, Vn.4S
	// scvtf Vd.2S, Vn.2S
	0b00001110, 0b00100001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// scvtf Vd.2D, Vn.2D
	0b00001110, 0b01100001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// scvtf Hd, Wn, #imm  ···························································  (0 < imm <= 32)
	0b00011110, 0b11000010, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// scvtf Sd, Wn, #imm  ···························································  (0 < imm <= 32)
	0b00011110, 0b00000010, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// scvtf Dd, Wn, #imm  ···························································  (0 < imm <= 32)
	0b00011110, 0b01000010, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// scvtf Hd, Xn, #imm  ···························································  (0 < imm <= 64)
	0b10011110, 0b11000010, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// scvtf Sd, Xn, #imm  ···························································  (0 < imm <= 64)
	0b10011110, 0b00000010, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// scvtf Dd, Xn, #imm  ···························································  (0 < imm <= 64)
	0b10011110, 0b01000010, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// scvtf Hd, Wn
	0b00011110, 0b11100010, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// scvtf Sd, Wn
	0b00011110, 0b00100010, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// scvtf Dd, Wn
	0b00011110, 0b01100010, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// scvtf Hd, Xn
	0b10011110, 0b11100010, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// scvtf Sd, Xn
	0b10011110, 0b00100010, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// scvtf Dd, Xn
	0b10011110, 0b01100010, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// sdiv Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sdiv Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sdot Vd.2S, Vn.8B, Vm.4B[i]
	0b00001111, 0b10000000, 0b11100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sdot Vd.4S, Vn.16B, Vm.4B[i]
	0b01001111, 0b10000000, 0b11100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sdot Vd.2S, Vn.8B, Vm.8B
	0b00001110, 0b10000000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sdot Vd.4S, Vn.16B, Vm.16B
	0b01001110, 0b10000000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// setf16 Wd
	0b00111010, 0b00000000, 0b01001000, 0b00001101, 1, CmdR5,

	// setf8 Wd
	0b00111010, 0b00000000, 0b00001000, 0b00001101, 1, CmdR5,

	// sev
	0b11010101, 0b00000011, 0b00100000, 0b10011111, 0,

	// sevl
	0b11010101, 0b00000011, 0b00100000, 0b10111111, 0,

	// sha1c Qd, Sn, Vm.4S
	0b01011110, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha1h Sd, Sn
	0b01011110, 0b00101000, 0b00001000, 0b00000000, 2, CmdR0, CmdR5,

	// sha1m Qd, Sn, Vm.4S
	0b01011110, 0b00000000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha1p Qd, Sn, Vm.4S
	0b01011110, 0b00000000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha1su0 Vd.4S, Vn.4S, Vm.4S
	0b01011110, 0b00000000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha1su1 Vd.4S, Vn.4S
	0b01011110, 0b00101000, 0b00011000, 0b00000000, 2, CmdR0, CmdR5,

	// sha256h Qd, Qn, Vm.4S
	0b01011110, 0b00000000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha256h2 Qd, Qn, Vm.4S
	0b01011110, 0b00000000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha256su0 Vd.4S, Vn.4S
	0b01011110, 0b00101000, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,

	// sha256su1 Vd.4S, Vn.4S, Vm.4S
	0b01011110, 0b00000000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha512h Qd, Qn, Vm.2D
	0b11001110, 0b01100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha512h2 Qd, Qn, Vm.2D
	0b11001110, 0b01100000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sha512su0 Vd.2D, Vn.2D
	0b11001110, 0b11000000, 0b10000000, 0b00000000, 2, CmdR0, CmdR5,

	// sha512su1 Vd.2D, Vn.2D, Vm.2D
	0b11001110, 0b01100000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// shadd Vd.16B, Vn.16B, Vm.16B
	// shadd Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// shadd Vd.8H, Vn.8H, Vm.8H
	// shadd Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// shadd Vd.4S, Vn.4S, Vm.4S
	// shadd Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// shl Dd, Dn, #imm  ·····························································  (0 <= imm < 64)
	0b01011111, 0b01000000, 0b01010100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 6,
	// shl Vd.16B, Vn.16B, #imm  ······················································  (0 <= imm < 8)
	// shl Vd.8B, Vn.8B, #imm  ························································  (0 <= imm < 8)
	0b00001111, 0b00001000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 3, CmdRwidth30,
	// shl Vd.8H, Vn.8H, #imm  ·······················································  (0 <= imm < 16)
	// shl Vd.4H, Vn.4H, #imm  ·······················································  (0 <= imm < 16)
	0b00001111, 0b00010000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 4, CmdRwidth30,
	// shl Vd.4S, Vn.4S, #imm  ·······················································  (0 <= imm < 32)
	// shl Vd.2S, Vn.2S, #imm  ·······················································  (0 <= imm < 32)
	0b00001111, 0b00100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 5, CmdRwidth30,
	// shl Vd.2D, Vn.2D, #imm  ·······················································  (0 <= imm < 64)
	0b00001111, 0b01000000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 6, CmdRwidth30,

	// shll Vd.8H, Vn.8B, #8
	0b00101110, 0b00100001, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// shll Vd.4S, Vn.4H, #16
	0b00101110, 0b01100001, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// shll Vd.2D, Vn.2S, #32
	0b00101110, 0b10100001, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,

	// shll2 Vd.8H, Vn.16B, #8
	0b01101110, 0b00100001, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// shll2 Vd.4S, Vn.8H, #16
	0b01101110, 0b01100001, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// shll2 Vd.2D, Vn.4S, #32
	0b01101110, 0b10100001, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,

	// shrn Vd.8B, Vn.8H, #imm  ·······················································  (0 < imm <= 8)
	0b00001111, 0b00001000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// shrn Vd.4H, Vn.4S, #imm  ······················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// shrn Vd.2S, Vn.2D, #imm  ······················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// shrn2 Vd.16B, Vn.8H, #imm  ·····················································  (0 < imm <= 8)
	0b01001111, 0b00001000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// shrn2 Vd.8H, Vn.4S, #imm  ·····················································  (0 < imm <= 16)
	0b01001111, 0b00010000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// shrn2 Vd.4S, Vn.2D, #imm  ·····················································  (0 < imm <= 32)
	0b01001111, 0b00100000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// shsub Vd.16B, Vn.16B, Vm.16B
	// shsub Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// shsub Vd.8H, Vn.8H, Vm.8H
	// shsub Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// shsub Vd.4S, Vn.4S, Vm.4S
	// shsub Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sli Dd, Dn, #imm  ·····························································  (0 <= imm < 64)
	0b01111111, 0b01000000, 0b01010100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 6,
	// sli Vd.16B, Vn.16B, #imm  ······················································  (0 <= imm < 8)
	// sli Vd.8B, Vn.8B, #imm  ························································  (0 <= imm < 8)
	0b00101111, 0b00001000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 3, CmdRwidth30,
	// sli Vd.8H, Vn.8H, #imm  ·······················································  (0 <= imm < 16)
	// sli Vd.4H, Vn.4H, #imm  ·······················································  (0 <= imm < 16)
	0b00101111, 0b00010000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 4, CmdRwidth30,
	// sli Vd.4S, Vn.4S, #imm  ·······················································  (0 <= imm < 32)
	// sli Vd.2S, Vn.2S, #imm  ·······················································  (0 <= imm < 32)
	0b00101111, 0b00100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 5, CmdRwidth30,
	// sli Vd.2D, Vn.2D, #imm  ·······················································  (0 <= imm < 64)
	0b00101111, 0b01000000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 6, CmdRwidth30,

	// sm3partw1 Vd.4S, Vn.4S, Vm.4S
	0b11001110, 0b01100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sm3partw2 Vd.4S, Vn.4S, Vm.4S
	0b11001110, 0b01100000, 0b11000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sm3ss1 Vd.4S, Vn.4S, Vm.4S, Va.4S
	0b11001110, 0b01000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// sm3tt1a Vd.4S, Vn.4S, Vm.S[i]
	0b11001110, 0b01000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 12, 2,

	// sm3tt1b Vd.4S, Vn.4S, Vm.S[i]
	0b11001110, 0b01000000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 12, 2,

	// sm3tt2a Vd.4S, Vn.4S, Vm.S[i]
	0b11001110, 0b01000000, 0b10001000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 12, 2,

	// sm3tt2b Vd.4S, Vn.4S, Vm.S[i]
	0b11001110, 0b01000000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 12, 2,

	// sm4e Vd.4S, Vn.4S
	0b11001110, 0b11000000, 0b10000100, 0b00000000, 2, CmdR0, CmdR5,

	// sm4ekey Vd.4S, Vn.4S, Vm.4S
	0b11001110, 0b01100000, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// smaddl Xd, Wn, Wm, Xa
	0b10011011, 0b00100000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// smax Vd.16B, Vn.16B, Vm.16B
	// smax Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// smax Vd.8H, Vn.8H, Vm.8H
	// smax Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// smax Vd.4S, Vn.4S, Vm.4S
	// smax Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// smaxp Vd.16B, Vn.16B, Vm.16B
	// smaxp Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// smaxp Vd.8H, Vn.8H, Vm.8H
	// smaxp Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// smaxp Vd.4S, Vn.4S, Vm.4S
	// smaxp Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// smaxv Bd, Vn.16B
	// smaxv Bd, Vn.8B
	0b00001110, 0b00110000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// smaxv Hd, Vn.8H
	// smaxv Hd, Vn.4H
	0b00001110, 0b01110000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// smaxv Sd, Vn.4S
	0b00001110, 0b10110000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// smc #imm  ··································································  (0 <= imm < 65536)
	0b11010100, 0b00000000, 0b00000000, 0b00000011, 1, CmdUbits, 5, 16,

	// smin Vd.16B, Vn.16B, Vm.16B
	// smin Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// smin Vd.8H, Vn.8H, Vm.8H
	// smin Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// smin Vd.4S, Vn.4S, Vm.4S
	// smin Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sminp Vd.16B, Vn.16B, Vm.16B
	// sminp Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sminp Vd.8H, Vn.8H, Vm.8H
	// sminp Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sminp Vd.4S, Vn.4S, Vm.4S
	// sminp Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sminv Bd, Vn.16B
	// sminv Bd, Vn.8B
	0b00001110, 0b00110001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sminv Hd, Vn.8H
	// sminv Hd, Vn.4H
	0b00001110, 0b01110001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sminv Sd, Vn.4S
	0b00001110, 0b10110001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// smlal Vd.4S, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b00001111, 0b01000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// smlal Vd.2D, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// smlal Vd.8H, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smlal Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smlal Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// smlal2 Vd.4S, Vn.8H, Vm.H[i]  ························································  (m < 16)
	0b01001111, 0b01000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// smlal2 Vd.2D, Vn.4S, Vm.S[i]
	0b01001111, 0b10000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// smlal2 Vd.8H, Vn.16B, Vm.16B
	0b01001110, 0b00100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smlal2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smlal2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// smlsl Vd.4S, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b00001111, 0b01000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// smlsl Vd.2D, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// smlsl Vd.8H, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smlsl Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smlsl Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// smlsl2 Vd.4S, Vn.8H, Vm.H[i]  ························································  (m < 16)
	0b01001111, 0b01000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// smlsl2 Vd.2D, Vn.4S, Vm.S[i]
	0b01001111, 0b10000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// smlsl2 Vd.8H, Vn.16B, Vm.16B
	0b01001110, 0b00100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smlsl2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smlsl2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// smnegl Xd, Wn, Wm
	0b10011011, 0b00100000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// smov Wd, Vn.B[i]
	0b00001110, 0b00000001, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 17, 4,
	// smov Wd, Vn.H[i]
	0b00001110, 0b00000010, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 18, 3,
	// smov Xd, Vn.B[i]
	0b01001110, 0b00000001, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 17, 4,
	// smov Xd, Vn.H[i]
	0b01001110, 0b00000010, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 18, 3,
	// smov Xd, Vn.S[i]
	0b01001110, 0b00000100, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 19, 2,

	// smsubl Xd, Wn, Wm, Xa
	0b10011011, 0b00100000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// smulh Xd, Xn, Xm
	0b10011011, 0b01000000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// smull Vd.4S, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b00001111, 0b01000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// smull Vd.2D, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// smull Vd.8H, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smull Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smull Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smull Xd, Wn, Wm
	0b10011011, 0b00100000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// smull2 Vd.4S, Vn.8H, Vm.H[i]  ························································  (m < 16)
	0b01001111, 0b01000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// smull2 Vd.2D, Vn.4S, Vm.S[i]
	0b01001111, 0b10000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// smull2 Vd.8H, Vn.16B, Vm.16B
	0b01001110, 0b00100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smull2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// smull2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sqabs Bd, Bn
	0b01011110, 0b00100000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// sqabs Hd, Hn
	0b01011110, 0b01100000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// sqabs Sd, Sn
	0b01011110, 0b10100000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// sqabs Dd, Dn
	0b01011110, 0b11100000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// sqabs Vd.16B, Vn.16B
	// sqabs Vd.8B, Vn.8B
	0b00001110, 0b00100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sqabs Vd.8H, Vn.8H
	// sqabs Vd.4H, Vn.4H
	0b00001110, 0b01100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sqabs Vd.4S, Vn.4S
	// sqabs Vd.2S, Vn.2S
	0b00001110, 0b10100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sqabs Vd.2D, Vn.2D
	0b00001110, 0b11100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// sqadd Bd, Bn, Bm
	0b01011110, 0b00100000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqadd Hd, Hn, Hm
	0b01011110, 0b01100000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqadd Sd, Sn, Sm
	0b01011110, 0b10100000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqadd Dd, Dn, Dm
	0b01011110, 0b11100000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqadd Vd.16B, Vn.16B, Vm.16B
	// sqadd Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqadd Vd.8H, Vn.8H, Vm.8H
	// sqadd Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqadd Vd.4S, Vn.4S, Vm.4S
	// sqadd Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqadd Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sqdmlal Sd, Hn, Vm.H[i]  ·····························································  (m < 16)
	0b01011111, 0b01000000, 0b00110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmlal Dd, Sn, Vm.S[i]
	0b01011111, 0b10000000, 0b00110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmlal Vd.4S, Vn.4H, Vm.H[i]  ·······················································  (m < 16)
	0b00001111, 0b01000000, 0b00110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmlal Vd.2D, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b00110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmlal Sd, Hn, Hm
	0b01011110, 0b01100000, 0b10010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmlal Dd, Sn, Sm
	0b01011110, 0b10100000, 0b10010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmlal Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmlal Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sqdmlal2 Vd.4S, Vn.8H, Vm.H[i]  ······················································  (m < 16)
	0b01001111, 0b01000000, 0b00110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmlal2 Vd.2D, Vn.4S, Vm.S[i]
	0b01001111, 0b10000000, 0b00110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmlal2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b10010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmlal2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b10010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sqdmlsl Sd, Hn, Vm.H[i]  ·····························································  (m < 16)
	0b01011111, 0b01000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmlsl Dd, Sn, Vm.S[i]
	0b01011111, 0b10000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmlsl Vd.4S, Vn.4H, Vm.H[i]  ·······················································  (m < 16)
	0b00001111, 0b01000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmlsl Vd.2D, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmlsl Sd, Hn, Hm
	0b01011110, 0b01100000, 0b10110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmlsl Dd, Sn, Sm
	0b01011110, 0b10100000, 0b10110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmlsl Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmlsl Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sqdmlsl2 Vd.4S, Vn.8H, Vm.H[i]  ······················································  (m < 16)
	0b01001111, 0b01000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmlsl2 Vd.2D, Vn.4S, Vm.S[i]
	0b01001111, 0b10000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmlsl2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b10110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmlsl2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b10110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sqdmulh Hd, Hn, Vm.H[i]  ·····························································  (m < 16)
	0b01011111, 0b01000000, 0b11000000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmulh Sd, Sn, Vm.S[i]
	0b01011111, 0b10000000, 0b11000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmulh Vd.8H, Vn.8H, Vm.H[i]  ·······················································  (m < 16)
	// sqdmulh Vd.4H, Vn.4H, Vm.H[i]  ·······················································  (m < 16)
	0b00001111, 0b01000000, 0b11000000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// sqdmulh Vd.4S, Vn.4S, Vm.S[i]
	// sqdmulh Vd.2S, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b11000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// sqdmulh Hd, Hn, Hm
	0b01011110, 0b01100000, 0b10110100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmulh Sd, Sn, Sm
	0b01011110, 0b10100000, 0b10110100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmulh Vd.8H, Vn.8H, Vm.8H
	// sqdmulh Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b10110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqdmulh Vd.4S, Vn.4S, Vm.4S
	// sqdmulh Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b10110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sqdmull Sd, Hn, Vm.H[i]  ·····························································  (m < 16)
	0b01011111, 0b01000000, 0b10110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmull Dd, Sn, Vm.S[i]
	0b01011111, 0b10000000, 0b10110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmull Vd.4S, Vn.4H, Vm.H[i]  ·······················································  (m < 16)
	0b00001111, 0b01000000, 0b10110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmull Vd.2D, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b10110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmull Sd, Hn, Hm
	0b01011110, 0b01100000, 0b11010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmull Dd, Sn, Sm
	0b01011110, 0b10100000, 0b11010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmull Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b11010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmull Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b11010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sqdmull2 Vd.4S, Vn.8H, Vm.H[i]  ······················································  (m < 16)
	0b01001111, 0b01000000, 0b10110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqdmull2 Vd.2D, Vn.4S, Vm.S[i]
	0b01001111, 0b10000000, 0b10110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqdmull2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b11010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqdmull2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b11010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// sqneg Bd, Bn
	0b01111110, 0b00100000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// sqneg Hd, Hn
	0b01111110, 0b01100000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// sqneg Sd, Sn
	0b01111110, 0b10100000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// sqneg Dd, Dn
	0b01111110, 0b11100000, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// sqneg Vd.16B, Vn.16B
	// sqneg Vd.8B, Vn.8B
	0b00101110, 0b00100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sqneg Vd.8H, Vn.8H
	// sqneg Vd.4H, Vn.4H
	0b00101110, 0b01100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sqneg Vd.4S, Vn.4S
	// sqneg Vd.2S, Vn.2S
	0b00101110, 0b10100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// sqneg Vd.2D, Vn.2D
	0b00101110, 0b11100000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// sqrdmlah Hd, Hn, Vm.H[i]  ····························································  (m < 16)
	0b01111111, 0b01000000, 0b11010000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqrdmlah Sd, Sn, Vm.S[i]
	0b01111111, 0b10000000, 0b11010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqrdmlah Vd.8H, Vn.8H, Vm.H[i]  ······················································  (m < 16)
	// sqrdmlah Vd.4H, Vn.4H, Vm.H[i]  ······················································  (m < 16)
	0b00101111, 0b01000000, 0b11010000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// sqrdmlah Vd.4S, Vn.4S, Vm.S[i]
	// sqrdmlah Vd.2S, Vn.2S, Vm.S[i]
	0b00101111, 0b10000000, 0b11010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// sqrdmlah Hd, Hn, Hm
	0b01111110, 0b01000000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrdmlah Sd, Sn, Sm
	0b01111110, 0b10000000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrdmlah Vd.8H, Vn.8H, Vm.8H
	// sqrdmlah Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqrdmlah Vd.4S, Vn.4S, Vm.4S
	// sqrdmlah Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10000000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sqrdmlsh Hd, Hn, Vm.H[i]  ····························································  (m < 16)
	0b01111111, 0b01000000, 0b11110000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqrdmlsh Sd, Sn, Vm.S[i]
	0b01111111, 0b10000000, 0b11110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqrdmlsh Vd.8H, Vn.8H, Vm.H[i]  ······················································  (m < 16)
	// sqrdmlsh Vd.4H, Vn.4H, Vm.H[i]  ······················································  (m < 16)
	0b00101111, 0b01000000, 0b11110000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// sqrdmlsh Vd.4S, Vn.4S, Vm.S[i]
	// sqrdmlsh Vd.2S, Vn.2S, Vm.S[i]
	0b00101111, 0b10000000, 0b11110000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// sqrdmlsh Hd, Hn, Hm
	0b01111110, 0b01000000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrdmlsh Sd, Sn, Sm
	0b01111110, 0b10000000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrdmlsh Vd.8H, Vn.8H, Vm.8H
	// sqrdmlsh Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01000000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqrdmlsh Vd.4S, Vn.4S, Vm.4S
	// sqrdmlsh Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10000000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sqrdmulh Hd, Hn, Vm.H[i]  ····························································  (m < 16)
	0b01011111, 0b01000000, 0b11010000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// sqrdmulh Sd, Sn, Vm.S[i]
	0b01011111, 0b10000000, 0b11010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// sqrdmulh Vd.8H, Vn.8H, Vm.H[i]  ······················································  (m < 16)
	// sqrdmulh Vd.4H, Vn.4H, Vm.H[i]  ······················································  (m < 16)
	0b00001111, 0b01000000, 0b11010000, 0b00000000, 5, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3, CmdRwidth30,
	// sqrdmulh Vd.4S, Vn.4S, Vm.S[i]
	// sqrdmulh Vd.2S, Vn.2S, Vm.S[i]
	0b00001111, 0b10000000, 0b11010000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdUfields11, 2, CmdRwidth30,
	// sqrdmulh Hd, Hn, Hm
	0b01111110, 0b01100000, 0b10110100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrdmulh Sd, Sn, Sm
	0b01111110, 0b10100000, 0b10110100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrdmulh Vd.8H, Vn.8H, Vm.8H
	// sqrdmulh Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b10110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqrdmulh Vd.4S, Vn.4S, Vm.4S
	// sqrdmulh Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b10110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sqrshl Bd, Bn, Bm
	0b01011110, 0b00100000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrshl Hd, Hn, Hm
	0b01011110, 0b01100000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrshl Sd, Sn, Sm
	0b01011110, 0b10100000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrshl Dd, Dn, Dm
	0b01011110, 0b11100000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqrshl Vd.16B, Vn.16B, Vm.16B
	// sqrshl Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqrshl Vd.8H, Vn.8H, Vm.8H
	// sqrshl Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqrshl Vd.4S, Vn.4S, Vm.4S
	// sqrshl Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqrshl Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b01011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sqrshrn Bd, Hn, #imm  ··························································  (0 < imm <= 8)
	0b01011111, 0b00000000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 8, CmdUsub, 16, 4, 16,
	// sqrshrn Hd, Sn, #imm  ·························································  (0 < imm <= 16)
	0b01011111, 0b00000000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// sqrshrn Sd, Dn, #imm  ·························································  (0 < imm <= 32)
	0b01011111, 0b00000000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// sqrshrn Vd.8B, Vn.8H, #imm  ····················································  (0 < imm <= 8)
	0b00001111, 0b00001000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// sqrshrn Vd.4H, Vn.4S, #imm  ···················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// sqrshrn Vd.2S, Vn.2D, #imm  ···················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// sqrshrn2 Vd.16B, Vn.8H, #imm  ··················································  (0 < imm <= 8)
	0b01001111, 0b00001000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// sqrshrn2 Vd.8H, Vn.4S, #imm  ··················································  (0 < imm <= 16)
	0b01001111, 0b00010000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// sqrshrn2 Vd.4S, Vn.2D, #imm  ··················································  (0 < imm <= 32)
	0b01001111, 0b00100000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// sqrshrun Bd, Hn, #imm  ·························································  (0 < imm <= 8)
	0b01111111, 0b00000000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 8, CmdUsub, 16, 4, 16,
	// sqrshrun Hd, Sn, #imm  ························································  (0 < imm <= 16)
	0b01111111, 0b00000000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// sqrshrun Sd, Dn, #imm  ························································  (0 < imm <= 32)
	0b01111111, 0b00000000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// sqrshrun Vd.8B, Vn.8H, #imm  ···················································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// sqrshrun Vd.4H, Vn.4S, #imm  ··················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// sqrshrun Vd.2S, Vn.2D, #imm  ··················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// sqrshrun2 Vd.16B, Vn.8H, #imm  ·················································  (0 < imm <= 8)
	0b01101111, 0b00001000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// sqrshrun2 Vd.8H, Vn.4S, #imm  ·················································  (0 < imm <= 16)
	0b01101111, 0b00010000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// sqrshrun2 Vd.4S, Vn.2D, #imm  ·················································  (0 < imm <= 32)
	0b01101111, 0b00100000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// sqshl Bd, Bn, #imm  ····························································  (0 <= imm < 8)
	0b01011111, 0b00001000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 3,
	// sqshl Hd, Hn, #imm  ···························································  (0 <= imm < 16)
	0b01011111, 0b00010000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 4,
	// sqshl Sd, Sn, #imm  ···························································  (0 <= imm < 32)
	0b01011111, 0b00100000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,
	// sqshl Dd, Dn, #imm  ···························································  (0 <= imm < 64)
	0b01011111, 0b01000000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 6,
	// sqshl Vd.16B, Vn.16B, #imm  ····················································  (0 <= imm < 8)
	// sqshl Vd.8B, Vn.8B, #imm  ······················································  (0 <= imm < 8)
	0b00001111, 0b00001000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 3, CmdRwidth30,
	// sqshl Vd.8H, Vn.8H, #imm  ·····················································  (0 <= imm < 16)
	// sqshl Vd.4H, Vn.4H, #imm  ·····················································  (0 <= imm < 16)
	0b00001111, 0b00010000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 4, CmdRwidth30,
	// sqshl Vd.4S, Vn.4S, #imm  ·····················································  (0 <= imm < 32)
	// sqshl Vd.2S, Vn.2S, #imm  ·····················································  (0 <= imm < 32)
	0b00001111, 0b00100000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 5, CmdRwidth30,
	// sqshl Vd.2D, Vn.2D, #imm  ·····················································  (0 <= imm < 64)
	0b00001111, 0b01000000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 6, CmdRwidth30,
	// sqshl Bd, Bn, Bm
	0b01011110, 0b00100000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqshl Hd, Hn, Hm
	0b01011110, 0b01100000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqshl Sd, Sn, Sm
	0b01011110, 0b10100000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqshl Dd, Dn, Dm
	0b01011110, 0b11100000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqshl Vd.16B, Vn.16B, Vm.16B
	// sqshl Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqshl Vd.8H, Vn.8H, Vm.8H
	// sqshl Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqshl Vd.4S, Vn.4S, Vm.4S
	// sqshl Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqshl Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sqshlu Bd, Bn, #imm  ···························································  (0 <= imm < 8)
	0b01111111, 0b00001000, 0b01100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 3,
	// sqshlu Hd, Hn, #imm  ··························································  (0 <= imm < 16)
	0b01111111, 0b00010000, 0b01100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 4,
	// sqshlu Sd, Sn, #imm  ··························································  (0 <= imm < 32)
	0b01111111, 0b00100000, 0b01100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,
	// sqshlu Dd, Dn, #imm  ··························································  (0 <= imm < 64)
	0b01111111, 0b01000000, 0b01100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 6,
	// sqshlu Vd.16B, Vn.16B, #imm  ···················································  (0 <= imm < 8)
	// sqshlu Vd.8B, Vn.8B, #imm  ·····················································  (0 <= imm < 8)
	0b00101111, 0b00001000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 3, CmdRwidth30,
	// sqshlu Vd.8H, Vn.8H, #imm  ····················································  (0 <= imm < 16)
	// sqshlu Vd.4H, Vn.4H, #imm  ····················································  (0 <= imm < 16)
	0b00101111, 0b00010000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 4, CmdRwidth30,
	// sqshlu Vd.4S, Vn.4S, #imm  ····················································  (0 <= imm < 32)
	// sqshlu Vd.2S, Vn.2S, #imm  ····················································  (0 <= imm < 32)
	0b00101111, 0b00100000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 5, CmdRwidth30,
	// sqshlu Vd.2D, Vn.2D, #imm  ····················································  (0 <= imm < 64)
	0b00101111, 0b01000000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 6, CmdRwidth30,

	// sqshrn Bd, Hn, #imm  ···························································  (0 < imm <= 8)
	0b01011111, 0b00000000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 8, CmdUsub, 16, 4, 16,
	// sqshrn Hd, Sn, #imm  ··························································  (0 < imm <= 16)
	0b01011111, 0b00000000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// sqshrn Sd, Dn, #imm  ··························································  (0 < imm <= 32)
	0b01011111, 0b00000000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// sqshrn Vd.8B, Vn.8H, #imm  ·····················································  (0 < imm <= 8)
	0b00001111, 0b00001000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// sqshrn Vd.4H, Vn.4S, #imm  ····················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// sqshrn Vd.2S, Vn.2D, #imm  ····················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// sqshrn2 Vd.16B, Vn.8H, #imm  ···················································  (0 < imm <= 8)
	0b01001111, 0b00001000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// sqshrn2 Vd.8H, Vn.4S, #imm  ···················································  (0 < imm <= 16)
	0b01001111, 0b00010000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// sqshrn2 Vd.4S, Vn.2D, #imm  ···················································  (0 < imm <= 32)
	0b01001111, 0b00100000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// sqshrun Bd, Hn, #imm  ··························································  (0 < imm <= 8)
	0b01111111, 0b00000000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 8, CmdUsub, 16, 4, 16,
	// sqshrun Hd, Sn, #imm  ·························································  (0 < imm <= 16)
	0b01111111, 0b00000000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// sqshrun Sd, Dn, #imm  ·························································  (0 < imm <= 32)
	0b01111111, 0b00000000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// sqshrun Vd.8B, Vn.8H, #imm  ····················································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// sqshrun Vd.4H, Vn.4S, #imm  ···················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// sqshrun Vd.2S, Vn.2D, #imm  ···················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// sqshrun2 Vd.16B, Vn.8H, #imm  ··················································  (0 < imm <= 8)
	0b01101111, 0b00001000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// sqshrun2 Vd.8H, Vn.4S, #imm  ··················································  (0 < imm <= 16)
	0b01101111, 0b00010000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// sqshrun2 Vd.4S, Vn.2D, #imm  ··················································  (0 < imm <= 32)
	0b01101111, 0b00100000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// sqsub Bd, Bn, Bm
	0b01011110, 0b00100000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqsub Hd, Hn, Hm
	0b01011110, 0b01100000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqsub Sd, Sn, Sm
	0b01011110, 0b10100000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqsub Dd, Dn, Dm
	0b01011110, 0b11100000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sqsub Vd.16B, Vn.16B, Vm.16B
	// sqsub Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqsub Vd.8H, Vn.8H, Vm.8H
	// sqsub Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqsub Vd.4S, Vn.4S, Vm.4S
	// sqsub Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sqsub Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sqxtn Bd, Hn
	0b01011110, 0b00100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtn Hd, Sn
	0b01011110, 0b01100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtn Sd, Dn
	0b01011110, 0b10100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtn Vd.8B, Vn.8H
	0b00001110, 0b00100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtn Vd.4H, Vn.4S
	0b00001110, 0b01100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtn Vd.2S, Vn.2D
	0b00001110, 0b10100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,

	// sqxtn2 Vd.16B, Vn.8H
	0b01001110, 0b00100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtn2 Vd.8H, Vn.4S
	0b01001110, 0b01100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtn2 Vd.4S, Vn.2D
	0b01001110, 0b10100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,

	// sqxtun Bd, Hn
	0b01111110, 0b00100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtun Hd, Sn
	0b01111110, 0b01100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtun Sd, Dn
	0b01111110, 0b10100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtun Vd.8B, Vn.8H
	0b00101110, 0b00100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtun Vd.4H, Vn.4S
	0b00101110, 0b01100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtun Vd.2S, Vn.2D
	0b00101110, 0b10100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,

	// sqxtun2 Vd.16B, Vn.8H
	0b01101110, 0b00100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtun2 Vd.8H, Vn.4S
	0b01101110, 0b01100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// sqxtun2 Vd.4S, Vn.2D
	0b01101110, 0b10100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,

	// srhadd Vd.16B, Vn.16B, Vm.16B
	// srhadd Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// srhadd Vd.8H, Vn.8H, Vm.8H
	// srhadd Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// srhadd Vd.4S, Vn.4S, Vm.4S
	// srhadd Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sri Dd, Dn, #imm  ·····························································  (0 < imm <= 64)
	0b01111111, 0b00000000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// sri Vd.16B, Vn.16B, #imm  ······················································  (0 < imm <= 8)
	// sri Vd.8B, Vn.8B, #imm  ························································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// sri Vd.8H, Vn.8H, #imm  ·······················································  (0 < imm <= 16)
	// sri Vd.4H, Vn.4H, #imm  ·······················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// sri Vd.4S, Vn.4S, #imm  ·······················································  (0 < imm <= 32)
	// sri Vd.2S, Vn.2S, #imm  ·······················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// sri Vd.2D, Vn.2D, #imm  ·······················································  (0 < imm <= 64)
	0b00101111, 0b01000000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// srshl Dd, Dn, Dm
	0b01011110, 0b11100000, 0b01010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// srshl Vd.16B, Vn.16B, Vm.16B
	// srshl Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// srshl Vd.8H, Vn.8H, Vm.8H
	// srshl Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// srshl Vd.4S, Vn.4S, Vm.4S
	// srshl Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// srshl Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// srshr Dd, Dn, #imm  ···························································  (0 < imm <= 64)
	0b01011111, 0b00000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// srshr Vd.16B, Vn.16B, #imm  ····················································  (0 < imm <= 8)
	// srshr Vd.8B, Vn.8B, #imm  ······················································  (0 < imm <= 8)
	0b00001111, 0b00001000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// srshr Vd.8H, Vn.8H, #imm  ·····················································  (0 < imm <= 16)
	// srshr Vd.4H, Vn.4H, #imm  ·····················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// srshr Vd.4S, Vn.4S, #imm  ·····················································  (0 < imm <= 32)
	// srshr Vd.2S, Vn.2S, #imm  ·····················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// srshr Vd.2D, Vn.2D, #imm  ·····················································  (0 < imm <= 64)
	0b00001111, 0b01000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// srsra Dd, Dn, #imm  ···························································  (0 < imm <= 64)
	0b01011111, 0b00000000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// srsra Vd.16B, Vn.16B, #imm  ····················································  (0 < imm <= 8)
	// srsra Vd.8B, Vn.8B, #imm  ······················································  (0 < imm <= 8)
	0b00001111, 0b00001000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// srsra Vd.8H, Vn.8H, #imm  ·····················································  (0 < imm <= 16)
	// srsra Vd.4H, Vn.4H, #imm  ·····················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// srsra Vd.4S, Vn.4S, #imm  ·····················································  (0 < imm <= 32)
	// srsra Vd.2S, Vn.2S, #imm  ·····················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// srsra Vd.2D, Vn.2D, #imm  ·····················································  (0 < imm <= 64)
	0b00001111, 0b01000000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// ssbb
	0b11010101, 0b00000011, 0b00110000, 0b10011111, 0,

	// sshl Dd, Dn, Dm
	0b01011110, 0b11100000, 0b01000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sshl Vd.16B, Vn.16B, Vm.16B
	// sshl Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sshl Vd.8H, Vn.8H, Vm.8H
	// sshl Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sshl Vd.4S, Vn.4S, Vm.4S
	// sshl Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sshl Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// sshll Vd.8H, Vn.8B, #imm  ······················································  (0 <= imm < 8)
	0b00001111, 0b00001000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 3,
	// sshll Vd.4S, Vn.4H, #imm  ·····················································  (0 <= imm < 16)
	0b00001111, 0b00010000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 4,
	// sshll Vd.2D, Vn.2S, #imm  ·····················································  (0 <= imm < 32)
	0b00001111, 0b00100000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,

	// sshll2 Vd.8H, Vn.16B, #imm  ····················································  (0 <= imm < 8)
	0b01001111, 0b00001000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 3,
	// sshll2 Vd.4S, Vn.8H, #imm  ····················································  (0 <= imm < 16)
	0b01001111, 0b00010000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 4,
	// sshll2 Vd.2D, Vn.4S, #imm  ····················································  (0 <= imm < 32)
	0b01001111, 0b00100000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,

	// sshr Dd, Dn, #imm  ····························································  (0 < imm <= 64)
	0b01011111, 0b00000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// sshr Vd.16B, Vn.16B, #imm  ·····················································  (0 < imm <= 8)
	// sshr Vd.8B, Vn.8B, #imm  ·······················································  (0 < imm <= 8)
	0b00001111, 0b00001000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// sshr Vd.8H, Vn.8H, #imm  ······················································  (0 < imm <= 16)
	// sshr Vd.4H, Vn.4H, #imm  ······················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// sshr Vd.4S, Vn.4S, #imm  ······················································  (0 < imm <= 32)
	// sshr Vd.2S, Vn.2S, #imm  ······················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// sshr Vd.2D, Vn.2D, #imm  ······················································  (0 < imm <= 64)
	0b00001111, 0b01000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// ssra Dd, Dn, #imm  ····························································  (0 < imm <= 64)
	0b01011111, 0b00000000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// ssra Vd.16B, Vn.16B, #imm  ·····················································  (0 < imm <= 8)
	// ssra Vd.8B, Vn.8B, #imm  ·······················································  (0 < imm <= 8)
	0b00001111, 0b00001000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// ssra Vd.8H, Vn.8H, #imm  ······················································  (0 < imm <= 16)
	// ssra Vd.4H, Vn.4H, #imm  ······················································  (0 < imm <= 16)
	0b00001111, 0b00010000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// ssra Vd.4S, Vn.4S, #imm  ······················································  (0 < imm <= 32)
	// ssra Vd.2S, Vn.2S, #imm  ······················································  (0 < imm <= 32)
	0b00001111, 0b00100000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// ssra Vd.2D, Vn.2D, #imm  ······················································  (0 < imm <= 64)
	0b00001111, 0b01000000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// ssubl Vd.8H, Vn.8B, Vm.8B
	0b00001110, 0b00100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ssubl Vd.4S, Vn.4H, Vm.4H
	0b00001110, 0b01100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ssubl Vd.2D, Vn.2S, Vm.2S
	0b00001110, 0b10100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// ssubl2 Vd.8H, Vn.16B, Vm.16B
	0b01001110, 0b00100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ssubl2 Vd.4S, Vn.8H, Vm.8H
	0b01001110, 0b01100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ssubl2 Vd.2D, Vn.4S, Vm.4S
	0b01001110, 0b10100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// ssubw Vd.8H, Vn.8H, Vm.8B
	0b00001110, 0b00100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ssubw Vd.4S, Vn.4S, Vm.4H
	0b00001110, 0b01100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ssubw Vd.2D, Vn.2D, Vm.2S
	0b00001110, 0b10100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// ssubw2 Vd.8H, Vn.8H, Vm.16B
	0b01001110, 0b00100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ssubw2 Vd.4S, Vn.4S, Vm.8H
	0b01001110, 0b01100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ssubw2 Vd.2D, Vn.2D, Vm.4S
	0b01001110, 0b10100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// st1 {Vd.16B * 1}, [Xn|SP]
	// st1 {Vd.8B * 1}, [Xn|SP]
	0b00001100, 0b00000000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.8H * 1}, [Xn|SP]
	// st1 {Vd.4H * 1}, [Xn|SP]
	0b00001100, 0b00000000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.4S * 1}, [Xn|SP]
	// st1 {Vd.2S * 1}, [Xn|SP]
	0b00001100, 0b00000000, 0b01111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.2D * 1}, [Xn|SP]
	// st1 {Vd.1D * 1}, [Xn|SP]
	0b00001100, 0b00000000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.16B * 2}, [Xn|SP]
	// st1 {Vd.8B * 2}, [Xn|SP]
	0b00001100, 0b00000000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.8H * 2}, [Xn|SP]
	// st1 {Vd.4H * 2}, [Xn|SP]
	0b00001100, 0b00000000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.4S * 2}, [Xn|SP]
	// st1 {Vd.2S * 2}, [Xn|SP]
	0b00001100, 0b00000000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.2D * 2}, [Xn|SP]
	// st1 {Vd.1D * 2}, [Xn|SP]
	0b00001100, 0b00000000, 0b10101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.16B * 3}, [Xn|SP]
	// st1 {Vd.8B * 3}, [Xn|SP]
	0b00001100, 0b00000000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.8H * 3}, [Xn|SP]
	// st1 {Vd.4H * 3}, [Xn|SP]
	0b00001100, 0b00000000, 0b01100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.4S * 3}, [Xn|SP]
	// st1 {Vd.2S * 3}, [Xn|SP]
	0b00001100, 0b00000000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.2D * 3}, [Xn|SP]
	// st1 {Vd.1D * 3}, [Xn|SP]
	0b00001100, 0b00000000, 0b01101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.16B * 4}, [Xn|SP]
	// st1 {Vd.8B * 4}, [Xn|SP]
	0b00001100, 0b00000000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.8H * 4}, [Xn|SP]
	// st1 {Vd.4H * 4}, [Xn|SP]
	0b00001100, 0b00000000, 0b00100100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.4S * 4}, [Xn|SP]
	// st1 {Vd.2S * 4}, [Xn|SP]
	0b00001100, 0b00000000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.2D * 4}, [Xn|SP]
	// st1 {Vd.1D * 4}, [Xn|SP]
	0b00001100, 0b00000000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st1 {Vd.8B * 1}, [Xn|SP], #8
	0b00001100, 0b10011111, 0b01110000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.4H * 1}, [Xn|SP], #8
	0b00001100, 0b10011111, 0b01110100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.2S * 1}, [Xn|SP], #8
	0b00001100, 0b10011111, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.1D * 1}, [Xn|SP], #8
	0b00001100, 0b10011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.16B * 1}, [Xn|SP], #16
	0b01001100, 0b10011111, 0b01110000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.8H * 1}, [Xn|SP], #16
	0b01001100, 0b10011111, 0b01110100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.4S * 1}, [Xn|SP], #16
	0b01001100, 0b10011111, 0b01111000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.2D * 1}, [Xn|SP], #16
	0b01001100, 0b10011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.16B * 1}, [Xn|SP], Xm  ······················································  (m != 31)
	// st1 {Vd.8B * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.8H * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.4H * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.4S * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.2S * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01111000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.2D * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.1D * 1}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01111100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.8B * 2}, [Xn|SP], #16
	0b00001100, 0b10011111, 0b10100000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.4H * 2}, [Xn|SP], #16
	0b00001100, 0b10011111, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.2S * 2}, [Xn|SP], #16
	0b00001100, 0b10011111, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.1D * 2}, [Xn|SP], #16
	0b00001100, 0b10011111, 0b10101100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.16B * 2}, [Xn|SP], #32
	0b01001100, 0b10011111, 0b10100000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.8H * 2}, [Xn|SP], #32
	0b01001100, 0b10011111, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.4S * 2}, [Xn|SP], #32
	0b01001100, 0b10011111, 0b10101000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.2D * 2}, [Xn|SP], #32
	0b01001100, 0b10011111, 0b10101100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.16B * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	// st1 {Vd.8B * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.8H * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.4H * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b10100100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.4S * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.2S * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b10101000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.2D * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.1D * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b10101100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.8B * 3}, [Xn|SP], #24
	0b00001100, 0b10011111, 0b01100000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.4H * 3}, [Xn|SP], #24
	0b00001100, 0b10011111, 0b01100100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.2S * 3}, [Xn|SP], #24
	0b00001100, 0b10011111, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.1D * 3}, [Xn|SP], #24
	0b00001100, 0b10011111, 0b01101100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.16B * 3}, [Xn|SP], #48
	0b01001100, 0b10011111, 0b01100000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.8H * 3}, [Xn|SP], #48
	0b01001100, 0b10011111, 0b01100100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.4S * 3}, [Xn|SP], #48
	0b01001100, 0b10011111, 0b01101000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.2D * 3}, [Xn|SP], #48
	0b01001100, 0b10011111, 0b01101100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.16B * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	// st1 {Vd.8B * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.8H * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.4H * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.4S * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.2S * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01101000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.2D * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.1D * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01101100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.8B * 4}, [Xn|SP], #32
	0b00001100, 0b10011111, 0b00100000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.4H * 4}, [Xn|SP], #32
	0b00001100, 0b10011111, 0b00100100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.2S * 4}, [Xn|SP], #32
	0b00001100, 0b10011111, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.1D * 4}, [Xn|SP], #32
	0b00001100, 0b10011111, 0b00101100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.16B * 4}, [Xn|SP], #64
	0b01001100, 0b10011111, 0b00100000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.8H * 4}, [Xn|SP], #64
	0b01001100, 0b10011111, 0b00100100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.4S * 4}, [Xn|SP], #64
	0b01001100, 0b10011111, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.2D * 4}, [Xn|SP], #64
	0b01001100, 0b10011111, 0b00101100, 0b00000000, 2, CmdR0, CmdR5,
	// st1 {Vd.16B * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	// st1 {Vd.8B * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.8H * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.4H * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.4S * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.2S * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b00101000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.2D * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st1 {Vd.1D * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st1 {Vd.B * 1}[i], [Xn|SP]
	0b00001101, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// st1 {Vd.H * 1}[i], [Xn|SP]
	0b00001101, 0b00000000, 0b01000000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// st1 {Vd.S * 1}[i], [Xn|SP]
	0b00001101, 0b00000000, 0b10000000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// st1 {Vd.D * 1}[i], [Xn|SP]
	0b00001101, 0b00000000, 0b10000100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// st1 {Vd.B * 1}[i], [Xn|SP], #1
	0b00001101, 0b10011111, 0b00000000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// st1 {Vd.B * 1}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdUfields30, 4, CmdR5, CmdRNz16,
	// st1 {Vd.H * 1}[i], [Xn|SP], #2
	0b00001101, 0b10011111, 0b01000000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// st1 {Vd.H * 1}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10000000, 0b01000000, 0b00000000, 4, CmdR0, CmdUfields30, 3, CmdR5, CmdRNz16,
	// st1 {Vd.S * 1}[i], [Xn|SP], #4
	0b00001101, 0b10011111, 0b10000000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// st1 {Vd.S * 1}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10000000, 0b10000000, 0b00000000, 4, CmdR0, CmdUfields30, 2, CmdR5, CmdRNz16,
	// st1 {Vd.D * 1}[i], [Xn|SP], #8
	0b00001101, 0b10011111, 0b10000100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// st1 {Vd.D * 1}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10000000, 0b10000100, 0b00000000, 4, CmdR0, CmdUfields30, 1, CmdR5, CmdRNz16,

	// st2 {Vd.16B * 2}, [Xn|SP]
	// st2 {Vd.8B * 2}, [Xn|SP]
	0b00001100, 0b00000000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st2 {Vd.8H * 2}, [Xn|SP]
	// st2 {Vd.4H * 2}, [Xn|SP]
	0b00001100, 0b00000000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st2 {Vd.4S * 2}, [Xn|SP]
	// st2 {Vd.2S * 2}, [Xn|SP]
	0b00001100, 0b00000000, 0b10001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st2 {Vd.2D * 2}, [Xn|SP]
	0b00001100, 0b00000000, 0b10001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st2 {Vd.8B * 2}, [Xn|SP], #16
	0b00001100, 0b10011111, 0b10000000, 0b00000000, 2, CmdR0, CmdR5,
	// st2 {Vd.4H * 2}, [Xn|SP], #16
	0b00001100, 0b10011111, 0b10000100, 0b00000000, 2, CmdR0, CmdR5,
	// st2 {Vd.2S * 2}, [Xn|SP], #16
	0b00001100, 0b10011111, 0b10001000, 0b00000000, 2, CmdR0, CmdR5,
	// st2 {Vd.16B * 2}, [Xn|SP], #32
	0b01001100, 0b10011111, 0b10000000, 0b00000000, 2, CmdR0, CmdR5,
	// st2 {Vd.8H * 2}, [Xn|SP], #32
	0b01001100, 0b10011111, 0b10000100, 0b00000000, 2, CmdR0, CmdR5,
	// st2 {Vd.4S * 2}, [Xn|SP], #32
	0b01001100, 0b10011111, 0b10001000, 0b00000000, 2, CmdR0, CmdR5,
	// st2 {Vd.2D * 2}, [Xn|SP], #32
	0b01001100, 0b10011111, 0b10001100, 0b00000000, 2, CmdR0, CmdR5,
	// st2 {Vd.16B * 2}, [Xn|SP], Xm  ······················································  (m != 31)
	// st2 {Vd.8B * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st2 {Vd.8H * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st2 {Vd.4H * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st2 {Vd.4S * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st2 {Vd.2S * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b10001000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st2 {Vd.2D * 2}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b10001100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st2 {Vd.B * 2}[i], [Xn|SP]
	0b00001101, 0b00100000, 0b00000000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// st2 {Vd.H * 2}[i], [Xn|SP]
	0b00001101, 0b00100000, 0b01000000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// st2 {Vd.S * 2}[i], [Xn|SP]
	0b00001101, 0b00100000, 0b10000000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// st2 {Vd.D * 2}[i], [Xn|SP]
	0b00001101, 0b00100000, 0b10000100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// st2 {Vd.B * 2}[i], [Xn|SP], #2
	0b00001101, 0b10111111, 0b00000000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// st2 {Vd.B * 2}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10100000, 0b00000000, 0b00000000, 4, CmdR0, CmdUfields30, 4, CmdR5, CmdRNz16,
	// st2 {Vd.H * 2}[i], [Xn|SP], #4
	0b00001101, 0b10111111, 0b01000000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// st2 {Vd.H * 2}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10100000, 0b01000000, 0b00000000, 4, CmdR0, CmdUfields30, 3, CmdR5, CmdRNz16,
	// st2 {Vd.S * 2}[i], [Xn|SP], #8
	0b00001101, 0b10111111, 0b10000000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// st2 {Vd.S * 2}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10100000, 0b10000000, 0b00000000, 4, CmdR0, CmdUfields30, 2, CmdR5, CmdRNz16,
	// st2 {Vd.D * 2}[i], [Xn|SP], #16
	0b00001101, 0b10111111, 0b10000100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// st2 {Vd.D * 2}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10100000, 0b10000100, 0b00000000, 4, CmdR0, CmdUfields30, 1, CmdR5, CmdRNz16,

	// st3 {Vd.16B * 3}, [Xn|SP]
	// st3 {Vd.8B * 3}, [Xn|SP]
	0b00001100, 0b00000000, 0b01000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st3 {Vd.8H * 3}, [Xn|SP]
	// st3 {Vd.4H * 3}, [Xn|SP]
	0b00001100, 0b00000000, 0b01000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st3 {Vd.4S * 3}, [Xn|SP]
	// st3 {Vd.2S * 3}, [Xn|SP]
	0b00001100, 0b00000000, 0b01001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st3 {Vd.2D * 3}, [Xn|SP]
	0b00001100, 0b00000000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st3 {Vd.8B * 3}, [Xn|SP], #24
	0b00001100, 0b10011111, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// st3 {Vd.4H * 3}, [Xn|SP], #24
	0b00001100, 0b10011111, 0b01000100, 0b00000000, 2, CmdR0, CmdR5,
	// st3 {Vd.2S * 3}, [Xn|SP], #24
	0b00001100, 0b10011111, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// st3 {Vd.16B * 3}, [Xn|SP], #48
	0b01001100, 0b10011111, 0b01000000, 0b00000000, 2, CmdR0, CmdR5,
	// st3 {Vd.8H * 3}, [Xn|SP], #48
	0b01001100, 0b10011111, 0b01000100, 0b00000000, 2, CmdR0, CmdR5,
	// st3 {Vd.4S * 3}, [Xn|SP], #48
	0b01001100, 0b10011111, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// st3 {Vd.2D * 3}, [Xn|SP], #48
	0b01001100, 0b10011111, 0b01001100, 0b00000000, 2, CmdR0, CmdR5,
	// st3 {Vd.16B * 3}, [Xn|SP], Xm  ······················································  (m != 31)
	// st3 {Vd.8B * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01000000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st3 {Vd.8H * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st3 {Vd.4H * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st3 {Vd.4S * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st3 {Vd.2S * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01001000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st3 {Vd.2D * 3}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st3 {Vd.B * 3}[i], [Xn|SP]
	0b00001101, 0b00000000, 0b00100000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// st3 {Vd.H * 3}[i], [Xn|SP]
	0b00001101, 0b00000000, 0b01100000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// st3 {Vd.S * 3}[i], [Xn|SP]
	0b00001101, 0b00000000, 0b10100000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// st3 {Vd.D * 3}[i], [Xn|SP]
	0b00001101, 0b00000000, 0b10100100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// st3 {Vd.B * 3}[i], [Xn|SP], #3
	0b00001101, 0b10011111, 0b00100000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// st3 {Vd.B * 3}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10000000, 0b00100000, 0b00000000, 4, CmdR0, CmdUfields30, 4, CmdR5, CmdRNz16,
	// st3 {Vd.H * 3}[i], [Xn|SP], #6
	0b00001101, 0b10011111, 0b01100000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// st3 {Vd.H * 3}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10000000, 0b01100000, 0b00000000, 4, CmdR0, CmdUfields30, 3, CmdR5, CmdRNz16,
	// st3 {Vd.S * 3}[i], [Xn|SP], #12
	0b00001101, 0b10011111, 0b10100000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// st3 {Vd.S * 3}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10000000, 0b10100000, 0b00000000, 4, CmdR0, CmdUfields30, 2, CmdR5, CmdRNz16,
	// st3 {Vd.D * 3}[i], [Xn|SP], #24
	0b00001101, 0b10011111, 0b10100100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// st3 {Vd.D * 3}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10000000, 0b10100100, 0b00000000, 4, CmdR0, CmdUfields30, 1, CmdR5, CmdRNz16,

	// st4 {Vd.16B * 4}, [Xn|SP]
	// st4 {Vd.8B * 4}, [Xn|SP]
	0b00001100, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st4 {Vd.8H * 4}, [Xn|SP]
	// st4 {Vd.4H * 4}, [Xn|SP]
	0b00001100, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st4 {Vd.4S * 4}, [Xn|SP]
	// st4 {Vd.2S * 4}, [Xn|SP]
	0b00001100, 0b00000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st4 {Vd.2D * 4}, [Xn|SP]
	0b00001100, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// st4 {Vd.8B * 4}, [Xn|SP], #32
	0b00001100, 0b10011111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// st4 {Vd.4H * 4}, [Xn|SP], #32
	0b00001100, 0b10011111, 0b00000100, 0b00000000, 2, CmdR0, CmdR5,
	// st4 {Vd.2S * 4}, [Xn|SP], #32
	0b00001100, 0b10011111, 0b00001000, 0b00000000, 2, CmdR0, CmdR5,
	// st4 {Vd.16B * 4}, [Xn|SP], #64
	0b01001100, 0b10011111, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// st4 {Vd.8H * 4}, [Xn|SP], #64
	0b01001100, 0b10011111, 0b00000100, 0b00000000, 2, CmdR0, CmdR5,
	// st4 {Vd.4S * 4}, [Xn|SP], #64
	0b01001100, 0b10011111, 0b00001000, 0b00000000, 2, CmdR0, CmdR5,
	// st4 {Vd.2D * 4}, [Xn|SP], #64
	0b01001100, 0b10011111, 0b00001100, 0b00000000, 2, CmdR0, CmdR5,
	// st4 {Vd.16B * 4}, [Xn|SP], Xm  ······················································  (m != 31)
	// st4 {Vd.8B * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st4 {Vd.8H * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st4 {Vd.4H * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st4 {Vd.4S * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	// st4 {Vd.2S * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b00001000, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st4 {Vd.2D * 4}, [Xn|SP], Xm  ·······················································  (m != 31)
	0b00001100, 0b10000000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdRNz16, CmdRwidth30,
	// st4 {Vd.B * 4}[i], [Xn|SP]
	0b00001101, 0b00100000, 0b00100000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// st4 {Vd.H * 4}[i], [Xn|SP]
	0b00001101, 0b00100000, 0b01100000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// st4 {Vd.S * 4}[i], [Xn|SP]
	0b00001101, 0b00100000, 0b10100000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// st4 {Vd.D * 4}[i], [Xn|SP]
	0b00001101, 0b00100000, 0b10100100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// st4 {Vd.B * 4}[i], [Xn|SP], #4
	0b00001101, 0b10111111, 0b00100000, 0b00000000, 3, CmdR0, CmdUfields30, 4, CmdR5,
	// st4 {Vd.B * 4}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10100000, 0b00100000, 0b00000000, 4, CmdR0, CmdUfields30, 4, CmdR5, CmdRNz16,
	// st4 {Vd.H * 4}[i], [Xn|SP], #8
	0b00001101, 0b10111111, 0b01100000, 0b00000000, 3, CmdR0, CmdUfields30, 3, CmdR5,
	// st4 {Vd.H * 4}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10100000, 0b01100000, 0b00000000, 4, CmdR0, CmdUfields30, 3, CmdR5, CmdRNz16,
	// st4 {Vd.S * 4}[i], [Xn|SP], #16
	0b00001101, 0b10111111, 0b10100000, 0b00000000, 3, CmdR0, CmdUfields30, 2, CmdR5,
	// st4 {Vd.S * 4}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10100000, 0b10100000, 0b00000000, 4, CmdR0, CmdUfields30, 2, CmdR5, CmdRNz16,
	// st4 {Vd.D * 4}[i], [Xn|SP], #32
	0b00001101, 0b10111111, 0b10100100, 0b00000000, 3, CmdR0, CmdUfields30, 1, CmdR5,
	// st4 {Vd.D * 4}[i], [Xn|SP], Xm  ·····················································  (m != 31)
	0b00001101, 0b10100000, 0b10100100, 0b00000000, 4, CmdR0, CmdUfields30, 1, CmdR5, CmdRNz16,

	// stadd Wd, [Xn|SP]
	0b10111000, 0b00100000, 0b00000000, 0b00011111, 2, CmdR16, CmdR5,
	// stadd Xd, [Xn|SP]
	0b11111000, 0b00100000, 0b00000000, 0b00011111, 2, CmdR16, CmdR5,

	// staddb Wd, [Xn|SP]
	0b00111000, 0b00100000, 0b00000000, 0b00011111, 2, CmdR16, CmdR5,

	// staddh Wd, [Xn|SP]
	0b01111000, 0b00100000, 0b00000000, 0b00011111, 2, CmdR16, CmdR5,

	// staddl Wd, [Xn|SP]
	0b10111000, 0b01100000, 0b00000000, 0b00011111, 2, CmdR16, CmdR5,
	// staddl Xd, [Xn|SP]
	0b11111000, 0b01100000, 0b00000000, 0b00011111, 2, CmdR16, CmdR5,

	// staddlb Wd, [Xn|SP]
	0b00111000, 0b01100000, 0b00000000, 0b00011111, 2, CmdR16, CmdR5,

	// staddlh Wd, [Xn|SP]
	0b01111000, 0b01100000, 0b00000000, 0b00011111, 2, CmdR16, CmdR5,

	// stclr Wd, [Xn|SP]
	0b10111000, 0b00100000, 0b00010000, 0b00011111, 2, CmdR16, CmdR5,
	// stclr Xd, [Xn|SP]
	0b11111000, 0b00100000, 0b00010000, 0b00011111, 2, CmdR16, CmdR5,

	// stclrb Wd, [Xn|SP]
	0b00111000, 0b00100000, 0b00010000, 0b00011111, 2, CmdR16, CmdR5,

	// stclrh Wd, [Xn|SP]
	0b01111000, 0b00100000, 0b00010000, 0b00011111, 2, CmdR16, CmdR5,

	// stclrl Wd, [Xn|SP]
	0b10111000, 0b01100000, 0b00010000, 0b00011111, 2, CmdR16, CmdR5,
	// stclrl Xd, [Xn|SP]
	0b11111000, 0b01100000, 0b00010000, 0b00011111, 2, CmdR16, CmdR5,

	// stclrlb Wd, [Xn|SP]
	0b00111000, 0b01100000, 0b00010000, 0b00011111, 2, CmdR16, CmdR5,

	// stclrlh Wd, [Xn|SP]
	0b01111000, 0b01100000, 0b00010000, 0b00011111, 2, CmdR16, CmdR5,

	// steor Wd, [Xn|SP]
	0b10111000, 0b00100000, 0b00100000, 0b00011111, 2, CmdR16, CmdR5,
	// steor Xd, [Xn|SP]
	0b11111000, 0b00100000, 0b00100000, 0b00011111, 2, CmdR16, CmdR5,

	// steorb Wd, [Xn|SP]
	0b00111000, 0b00100000, 0b00100000, 0b00011111, 2, CmdR16, CmdR5,

	// steorh Wd, [Xn|SP]
	0b01111000, 0b00100000, 0b00100000, 0b00011111, 2, CmdR16, CmdR5,

	// steorl Wd, [Xn|SP]
	0b10111000, 0b01100000, 0b00100000, 0b00011111, 2, CmdR16, CmdR5,
	// steorl Xd, [Xn|SP]
	0b11111000, 0b01100000, 0b00100000, 0b00011111, 2, CmdR16, CmdR5,

	// steorlb Wd, [Xn|SP]
	0b00111000, 0b01100000, 0b00100000, 0b00011111, 2, CmdR16, CmdR5,

	// steorlh Wd, [Xn|SP]
	0b01111000, 0b01100000, 0b00100000, 0b00011111, 2, CmdR16, CmdR5,

	// stllr Wd, [Xn|SP]
	0b10001000, 0b10011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,
	// stllr Xd, [Xn|SP]
	0b11001000, 0b10011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// stllrb Wd, [Xn|SP]
	0b00001000, 0b10011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// stllrh Wd, [Xn|SP]
	0b01001000, 0b10011111, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// stlr Wd, [Xn|SP]
	0b10001000, 0b10011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,
	// stlr Xd, [Xn|SP]
	0b11001000, 0b10011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// stlrb Wd, [Xn|SP]
	0b00001000, 0b10011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// stlrh Wd, [Xn|SP]
	0b01001000, 0b10011111, 0b11111100, 0b00000000, 2, CmdR0, CmdR5,

	// stlur Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b10011001, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// stlur Xd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b11011001, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// stlurb Wd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b00011001, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// stlurh Wd, [Xn|SP {, #imm }]  ·············································  (-256 <= imm < 256)
	0b01011001, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// stlxp Wd, Wn, Wm, [Xa|SP]
	0b10001000, 0b00100000, 0b10000000, 0b00000000, 4, CmdR16, CmdR0, CmdR10, CmdR5,
	// stlxp Wd, Xn, Xm, [Xa|SP]
	0b11001000, 0b00100000, 0b10000000, 0b00000000, 4, CmdR16, CmdR0, CmdR10, CmdR5,

	// stlxr Wd, Wn, [Xm|SP]
	0b10001000, 0b00000000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// stlxr Wd, Xn, [Xm|SP]
	0b11001000, 0b00000000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// stlxrb Wd, Wn, [Xm|SP]
	0b00001000, 0b00000000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// stlxrh Wd, Wn, [Xm|SP]
	0b01001000, 0b00000000, 0b11111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// stnp Sd, Sn, [Xm|SP {, #imm }]  ·································  (-256 <= imm < 256, imm >> 2)
	0b00101100, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// stnp Dd, Dn, [Xm|SP {, #imm }]  ·································  (-512 <= imm < 512, imm >> 3)
	0b01101100, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// stnp Qd, Qn, [Xm|SP {, #imm }]  ·······························  (-1024 <= imm < 1024, imm >> 4)
	0b10101100, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 4,
	// stnp Wd, Wn, [Xm|SP {, #imm }]  ·································  (-256 <= imm < 256, imm >> 2)
	0b00101000, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// stnp Xd, Xn, [Xm|SP {, #imm }]  ·································  (-512 <= imm < 512, imm >> 3)
	0b10101000, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,

	// stp Sd, Sn, [Xm|SP], #imm  ······································  (-256 <= imm < 256, imm >> 2)
	0b00101100, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// stp Dd, Dn, [Xm|SP], #imm  ······································  (-512 <= imm < 512, imm >> 3)
	0b01101100, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// stp Qd, Qn, [Xm|SP], #imm  ····································  (-1024 <= imm < 1024, imm >> 4)
	0b10101100, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 4,
	// stp Sd, Sn, [Xm|SP, #imm]!  ·····································  (-256 <= imm < 256, imm >> 2)
	0b00101101, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// stp Dd, Dn, [Xm|SP, #imm]!  ·····································  (-512 <= imm < 512, imm >> 3)
	0b01101101, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// stp Qd, Qn, [Xm|SP, #imm]!  ···································  (-1024 <= imm < 1024, imm >> 4)
	0b10101101, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 4,
	// stp Sd, Sn, [Xm|SP {, #imm }]  ··································  (-256 <= imm < 256, imm >> 2)
	0b00101101, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// stp Dd, Dn, [Xm|SP {, #imm }]  ··································  (-512 <= imm < 512, imm >> 3)
	0b01101101, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// stp Qd, Qn, [Xm|SP {, #imm }]  ································  (-1024 <= imm < 1024, imm >> 4)
	0b10101101, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 4,
	// stp Wd, Wn, [Xm|SP], #imm  ······································  (-256 <= imm < 256, imm >> 2)
	0b00101000, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// stp Xd, Xn, [Xm|SP], #imm  ······································  (-512 <= imm < 512, imm >> 3)
	0b10101000, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// stp Wd, Wn, [Xm|SP, #imm]!  ·····································  (-256 <= imm < 256, imm >> 2)
	0b00101001, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// stp Xd, Xn, [Xm|SP, #imm]!  ·····································  (-512 <= imm < 512, imm >> 3)
	0b10101001, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,
	// stp Wd, Wn, [Xm|SP {, #imm }]  ··································  (-256 <= imm < 256, imm >> 2)
	0b00101001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 2,
	// stp Xd, Xn, [Xm|SP {, #imm }]  ··································  (-512 <= imm < 512, imm >> 3)
	0b10101001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR10, CmdR5, CmdSscaled, 3,

	// str Bd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b00111100, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Hd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b01111100, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Sd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b10111100, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Dd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b11111100, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Qd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b00111100, 0b10000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Bd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b00111100, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Hd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b01111100, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Sd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b10111100, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Dd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b11111100, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Qd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b00111100, 0b10000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Bd, [Xn|SP {, #imm }]  ··················································  (0 <= imm < 4096)
	0b00111101, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 10, 12,
	// str Hd, [Xn|SP {, #imm }]  ········································  (0 <= imm < 8192, imm >> 1)
	0b01111101, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 1,
	// str Sd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 16384, imm >> 2)
	0b10111101, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 2,
	// str Dd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 32768, imm >> 3)
	0b11111101, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 3,
	// str Qd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 65536, imm >> 4)
	0b00111101, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 4,
	// str Wd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b10111000, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Xd, [Xn|SP], #imm  ····················································  (-256 <= imm < 256)
	0b11111000, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Wd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b10111000, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Xd, [Xn|SP, #imm]!  ···················································  (-256 <= imm < 256)
	0b11111000, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// str Wd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 16384, imm >> 2)
	0b10111001, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 2,
	// str Xd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 32768, imm >> 3)
	0b11111001, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 3,
	// str Bd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ·······························  (imm == 0)
	0b00111100, 0b00100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 0,
	// str Hd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 1])
	0b01111100, 0b00100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 1,
	// str Sd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 2])
	0b10111100, 0b00100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 2,
	// str Dd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 3])
	0b11111100, 0b00100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 3,
	// str Qd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 4])
	0b00111100, 0b10100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 4,
	// str Wd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 2])
	0b10111000, 0b00100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 2,
	// str Xd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ··························  (imm in [0, 3])
	0b11111000, 0b00100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 3,

	// strb Wd, [Xn|SP], #imm  ···················································  (-256 <= imm < 256)
	0b00111000, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// strb Wd, [Xn|SP, #imm]!  ··················································  (-256 <= imm < 256)
	0b00111000, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// strb Wd, [Xn|SP {, #imm }]  ·················································  (0 <= imm < 4096)
	0b00111001, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 10, 12,
	// strb Wd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ······························  (imm == 0)
	0b00111000, 0b00100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 0,

	// strh Wd, [Xn|SP], #imm  ···················································  (-256 <= imm < 256)
	0b01111000, 0b00000000, 0b00000100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// strh Wd, [Xn|SP, #imm]!  ··················································  (-256 <= imm < 256)
	0b01111000, 0b00000000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// strh Wd, [Xn|SP {, #imm }]  ·······································  (0 <= imm < 8192, imm >> 1)
	0b01111001, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUscaled, 10, 12, 1,
	// strh Wd, [Xn|SP, Wm|Xm {, LSL|UXTW|SXTW|SXTX #imm }]  ·························  (imm in [0, 1])
	0b01111000, 0b00100000, 0b00001000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUAlt2, 12, 1,

	// stset Wd, [Xn|SP]
	0b10111000, 0b00100000, 0b00110000, 0b00011111, 2, CmdR16, CmdR5,
	// stset Xd, [Xn|SP]
	0b11111000, 0b00100000, 0b00110000, 0b00011111, 2, CmdR16, CmdR5,

	// stsetb Wd, [Xn|SP]
	0b00111000, 0b00100000, 0b00110000, 0b00011111, 2, CmdR16, CmdR5,

	// stseth Wd, [Xn|SP]
	0b01111000, 0b00100000, 0b00110000, 0b00011111, 2, CmdR16, CmdR5,

	// stsetl Wd, [Xn|SP]
	0b10111000, 0b01100000, 0b00110000, 0b00011111, 2, CmdR16, CmdR5,
	// stsetl Xd, [Xn|SP]
	0b11111000, 0b01100000, 0b00110000, 0b00011111, 2, CmdR16, CmdR5,

	// stsetlb Wd, [Xn|SP]
	0b00111000, 0b01100000, 0b00110000, 0b00011111, 2, CmdR16, CmdR5,

	// stsetlh Wd, [Xn|SP]
	0b01111000, 0b01100000, 0b00110000, 0b00011111, 2, CmdR16, CmdR5,

	// stsmax Wd, [Xn|SP]
	0b10111000, 0b00100000, 0b01000000, 0b00011111, 2, CmdR16, CmdR5,
	// stsmax Xd, [Xn|SP]
	0b11111000, 0b00100000, 0b01000000, 0b00011111, 2, CmdR16, CmdR5,

	// stsmaxb Wd, [Xn|SP]
	0b00111000, 0b00100000, 0b01000000, 0b00011111, 2, CmdR16, CmdR5,

	// stsmaxh Wd, [Xn|SP]
	0b01111000, 0b00100000, 0b01000000, 0b00011111, 2, CmdR16, CmdR5,

	// stsmaxl Wd, [Xn|SP]
	0b10111000, 0b01100000, 0b01000000, 0b00011111, 2, CmdR16, CmdR5,
	// stsmaxl Xd, [Xn|SP]
	0b11111000, 0b01100000, 0b01000000, 0b00011111, 2, CmdR16, CmdR5,

	// stsmaxlb Wd, [Xn|SP]
	0b00111000, 0b01100000, 0b01000000, 0b00011111, 2, CmdR16, CmdR5,

	// stsmaxlh Wd, [Xn|SP]
	0b01111000, 0b01100000, 0b01000000, 0b00011111, 2, CmdR16, CmdR5,

	// stsmin Wd, [Xn|SP]
	0b10111000, 0b00100000, 0b01010000, 0b00011111, 2, CmdR16, CmdR5,
	// stsmin Xd, [Xn|SP]
	0b11111000, 0b00100000, 0b01010000, 0b00011111, 2, CmdR16, CmdR5,

	// stsminb Wd, [Xn|SP]
	0b00111000, 0b00100000, 0b01010000, 0b00011111, 2, CmdR16, CmdR5,

	// stsminh Wd, [Xn|SP]
	0b01111000, 0b00100000, 0b01010000, 0b00011111, 2, CmdR16, CmdR5,

	// stsminl Wd, [Xn|SP]
	0b10111000, 0b01100000, 0b01010000, 0b00011111, 2, CmdR16, CmdR5,
	// stsminl Xd, [Xn|SP]
	0b11111000, 0b01100000, 0b01010000, 0b00011111, 2, CmdR16, CmdR5,

	// stsminlb Wd, [Xn|SP]
	0b00111000, 0b01100000, 0b01010000, 0b00011111, 2, CmdR16, CmdR5,

	// stsminlh Wd, [Xn|SP]
	0b01111000, 0b01100000, 0b01010000, 0b00011111, 2, CmdR16, CmdR5,

	// sttr Wd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b10111000, 0b00000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// sttr Xd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b11111000, 0b00000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// sttrb Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b00111000, 0b00000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// sttrh Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b01111000, 0b00000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// stumax Wd, [Xn|SP]
	0b10111000, 0b00100000, 0b01100000, 0b00011111, 2, CmdR16, CmdR5,
	// stumax Xd, [Xn|SP]
	0b11111000, 0b00100000, 0b01100000, 0b00011111, 2, CmdR16, CmdR5,

	// stumaxb Wd, [Xn|SP]
	0b00111000, 0b00100000, 0b01100000, 0b00011111, 2, CmdR16, CmdR5,

	// stumaxh Wd, [Xn|SP]
	0b01111000, 0b00100000, 0b01100000, 0b00011111, 2, CmdR16, CmdR5,

	// stumaxl Wd, [Xn|SP]
	0b10111000, 0b01100000, 0b01100000, 0b00011111, 2, CmdR16, CmdR5,
	// stumaxl Xd, [Xn|SP]
	0b11111000, 0b01100000, 0b01100000, 0b00011111, 2, CmdR16, CmdR5,

	// stumaxlb Wd, [Xn|SP]
	0b00111000, 0b01100000, 0b01100000, 0b00011111, 2, CmdR16, CmdR5,

	// stumaxlh Wd, [Xn|SP]
	0b01111000, 0b01100000, 0b01100000, 0b00011111, 2, CmdR16, CmdR5,

	// stumin Wd, [Xn|SP]
	0b10111000, 0b00100000, 0b01110000, 0b00011111, 2, CmdR16, CmdR5,
	// stumin Xd, [Xn|SP]
	0b11111000, 0b00100000, 0b01110000, 0b00011111, 2, CmdR16, CmdR5,

	// stuminb Wd, [Xn|SP]
	0b00111000, 0b00100000, 0b01110000, 0b00011111, 2, CmdR16, CmdR5,

	// stuminh Wd, [Xn|SP]
	0b01111000, 0b00100000, 0b01110000, 0b00011111, 2, CmdR16, CmdR5,

	// stuminl Wd, [Xn|SP]
	0b10111000, 0b01100000, 0b01110000, 0b00011111, 2, CmdR16, CmdR5,
	// stuminl Xd, [Xn|SP]
	0b11111000, 0b01100000, 0b01110000, 0b00011111, 2, CmdR16, CmdR5,

	// stuminlb Wd, [Xn|SP]
	0b00111000, 0b01100000, 0b01110000, 0b00011111, 2, CmdR16, CmdR5,

	// stuminlh Wd, [Xn|SP]
	0b01111000, 0b01100000, 0b01110000, 0b00011111, 2, CmdR16, CmdR5,

	// stur Bd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b00111100, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// stur Hd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b01111100, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// stur Sd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b10111100, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// stur Dd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b11111100, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// stur Qd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b00111100, 0b10000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// stur Wd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b10111000, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,
	// stur Xd, [Xn|SP {, #imm }]  ···············································  (-256 <= imm < 256)
	0b11111000, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// sturb Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b00111000, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// sturh Wd, [Xn|SP {, #imm }]  ··············································  (-256 <= imm < 256)
	0b01111000, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdSbits,

	// stxp Wd, Wn, Wm, [Xa|SP]
	0b10001000, 0b00100000, 0b00000000, 0b00000000, 4, CmdR16, CmdR0, CmdR10, CmdR5,
	// stxp Wd, Xn, Xm, [Xa|SP]
	0b11001000, 0b00100000, 0b00000000, 0b00000000, 4, CmdR16, CmdR0, CmdR10, CmdR5,

	// stxr Wd, Wn, [Xm|SP]
	0b10001000, 0b00000000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// stxr Wd, Xn, [Xm|SP]
	0b11001000, 0b00000000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// stxrb Wd, Wn, [Xm|SP]
	0b00001000, 0b00000000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// stxrh Wd, Wn, [Xm|SP]
	0b01001000, 0b00000000, 0b01111100, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// sub Wd, Wn, Wm {, LSL|LSR|ASR #imm }  ·········································  (0 <= imm < 32)
	0b01001011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// sub Xd, Xn, Xm {, LSL|LSR|ASR #imm }  ·········································  (0 <= imm < 64)
	0b11001011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,
	// sub Wd|WSP, Wn|WSP, Wm {, LSL|UXT[BHWX]|SXT[BHWX] #imm }  ·····················  (0 <= imm <= 4)
	0b01001011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsW, CmdUrange, 10, 0, 4,
	// sub Xd|SP, Xn|SP, Wm {, UXT[BHW]|SXT[BHW] #imm }  ·····························  (0 <= imm <= 4)
	0b11001011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// sub Xd|SP, Xn|SP, Xm {, LSL|UXTX|SXTX #imm }  ·································  (0 <= imm <= 4)
	0b11001011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// sub Wd|WSP, Wn|WSP, #imm1 {, LSL #imm2 }  ·················  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b01010001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,
	// sub Xd|SP, Xn|SP, #imm1 {, LSL #imm2 }  ···················  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b11010001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,
	// sub Dd, Dn, Dm
	0b01111110, 0b11100000, 0b10000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// sub Vd.16B, Vn.16B, Vm.16B
	// sub Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sub Vd.8H, Vn.8H, Vm.8H
	// sub Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sub Vd.4S, Vn.4S, Vm.4S
	// sub Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// sub Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b10000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// subhn Vd.8B, Vn.8H, Vm.8H
	0b00001110, 0b00100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// subhn Vd.4H, Vn.4S, Vm.4S
	0b00001110, 0b01100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// subhn Vd.2S, Vn.2D, Vm.2D
	0b00001110, 0b10100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// subhn2 Vd.16B, Vn.8H, Vm.8H
	0b01001110, 0b00100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// subhn2 Vd.8H, Vn.4S, Vm.4S
	0b01001110, 0b01100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// subhn2 Vd.4S, Vn.2D, Vm.2D
	0b01001110, 0b10100000, 0b01100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// subs Wd, Wn, Wm {, LSL|LSR|ASR #imm }  ········································  (0 <= imm < 32)
	0b01101011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// subs Xd, Xn, Xm {, LSL|LSR|ASR #imm }  ········································  (0 <= imm < 64)
	0b11101011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,
	// subs Wd, Wn|WSP, Wm {, LSL|UXT[BHWX]|SXT[BHWX] #imm }  ························  (0 <= imm <= 4)
	0b01101011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsW, CmdUrange, 10, 0, 4,
	// subs Xd, Xn|SP, Wm {, UXT[BHW]|SXT[BHW] #imm }  ·······························  (0 <= imm <= 4)
	0b11101011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// subs Xd, Xn|SP, Xm {, LSL|UXTX|SXTX #imm }  ···································  (0 <= imm <= 4)
	0b11101011, 0b00100000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdR16, CmdExtendsX, CmdUrange, 10, 0, 4,
	// subs Wd, Wn|WSP, #imm1 {, LSL #imm2 }  ····················  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b01110001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,
	// subs Xd, Xn|SP, #imm1 {, LSL #imm2 }  ·····················  (0 <= imm1 < 4096, imm2 in [0, 12])
	0b11110001, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 10, 12, CmdUAlt2, 22, 6,

	// suqadd Bd, Bn
	0b01011110, 0b00100000, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// suqadd Hd, Hn
	0b01011110, 0b01100000, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// suqadd Sd, Sn
	0b01011110, 0b10100000, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// suqadd Dd, Dn
	0b01011110, 0b11100000, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// suqadd Vd.16B, Vn.16B
	// suqadd Vd.8B, Vn.8B
	0b00001110, 0b00100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// suqadd Vd.8H, Vn.8H
	// suqadd Vd.4H, Vn.4H
	0b00001110, 0b01100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// suqadd Vd.4S, Vn.4S
	// suqadd Vd.2S, Vn.2S
	0b00001110, 0b10100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// suqadd Vd.2D, Vn.2D
	0b00001110, 0b11100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// svc #imm  ··································································  (0 <= imm < 65536)
	0b11010100, 0b00000000, 0b00000000, 0b00000001, 1, CmdUbits, 5, 16,

	// swp Wd, Wn, [Xm|SP]
	0b10111000, 0b00100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// swp Xd, Xn, [Xm|SP]
	0b11111000, 0b00100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swpa Wd, Wn, [Xm|SP]
	0b10111000, 0b10100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// swpa Xd, Xn, [Xm|SP]
	0b11111000, 0b10100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swpab Wd, Wn, [Xm|SP]
	0b00111000, 0b10100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swpah Wd, Wn, [Xm|SP]
	0b01111000, 0b10100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swpal Wd, Wn, [Xm|SP]
	0b10111000, 0b11100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// swpal Xd, Xn, [Xm|SP]
	0b11111000, 0b11100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swpalb Wd, Wn, [Xm|SP]
	0b00111000, 0b11100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swpalh Wd, Wn, [Xm|SP]
	0b01111000, 0b11100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swpb Wd, Wn, [Xm|SP]
	0b00111000, 0b00100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swph Wd, Wn, [Xm|SP]
	0b01111000, 0b00100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swpl Wd, Wn, [Xm|SP]
	0b10111000, 0b01100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,
	// swpl Xd, Xn, [Xm|SP]
	0b11111000, 0b01100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swplb Wd, Wn, [Xm|SP]
	0b00111000, 0b01100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// swplh Wd, Wn, [Xm|SP]
	0b01111000, 0b01100000, 0b10000000, 0b00000000, 3, CmdR16, CmdR0, CmdR5,

	// sxtb Wd, Wn
	0b00010011, 0b00000000, 0b00011100, 0b00000000, 2, CmdR0, CmdR5,
	// sxtb Xd, Wn
	0b10010011, 0b01000000, 0b00011100, 0b00000000, 2, CmdR0, CmdR5,

	// sxth Wd, Wn
	0b00010011, 0b00000000, 0b00111100, 0b00000000, 2, CmdR0, CmdR5,
	// sxth Xd, Wn
	0b10010011, 0b01000000, 0b00111100, 0b00000000, 2, CmdR0, CmdR5,

	// sxtl Vd.8H, Vn.8B
	0b00001111, 0b00001000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// sxtl Vd.4S, Vn.4H
	0b00001111, 0b00010000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// sxtl Vd.2D, Vn.2S
	0b00001111, 0b00100000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,

	// sxtl2 Vd.8H, Vn.16B
	0b01001111, 0b00001000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// sxtl2 Vd.4S, Vn.8H
	0b01001111, 0b00010000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// sxtl2 Vd.2D, Vn.4S
	0b01001111, 0b00100000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,

	// sxtw Xd, Wn
	0b10010011, 0b01000000, 0b01111100, 0b00000000, 2, CmdR0, CmdR5,

	// sys #imm1, <symbol>, <symbol>, #imm2 {, Xn }  ··················  (0 <= imm1 < 8, 0 <= imm2 < 8)
	0b11010101, 0b00001000, 0b00000000, 0b00000000, 5, CmdUbits, 16, 3, CmdLitList, 12, SymCONTROLREGS, CmdLitList, 8, SymCONTROLREGS, CmdUbits, 5, 3, CmdR0,

	// sysl Xd, #imm1, <symbol>, <symbol>, #imm2  ·····················  (0 <= imm1 < 8, 0 <= imm2 < 8)
	0b11010101, 0b00101000, 0b00000000, 0b00000000, 5, CmdR0, CmdUbits, 16, 3, CmdLitList, 12, SymCONTROLREGS, CmdLitList, 8, SymCONTROLREGS, CmdUbits, 5, 3,

	// tbl Vd.16B, {Vn.16B * 2}, Vm.16B
	// tbl Vd.8B, {Vn.16B * 2}, Vm.8B
	0b00001110, 0b00000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// tbl Vd.16B, {Vn.16B * 3}, Vm.16B
	// tbl Vd.8B, {Vn.16B * 3}, Vm.8B
	0b00001110, 0b00000000, 0b01000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// tbl Vd.16B, {Vn.16B * 4}, Vm.16B
	// tbl Vd.8B, {Vn.16B * 4}, Vm.8B
	0b00001110, 0b00000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// tbl Vd.16B, {Vn.16B * 1}, Vm.16B
	// tbl Vd.8B, {Vn.16B * 1}, Vm.8B
	0b00001110, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// tbnz Wd, #imm, <offset>  ···················  (0 <= imm < 32, offset >> 2 is 14-bit (+/- 32 KB))
	0b00110111, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUbits, 19, 5, CmdOffset, RelTbz,
	// tbnz Xd, #imm, <offset>  ···················  (0 <= imm < 64, offset >> 2 is 14-bit (+/- 32 KB))
	0b00110111, 0b00000000, 0b00000000, 0b00000000, 6, CmdR0, CmdChkUbits, 6, CmdUslice, 19, 5, 0, CmdUslice, 31, 1, 5, CmdAdv, CmdOffset, RelTbz,

	// tbx Vd.16B, {Vn.16B * 2}, Vm.16B
	// tbx Vd.8B, {Vn.16B * 2}, Vm.8B
	0b00001110, 0b00000000, 0b00110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// tbx Vd.16B, {Vn.16B * 3}, Vm.16B
	// tbx Vd.8B, {Vn.16B * 3}, Vm.8B
	0b00001110, 0b00000000, 0b01010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// tbx Vd.16B, {Vn.16B * 4}, Vm.16B
	// tbx Vd.8B, {Vn.16B * 4}, Vm.8B
	0b00001110, 0b00000000, 0b01110000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// tbx Vd.16B, {Vn.16B * 1}, Vm.16B
	// tbx Vd.8B, {Vn.16B * 1}, Vm.8B
	0b00001110, 0b00000000, 0b00010000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// tbz Wd, #imm, <offset>  ····················  (0 <= imm < 32, offset >> 2 is 14-bit (+/- 32 KB))
	0b00110110, 0b00000000, 0b00000000, 0b00000000, 3, CmdR0, CmdUbits, 19, 5, CmdOffset, RelTbz,
	// tbz Xd, #imm, <offset>  ····················  (0 <= imm < 64, offset >> 2 is 14-bit (+/- 32 KB))
	0b00110110, 0b00000000, 0b00000000, 0b00000000, 6, CmdR0, CmdChkUbits, 6, CmdUslice, 19, 5, 0, CmdUslice, 31, 1, 5, CmdAdv, CmdOffset, RelTbz,

	// tlbi <symbol> {, Xn }
	0b11010101, 0b00001000, 0b10000000, 0b00000000, 2, CmdLitList, 5, SymTLBIOPS, CmdR0,

	// trn1 Vd.16B, Vn.16B, Vm.16B
	// trn1 Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00000000, 0b00101000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// trn1 Vd.8H, Vn.8H, Vm.8H
	// trn1 Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00101000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// trn1 Vd.4S, Vn.4S, Vm.4S
	// trn1 Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10000000, 0b00101000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// trn1 Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11000000, 0b00101000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// trn2 Vd.16B, Vn.16B, Vm.16B
	// trn2 Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00000000, 0b01101000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// trn2 Vd.8H, Vn.8H, Vm.8H
	// trn2 Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b01101000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// trn2 Vd.4S, Vn.4S, Vm.4S
	// trn2 Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10000000, 0b01101000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// trn2 Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11000000, 0b01101000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// tsb CSYNC
	0b11010101, 0b00000011, 0b00100010, 0b01011111, 0,

	// tst Wd, #imm  ·························································  (imm is 32-bit logical)
	0b01110010, 0b00000000, 0b00000000, 0b00011111, 2, CmdR5, CmdSpecial, 10, SpecialImmLogical32,
	// tst Xd, #imm  ·························································  (imm is 64-bit logical)
	0b11110010, 0b00000000, 0b00000000, 0b00011111, 2, CmdR5, CmdSpecial, 10, SpecialImmLogical64,
	// tst Wd, Wn {, LSL|LSR|ASR|ROR #imm }  ·········································  (0 <= imm < 32)
	0b01101010, 0b00000000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 5,
	// tst Xd, Xn {, LSL|LSR|ASR|ROR #imm }  ·········································  (0 <= imm < 64)
	0b11101010, 0b00000000, 0b00000000, 0b00011111, 4, CmdR5, CmdR16, CmdRotates, CmdUbits, 10, 6,

	// uaba Vd.16B, Vn.16B, Vm.16B
	// uaba Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uaba Vd.8H, Vn.8H, Vm.8H
	// uaba Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uaba Vd.4S, Vn.4S, Vm.4S
	// uaba Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01111100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uabal Vd.8H, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uabal Vd.4S, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uabal Vd.2D, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uabal2 Vd.8H, Vn.16B, Vm.16B
	0b01101110, 0b00100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uabal2 Vd.4S, Vn.8H, Vm.8H
	0b01101110, 0b01100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uabal2 Vd.2D, Vn.4S, Vm.4S
	0b01101110, 0b10100000, 0b01010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uabd Vd.16B, Vn.16B, Vm.16B
	// uabd Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uabd Vd.8H, Vn.8H, Vm.8H
	// uabd Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uabd Vd.4S, Vn.4S, Vm.4S
	// uabd Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uabdl Vd.8H, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uabdl Vd.4S, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uabdl Vd.2D, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uabdl2 Vd.8H, Vn.16B, Vm.16B
	0b01101110, 0b00100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uabdl2 Vd.4S, Vn.8H, Vm.8H
	0b01101110, 0b01100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uabdl2 Vd.2D, Vn.4S, Vm.4S
	0b01101110, 0b10100000, 0b01110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uadalp Vd.8H, Vn.16B
	// uadalp Vd.4H, Vn.8B
	0b00101110, 0b00100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// uadalp Vd.4S, Vn.8H
	// uadalp Vd.2S, Vn.4H
	0b00101110, 0b01100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// uadalp Vd.2D, Vn.4S
	// uadalp Vd.1D, Vn.2S
	0b00101110, 0b10100000, 0b01101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// uaddl Vd.8H, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uaddl Vd.4S, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uaddl Vd.2D, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uaddl2 Vd.8H, Vn.16B, Vm.16B
	0b01101110, 0b00100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uaddl2 Vd.4S, Vn.8H, Vm.8H
	0b01101110, 0b01100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uaddl2 Vd.2D, Vn.4S, Vm.4S
	0b01101110, 0b10100000, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uaddlp Vd.8H, Vn.16B
	// uaddlp Vd.4H, Vn.8B
	0b00101110, 0b00100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// uaddlp Vd.4S, Vn.8H
	// uaddlp Vd.2S, Vn.4H
	0b00101110, 0b01100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// uaddlp Vd.2D, Vn.4S
	// uaddlp Vd.1D, Vn.2S
	0b00101110, 0b10100000, 0b00101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// uaddlv Hd, Vn.16B
	// uaddlv Hd, Vn.8B
	0b00101110, 0b00110000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// uaddlv Sd, Vn.8H
	// uaddlv Sd, Vn.4H
	0b00101110, 0b01110000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// uaddlv Dd, Vn.4S
	0b00101110, 0b10110000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// uaddw Vd.8H, Vn.8H, Vm.8B
	0b00101110, 0b00100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uaddw Vd.4S, Vn.4S, Vm.4H
	0b00101110, 0b01100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uaddw Vd.2D, Vn.2D, Vm.2S
	0b00101110, 0b10100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uaddw2 Vd.8H, Vn.8H, Vm.16B
	0b01101110, 0b00100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uaddw2 Vd.4S, Vn.4S, Vm.8H
	0b01101110, 0b01100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uaddw2 Vd.2D, Vn.2D, Vm.4S
	0b01101110, 0b10100000, 0b00010000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// ubfiz Wd, Wn, #imm1, #imm2  ···············  (0 <= imm1 < 32, 0 < imm2 <= 32, imm1 + imm2 <= 32)
	0b01010011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUnegmod, 16, 5, CmdChkUsum, 5, CmdUrange, 10, 1, 32,
	// ubfiz Xd, Xn, #imm1, #imm2  ···············  (0 <= imm1 < 64, 0 < imm2 <= 64, imm1 + imm2 <= 64)
	0b11010011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUnegmod, 16, 6, CmdChkUsum, 6, CmdUrange, 10, 1, 64,

	// ubfm Wd, Wn, #imm1, #imm2  ···································  (0 <= imm1 < 32, 0 <= imm2 < 32)
	0b01010011, 0b00000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 5, CmdUbits, 10, 5,
	// ubfm Xd, Xn, #imm1, #imm2  ·················  (0 <= imm1 < 64, 0 < imm2 < 64, imm1 + imm2 <= 64)
	0b11010011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 6, CmdChkUsum, 6, CmdUbits, 10, 6,

	// ubfx Wd, Wn, #imm1, #imm2  ················  (0 <= imm1 < 32, 0 < imm2 <= 32, imm1 + imm2 <= 32)
	0b01010011, 0b00000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 5, CmdChkUsum, 5, CmdUsumdec, 10, 5,
	// ubfx Xd, Xn, #imm1, #imm2  ················  (0 <= imm1 < 64, 0 < imm2 <= 64, imm1 + imm2 <= 64)
	0b11010011, 0b01000000, 0b00000000, 0b00000000, 5, CmdR0, CmdR5, CmdUbits, 16, 6, CmdChkUsum, 6, CmdUsumdec, 10, 6,

	// ucvtf Hd, Hn, #imm  ···························································  (0 < imm <= 16)
	0b01111111, 0b00000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// ucvtf Sd, Sn, #imm  ···························································  (0 < imm <= 32)
	0b01111111, 0b00000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// ucvtf Dd, Dn, #imm  ···························································  (0 < imm <= 64)
	0b01111111, 0b00000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// ucvtf Vd.8H, Vn.8H, #imm  ·····················································  (0 < imm <= 16)
	// ucvtf Vd.4H, Vn.4H, #imm  ·····················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// ucvtf Vd.4S, Vn.4S, #imm  ·····················································  (0 < imm <= 32)
	// ucvtf Vd.2S, Vn.2S, #imm  ·····················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// ucvtf Vd.2D, Vn.2D, #imm  ·····················································  (0 < imm <= 64)
	0b00101111, 0b01000000, 0b11100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,
	// ucvtf Hd, Hn
	0b01111110, 0b01111001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// ucvtf Sd, Sn
	0b01111110, 0b00100001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// ucvtf Dd, Dn
	0b01111110, 0b01100001, 0b11011000, 0b00000000, 2, CmdR0, CmdR5,
	// ucvtf Vd.8H, Vn.8H
	// ucvtf Vd.4H, Vn.4H
	0b00101110, 0b01111001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ucvtf Vd.4S, Vn.4S
	// ucvtf Vd.2S, Vn.2S
	0b00101110, 0b00100001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ucvtf Vd.2D, Vn.2D
	0b00101110, 0b01100001, 0b11011000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// ucvtf Hd, Wn, #imm  ···························································  (0 < imm <= 32)
	0b00011110, 0b11000011, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// ucvtf Sd, Wn, #imm  ···························································  (0 < imm <= 32)
	0b00011110, 0b00000011, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// ucvtf Dd, Wn, #imm  ···························································  (0 < imm <= 32)
	0b00011110, 0b01000011, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 10, 6, 64,
	// ucvtf Hd, Xn, #imm  ···························································  (0 < imm <= 64)
	0b10011110, 0b11000011, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// ucvtf Sd, Xn, #imm  ···························································  (0 < imm <= 64)
	0b10011110, 0b00000011, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// ucvtf Dd, Xn, #imm  ···························································  (0 < imm <= 64)
	0b10011110, 0b01000011, 0b00000000, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 10, 6, 64,
	// ucvtf Hd, Wn
	0b00011110, 0b11100011, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// ucvtf Sd, Wn
	0b00011110, 0b00100011, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// ucvtf Dd, Wn
	0b00011110, 0b01100011, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// ucvtf Hd, Xn
	0b10011110, 0b11100011, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// ucvtf Sd, Xn
	0b10011110, 0b00100011, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,
	// ucvtf Dd, Xn
	0b10011110, 0b01100011, 0b00000000, 0b00000000, 2, CmdR0, CmdR5,

	// udf #imm  ··································································  (0 <= imm < 65536)
	0b00000000, 0b00000000, 0b00000000, 0b00000000, 1, CmdUbits, 0, 16,

	// udiv Wd, Wn, Wm
	0b00011010, 0b11000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// udiv Xd, Xn, Xm
	0b10011010, 0b11000000, 0b00001000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// udot Vd.2S, Vn.8B, Vm.4B[i]
	0b00101111, 0b10000000, 0b11100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// udot Vd.4S, Vn.16B, Vm.4B[i]
	0b01101111, 0b10000000, 0b11100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// udot Vd.2S, Vn.8B, Vm.8B
	0b00101110, 0b10000000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// udot Vd.4S, Vn.16B, Vm.16B
	0b01101110, 0b10000000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uhadd Vd.16B, Vn.16B, Vm.16B
	// uhadd Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uhadd Vd.8H, Vn.8H, Vm.8H
	// uhadd Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uhadd Vd.4S, Vn.4S, Vm.4S
	// uhadd Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uhsub Vd.16B, Vn.16B, Vm.16B
	// uhsub Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uhsub Vd.8H, Vn.8H, Vm.8H
	// uhsub Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uhsub Vd.4S, Vn.4S, Vm.4S
	// uhsub Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// umaddl Xd, Wn, Wm, Xa
	0b10011011, 0b10100000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// umax Vd.16B, Vn.16B, Vm.16B
	// umax Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// umax Vd.8H, Vn.8H, Vm.8H
	// umax Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// umax Vd.4S, Vn.4S, Vm.4S
	// umax Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// umaxp Vd.16B, Vn.16B, Vm.16B
	// umaxp Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b10100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// umaxp Vd.8H, Vn.8H, Vm.8H
	// umaxp Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b10100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// umaxp Vd.4S, Vn.4S, Vm.4S
	// umaxp Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b10100100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// umaxv Bd, Vn.16B
	// umaxv Bd, Vn.8B
	0b00101110, 0b00110000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// umaxv Hd, Vn.8H
	// umaxv Hd, Vn.4H
	0b00101110, 0b01110000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// umaxv Sd, Vn.4S
	0b00101110, 0b10110000, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// umin Vd.16B, Vn.16B, Vm.16B
	// umin Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// umin Vd.8H, Vn.8H, Vm.8H
	// umin Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// umin Vd.4S, Vn.4S, Vm.4S
	// umin Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uminp Vd.16B, Vn.16B, Vm.16B
	// uminp Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b10101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uminp Vd.8H, Vn.8H, Vm.8H
	// uminp Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b10101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uminp Vd.4S, Vn.4S, Vm.4S
	// uminp Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b10101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uminv Bd, Vn.16B
	// uminv Bd, Vn.8B
	0b00101110, 0b00110001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// uminv Hd, Vn.8H
	// uminv Hd, Vn.4H
	0b00101110, 0b01110001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// uminv Sd, Vn.4S
	0b00101110, 0b10110001, 0b10101000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// umlal Vd.4S, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b00101111, 0b01000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// umlal Vd.2D, Vn.2S, Vm.S[i]
	0b00101111, 0b10000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// umlal Vd.8H, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umlal Vd.4S, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umlal Vd.2D, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// umlal2 Vd.4S, Vn.8H, Vm.H[i]  ························································  (m < 16)
	0b01101111, 0b01000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// umlal2 Vd.2D, Vn.4S, Vm.S[i]
	0b01101111, 0b10000000, 0b00100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// umlal2 Vd.8H, Vn.16B, Vm.16B
	0b01101110, 0b00100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umlal2 Vd.4S, Vn.8H, Vm.8H
	0b01101110, 0b01100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umlal2 Vd.2D, Vn.4S, Vm.4S
	0b01101110, 0b10100000, 0b10000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// umlsl Vd.4S, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b00101111, 0b01000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// umlsl Vd.2D, Vn.2S, Vm.S[i]
	0b00101111, 0b10000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// umlsl Vd.8H, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umlsl Vd.4S, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umlsl Vd.2D, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// umlsl2 Vd.4S, Vn.8H, Vm.H[i]  ························································  (m < 16)
	0b01101111, 0b01000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// umlsl2 Vd.2D, Vn.4S, Vm.S[i]
	0b01101111, 0b10000000, 0b01100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// umlsl2 Vd.8H, Vn.16B, Vm.16B
	0b01101110, 0b00100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umlsl2 Vd.4S, Vn.8H, Vm.8H
	0b01101110, 0b01100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umlsl2 Vd.2D, Vn.4S, Vm.4S
	0b01101110, 0b10100000, 0b10100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// umnegl Xd, Wn, Wm
	0b10011011, 0b10100000, 0b11111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// umov Wd, Vn.B[i]
	0b00001110, 0b00000001, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 17, 4,
	// umov Wd, Vn.H[i]
	0b00001110, 0b00000010, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 18, 3,
	// umov Wd, Vn.S[i]
	0b00001110, 0b00000100, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 19, 2,
	// umov Xd, Vn.D[i]
	0b01001110, 0b00001000, 0b00111100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 20, 1,

	// umsubl Xd, Wn, Wm, Xa
	0b10011011, 0b10100000, 0b10000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdR10,

	// umulh Xd, Xn, Xm
	0b10011011, 0b11000000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// umull Vd.4S, Vn.4H, Vm.H[i]  ·························································  (m < 16)
	0b00101111, 0b01000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// umull Vd.2D, Vn.2S, Vm.S[i]
	0b00101111, 0b10000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// umull Vd.8H, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umull Vd.4S, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umull Vd.2D, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umull Xd, Wn, Wm
	0b10011011, 0b10100000, 0b01111100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// umull2 Vd.4S, Vn.8H, Vm.H[i]  ························································  (m < 16)
	0b01101111, 0b01000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdRLo16, CmdUfields11, 3,
	// umull2 Vd.2D, Vn.4S, Vm.S[i]
	0b01101111, 0b10000000, 0b10100000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUfields11, 2,
	// umull2 Vd.8H, Vn.16B, Vm.16B
	0b01101110, 0b00100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umull2 Vd.4S, Vn.8H, Vm.8H
	0b01101110, 0b01100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// umull2 Vd.2D, Vn.4S, Vm.4S
	0b01101110, 0b10100000, 0b11000000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uqadd Bd, Bn, Bm
	0b01111110, 0b00100000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqadd Hd, Hn, Hm
	0b01111110, 0b01100000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqadd Sd, Sn, Sm
	0b01111110, 0b10100000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqadd Dd, Dn, Dm
	0b01111110, 0b11100000, 0b00001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqadd Vd.16B, Vn.16B, Vm.16B
	// uqadd Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqadd Vd.8H, Vn.8H, Vm.8H
	// uqadd Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqadd Vd.4S, Vn.4S, Vm.4S
	// uqadd Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqadd Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b00001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uqrshl Bd, Bn, Bm
	0b01111110, 0b00100000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqrshl Hd, Hn, Hm
	0b01111110, 0b01100000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqrshl Sd, Sn, Sm
	0b01111110, 0b10100000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqrshl Dd, Dn, Dm
	0b01111110, 0b11100000, 0b01011100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqrshl Vd.16B, Vn.16B, Vm.16B
	// uqrshl Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqrshl Vd.8H, Vn.8H, Vm.8H
	// uqrshl Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqrshl Vd.4S, Vn.4S, Vm.4S
	// uqrshl Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqrshl Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b01011100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uqrshrn Bd, Hn, #imm  ··························································  (0 < imm <= 8)
	0b01111111, 0b00000000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 8, CmdUsub, 16, 4, 16,
	// uqrshrn Hd, Sn, #imm  ·························································  (0 < imm <= 16)
	0b01111111, 0b00000000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// uqrshrn Sd, Dn, #imm  ·························································  (0 < imm <= 32)
	0b01111111, 0b00000000, 0b10011100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// uqrshrn Vd.8B, Vn.8H, #imm  ····················································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// uqrshrn Vd.4H, Vn.4S, #imm  ···················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// uqrshrn Vd.2S, Vn.2D, #imm  ···················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// uqrshrn2 Vd.16B, Vn.8H, #imm  ··················································  (0 < imm <= 8)
	0b01101111, 0b00001000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// uqrshrn2 Vd.8H, Vn.4S, #imm  ··················································  (0 < imm <= 16)
	0b01101111, 0b00010000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// uqrshrn2 Vd.4S, Vn.2D, #imm  ··················································  (0 < imm <= 32)
	0b01101111, 0b00100000, 0b10011100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// uqshl Bd, Bn, #imm  ····························································  (0 <= imm < 8)
	0b01111111, 0b00001000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 3,
	// uqshl Hd, Hn, #imm  ···························································  (0 <= imm < 16)
	0b01111111, 0b00010000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 4,
	// uqshl Sd, Sn, #imm  ···························································  (0 <= imm < 32)
	0b01111111, 0b00100000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,
	// uqshl Dd, Dn, #imm  ···························································  (0 <= imm < 64)
	0b01111111, 0b01000000, 0b01110100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 6,
	// uqshl Vd.16B, Vn.16B, #imm  ····················································  (0 <= imm < 8)
	// uqshl Vd.8B, Vn.8B, #imm  ······················································  (0 <= imm < 8)
	0b00101111, 0b00001000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 3, CmdRwidth30,
	// uqshl Vd.8H, Vn.8H, #imm  ·····················································  (0 <= imm < 16)
	// uqshl Vd.4H, Vn.4H, #imm  ·····················································  (0 <= imm < 16)
	0b00101111, 0b00010000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 4, CmdRwidth30,
	// uqshl Vd.4S, Vn.4S, #imm  ·····················································  (0 <= imm < 32)
	// uqshl Vd.2S, Vn.2S, #imm  ·····················································  (0 <= imm < 32)
	0b00101111, 0b00100000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 5, CmdRwidth30,
	// uqshl Vd.2D, Vn.2D, #imm  ·····················································  (0 <= imm < 64)
	0b00101111, 0b01000000, 0b01110100, 0b00000000, 4, CmdR0, CmdR5, CmdUbits, 16, 6, CmdRwidth30,
	// uqshl Bd, Bn, Bm
	0b01111110, 0b00100000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqshl Hd, Hn, Hm
	0b01111110, 0b01100000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqshl Sd, Sn, Sm
	0b01111110, 0b10100000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqshl Dd, Dn, Dm
	0b01111110, 0b11100000, 0b01001100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqshl Vd.16B, Vn.16B, Vm.16B
	// uqshl Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqshl Vd.8H, Vn.8H, Vm.8H
	// uqshl Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqshl Vd.4S, Vn.4S, Vm.4S
	// uqshl Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqshl Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b01001100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uqshrn Bd, Hn, #imm  ···························································  (0 < imm <= 8)
	0b01111111, 0b00000000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 8, CmdUsub, 16, 4, 16,
	// uqshrn Hd, Sn, #imm  ··························································  (0 < imm <= 16)
	0b01111111, 0b00000000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 16, CmdUsub, 16, 5, 32,
	// uqshrn Sd, Dn, #imm  ··························································  (0 < imm <= 32)
	0b01111111, 0b00000000, 0b10010100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 32, CmdUsub, 16, 6, 64,
	// uqshrn Vd.8B, Vn.8H, #imm  ·····················································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// uqshrn Vd.4H, Vn.4S, #imm  ····················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// uqshrn Vd.2S, Vn.2D, #imm  ····················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// uqshrn2 Vd.16B, Vn.8H, #imm  ···················································  (0 < imm <= 8)
	0b01101111, 0b00001000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 3, 8,
	// uqshrn2 Vd.8H, Vn.4S, #imm  ···················································  (0 < imm <= 16)
	0b01101111, 0b00010000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 4, 16,
	// uqshrn2 Vd.4S, Vn.2D, #imm  ···················································  (0 < imm <= 32)
	0b01101111, 0b00100000, 0b10010100, 0b00000000, 3, CmdR0, CmdR5, CmdUsub, 16, 5, 32,

	// uqsub Bd, Bn, Bm
	0b01111110, 0b00100000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqsub Hd, Hn, Hm
	0b01111110, 0b01100000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqsub Sd, Sn, Sm
	0b01111110, 0b10100000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqsub Dd, Dn, Dm
	0b01111110, 0b11100000, 0b00101100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// uqsub Vd.16B, Vn.16B, Vm.16B
	// uqsub Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqsub Vd.8H, Vn.8H, Vm.8H
	// uqsub Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqsub Vd.4S, Vn.4S, Vm.4S
	// uqsub Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uqsub Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b00101100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uqxtn Bd, Hn
	0b01111110, 0b00100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// uqxtn Hd, Sn
	0b01111110, 0b01100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// uqxtn Sd, Dn
	0b01111110, 0b10100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// uqxtn Vd.8B, Vn.8H
	0b00101110, 0b00100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// uqxtn Vd.4H, Vn.4S
	0b00101110, 0b01100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// uqxtn Vd.2S, Vn.2D
	0b00101110, 0b10100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,

	// uqxtn2 Vd.16B, Vn.8H
	0b01101110, 0b00100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// uqxtn2 Vd.8H, Vn.4S
	0b01101110, 0b01100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,
	// uqxtn2 Vd.4S, Vn.2D
	0b01101110, 0b10100001, 0b01001000, 0b00000000, 2, CmdR0, CmdR5,

	// urecpe Vd.4S, Vn.4S
	// urecpe Vd.2S, Vn.2S
	0b00001110, 0b10100001, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// urhadd Vd.16B, Vn.16B, Vm.16B
	// urhadd Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// urhadd Vd.8H, Vn.8H, Vm.8H
	// urhadd Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// urhadd Vd.4S, Vn.4S, Vm.4S
	// urhadd Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// urshl Dd, Dn, Dm
	0b01111110, 0b11100000, 0b01010100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// urshl Vd.16B, Vn.16B, Vm.16B
	// urshl Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// urshl Vd.8H, Vn.8H, Vm.8H
	// urshl Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// urshl Vd.4S, Vn.4S, Vm.4S
	// urshl Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// urshl Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b01010100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// urshr Dd, Dn, #imm  ···························································  (0 < imm <= 64)
	0b01111111, 0b00000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// urshr Vd.16B, Vn.16B, #imm  ····················································  (0 < imm <= 8)
	// urshr Vd.8B, Vn.8B, #imm  ······················································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// urshr Vd.8H, Vn.8H, #imm  ·····················································  (0 < imm <= 16)
	// urshr Vd.4H, Vn.4H, #imm  ·····················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// urshr Vd.4S, Vn.4S, #imm  ·····················································  (0 < imm <= 32)
	// urshr Vd.2S, Vn.2S, #imm  ·····················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// urshr Vd.2D, Vn.2D, #imm  ·····················································  (0 < imm <= 64)
	0b00101111, 0b01000000, 0b00100100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// ursqrte Vd.4S, Vn.4S
	// ursqrte Vd.2S, Vn.2S
	0b00101110, 0b10100001, 0b11001000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// ursra Dd, Dn, #imm  ···························································  (0 < imm <= 64)
	0b01111111, 0b00000000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// ursra Vd.16B, Vn.16B, #imm  ····················································  (0 < imm <= 8)
	// ursra Vd.8B, Vn.8B, #imm  ······················································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// ursra Vd.8H, Vn.8H, #imm  ·····················································  (0 < imm <= 16)
	// ursra Vd.4H, Vn.4H, #imm  ·····················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// ursra Vd.4S, Vn.4S, #imm  ·····················································  (0 < imm <= 32)
	// ursra Vd.2S, Vn.2S, #imm  ·····················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// ursra Vd.2D, Vn.2D, #imm  ·····················································  (0 < imm <= 64)
	0b00101111, 0b01000000, 0b00110100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// ushl Dd, Dn, Dm
	0b01111110, 0b11100000, 0b01000100, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// ushl Vd.16B, Vn.16B, Vm.16B
	// ushl Vd.8B, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// ushl Vd.8H, Vn.8H, Vm.8H
	// ushl Vd.4H, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// ushl Vd.4S, Vn.4S, Vm.4S
	// ushl Vd.2S, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// ushl Vd.2D, Vn.2D, Vm.2D
	0b00101110, 0b11100000, 0b01000100, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// ushll Vd.8H, Vn.8B, #imm  ······················································  (0 <= imm < 8)
	0b00101111, 0b00001000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 3,
	// ushll Vd.4S, Vn.4H, #imm  ·····················································  (0 <= imm < 16)
	0b00101111, 0b00010000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 4,
	// ushll Vd.2D, Vn.2S, #imm  ·····················································  (0 <= imm < 32)
	0b00101111, 0b00100000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,

	// ushll2 Vd.8H, Vn.16B, #imm  ····················································  (0 <= imm < 8)
	0b01101111, 0b00001000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 3,
	// ushll2 Vd.4S, Vn.8H, #imm  ····················································  (0 <= imm < 16)
	0b01101111, 0b00010000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 4,
	// ushll2 Vd.2D, Vn.4S, #imm  ····················································  (0 <= imm < 32)
	0b01101111, 0b00100000, 0b10100100, 0b00000000, 3, CmdR0, CmdR5, CmdUbits, 16, 5,

	// ushr Dd, Dn, #imm  ····························································  (0 < imm <= 64)
	0b01111111, 0b00000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// ushr Vd.16B, Vn.16B, #imm  ·····················································  (0 < imm <= 8)
	// ushr Vd.8B, Vn.8B, #imm  ·······················································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// ushr Vd.8H, Vn.8H, #imm  ······················································  (0 < imm <= 16)
	// ushr Vd.4H, Vn.4H, #imm  ······················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// ushr Vd.4S, Vn.4S, #imm  ······················································  (0 < imm <= 32)
	// ushr Vd.2S, Vn.2S, #imm  ······················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// ushr Vd.2D, Vn.2D, #imm  ······················································  (0 < imm <= 64)
	0b00101111, 0b01000000, 0b00000100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// usqadd Bd, Bn
	0b01111110, 0b00100000, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// usqadd Hd, Hn
	0b01111110, 0b01100000, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// usqadd Sd, Sn
	0b01111110, 0b10100000, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// usqadd Dd, Dn
	0b01111110, 0b11100000, 0b00111000, 0b00000000, 2, CmdR0, CmdR5,
	// usqadd Vd.16B, Vn.16B
	// usqadd Vd.8B, Vn.8B
	0b00101110, 0b00100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// usqadd Vd.8H, Vn.8H
	// usqadd Vd.4H, Vn.4H
	0b00101110, 0b01100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// usqadd Vd.4S, Vn.4S
	// usqadd Vd.2S, Vn.2S
	0b00101110, 0b10100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,
	// usqadd Vd.2D, Vn.2D
	0b00101110, 0b11100000, 0b00111000, 0b00000000, 3, CmdR0, CmdR5, CmdRwidth30,

	// usra Dd, Dn, #imm  ····························································  (0 < imm <= 64)
	0b01111111, 0b00000000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdChkUrange1, 64, CmdUsub, 16, 7, 128,
	// usra Vd.16B, Vn.16B, #imm  ·····················································  (0 < imm <= 8)
	// usra Vd.8B, Vn.8B, #imm  ·······················································  (0 < imm <= 8)
	0b00101111, 0b00001000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 3, 8, CmdRwidth30,
	// usra Vd.8H, Vn.8H, #imm  ······················································  (0 < imm <= 16)
	// usra Vd.4H, Vn.4H, #imm  ······················································  (0 < imm <= 16)
	0b00101111, 0b00010000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 4, 16, CmdRwidth30,
	// usra Vd.4S, Vn.4S, #imm  ······················································  (0 < imm <= 32)
	// usra Vd.2S, Vn.2S, #imm  ······················································  (0 < imm <= 32)
	0b00101111, 0b00100000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 5, 32, CmdRwidth30,
	// usra Vd.2D, Vn.2D, #imm  ······················································  (0 < imm <= 64)
	0b00101111, 0b01000000, 0b00010100, 0b00000000, 4, CmdR0, CmdR5, CmdUsub, 16, 6, 64, CmdRwidth30,

	// usubl Vd.8H, Vn.8B, Vm.8B
	0b00101110, 0b00100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// usubl Vd.4S, Vn.4H, Vm.4H
	0b00101110, 0b01100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// usubl Vd.2D, Vn.2S, Vm.2S
	0b00101110, 0b10100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// usubl2 Vd.8H, Vn.16B, Vm.16B
	0b01101110, 0b00100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// usubl2 Vd.4S, Vn.8H, Vm.8H
	0b01101110, 0b01100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// usubl2 Vd.2D, Vn.4S, Vm.4S
	0b01101110, 0b10100000, 0b00100000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// usubw Vd.8H, Vn.8H, Vm.8B
	0b00101110, 0b00100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// usubw Vd.4S, Vn.4S, Vm.4H
	0b00101110, 0b01100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// usubw Vd.2D, Vn.2D, Vm.2S
	0b00101110, 0b10100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// usubw2 Vd.8H, Vn.8H, Vm.16B
	0b01101110, 0b00100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// usubw2 Vd.4S, Vn.4S, Vm.8H
	0b01101110, 0b01100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,
	// usubw2 Vd.2D, Vn.2D, Vm.4S
	0b01101110, 0b10100000, 0b00110000, 0b00000000, 3, CmdR0, CmdR5, CmdR16,

	// uxtb Wd, Wn
	0b01010011, 0b00000000, 0b00011100, 0b00000000, 2, CmdR0, CmdR5,

	// uxth Wd, Wn
	0b01010011, 0b00000000, 0b00111100, 0b00000000, 2, CmdR0, CmdR5,

	// uxtl Vd.8H, Vn.8B
	0b00101111, 0b00001000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// uxtl Vd.4S, Vn.4H
	0b00101111, 0b00010000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// uxtl Vd.2D, Vn.2S
	0b00101111, 0b00100000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,

	// uxtl2 Vd.8H, Vn.16B
	0b01101111, 0b00001000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// uxtl2 Vd.4S, Vn.8H
	0b01101111, 0b00010000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,
	// uxtl2 Vd.2D, Vn.4S
	0b01101111, 0b00100000, 0b10100100, 0b00000000, 2, CmdR0, CmdR5,

	// uzp1 Vd.16B, Vn.16B, Vm.16B
	// uzp1 Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00000000, 0b00011000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uzp1 Vd.8H, Vn.8H, Vm.8H
	// uzp1 Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00011000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uzp1 Vd.4S, Vn.4S, Vm.4S
	// uzp1 Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10000000, 0b00011000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uzp1 Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11000000, 0b00011000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// uzp2 Vd.16B, Vn.16B, Vm.16B
	// uzp2 Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00000000, 0b01011000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uzp2 Vd.8H, Vn.8H, Vm.8H
	// uzp2 Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b01011000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uzp2 Vd.4S, Vn.4S, Vm.4S
	// uzp2 Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10000000, 0b01011000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// uzp2 Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11000000, 0b01011000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// wfe
	0b11010101, 0b00000011, 0b00100000, 0b01011111, 0,

	// wfi
	0b11010101, 0b00000011, 0b00100000, 0b01111111, 0,

	// xar Vd.2D, Vn.2D, Vm.2D, #imm  ················································  (0 <= imm < 64)
	0b11001110, 0b10000000, 0b00000000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdUbits, 10, 6,

	// xpacd Xd
	0b11011010, 0b11000001, 0b01000111, 0b11100000, 1, CmdR0,

	// xpaci Xd
	0b11011010, 0b11000001, 0b01000011, 0b11100000, 1, CmdR0,

	// xpaclri
	0b11010101, 0b00000011, 0b00100000, 0b11111111, 0,

	// xtn Vd.8B, Vn.8H
	0b00001110, 0b00100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// xtn Vd.4H, Vn.4S
	0b00001110, 0b01100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// xtn Vd.2S, Vn.2D
	0b00001110, 0b10100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,

	// xtn2 Vd.16B, Vn.8H
	0b01001110, 0b00100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// xtn2 Vd.8H, Vn.4S
	0b01001110, 0b01100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,
	// xtn2 Vd.4S, Vn.2D
	0b01001110, 0b10100001, 0b00101000, 0b00000000, 2, CmdR0, CmdR5,

	// yield
	0b11010101, 0b00000011, 0b00100000, 0b00111111, 0,

	// zip1 Vd.16B, Vn.16B, Vm.16B
	// zip1 Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00000000, 0b00111000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// zip1 Vd.8H, Vn.8H, Vm.8H
	// zip1 Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b00111000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// zip1 Vd.4S, Vn.4S, Vm.4S
	// zip1 Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10000000, 0b00111000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// zip1 Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11000000, 0b00111000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,

	// zip2 Vd.16B, Vn.16B, Vm.16B
	// zip2 Vd.8B, Vn.8B, Vm.8B
	0b00001110, 0b00000000, 0b01111000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// zip2 Vd.8H, Vn.8H, Vm.8H
	// zip2 Vd.4H, Vn.4H, Vm.4H
	0b00001110, 0b01000000, 0b01111000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// zip2 Vd.4S, Vn.4S, Vm.4S
	// zip2 Vd.2S, Vn.2S, Vm.2S
	0b00001110, 0b10000000, 0b01111000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
	// zip2 Vd.2D, Vn.2D, Vm.2D
	0b00001110, 0b11000000, 0b01111000, 0b00000000, 4, CmdR0, CmdR5, CmdR16, CmdRwidth30,
}