diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst index d864059de00bbfc..0e9d7a2a8392625 100644 --- a/boards/nxp/s32z2xxdc2/doc/index.rst +++ b/boards/nxp/s32z2xxdc2/doc/index.rst @@ -59,6 +59,8 @@ The boards support the following hardware features: +-----------+------------+-------------------------------------+ | LPI2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| HSE | on-chip | crypto | ++-----------+------------+-------------------------------------+ Other hardware features are not currently supported by the port. @@ -163,6 +165,19 @@ ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instan .. note:: All channels of an instance only run on 1 group channel at the same time. +CRYPTO +====== + +The Hardware Security Engine (HSE) supports cryptographic operations, including hashing and +symmetric ciphers, with capabilities for ECB, CBC, and CTR modes using RAM-based key catalogs +with 128-bit key lengths. + +.. note:: + Applications must format key catalogs before executing the first service. + + By default, MU0 is used, and other MUs are deactivated. If applications want to use other MUs, + must activate them first. + Programming and Debugging ************************* diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml index 1ec2dc27de4f34e..8514ffc88e29bdc 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml @@ -18,4 +18,5 @@ supported: - counter - adc - i2c + - crypto vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml index 329e11384c73939..85bfef637b9f129 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml @@ -18,4 +18,5 @@ supported: - counter - adc - i2c + - crypto vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml index ff384e953beac0b..abe01e9f4522f35 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml @@ -18,4 +18,5 @@ supported: - counter - adc - i2c + - crypto vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml index 1165ca8019468f1..52c6bff165da138 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml @@ -18,4 +18,5 @@ supported: - counter - adc - i2c + - crypto vendor: nxp diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.conf b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.conf new file mode 100644 index 000000000000000..fe8c96055fb688b --- /dev/null +++ b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.conf @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Only used for test +CONFIG_CRYPTO_NXP_HSE_FORMAT_KEY_CATALOG=y diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay new file mode 100644 index 000000000000000..f2558d71a6b11e7 --- /dev/null +++ b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&mu0_mua { + status = "okay"; +}; diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.conf b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.conf new file mode 100644 index 000000000000000..fe8c96055fb688b --- /dev/null +++ b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.conf @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Only used for test +CONFIG_CRYPTO_NXP_HSE_FORMAT_KEY_CATALOG=y diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay new file mode 100644 index 000000000000000..f2558d71a6b11e7 --- /dev/null +++ b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&mu0_mua { + status = "okay"; +}; diff --git a/samples/drivers/crypto/prj.conf b/samples/drivers/crypto/prj.conf index 997396aa8a433ae..06c1ffa13e6c259 100644 --- a/samples/drivers/crypto/prj.conf +++ b/samples/drivers/crypto/prj.conf @@ -3,4 +3,4 @@ CONFIG_CRYPTO_LOG_LEVEL_DBG=y CONFIG_LOG=y CONFIG_LOG_MODE_MINIMAL=y -CONFIG_MAIN_STACK_SIZE=4096 +CONFIG_MAIN_STACK_SIZE=8192 diff --git a/samples/drivers/crypto/src/main.c b/samples/drivers/crypto/src/main.c index 1d65cbd3c77065d..41d94773f2a1640 100644 --- a/samples/drivers/crypto/src/main.c +++ b/samples/drivers/crypto/src/main.c @@ -27,6 +27,8 @@ LOG_MODULE_REGISTER(main); #define CRYPTO_DEV_COMPAT st_stm32_aes #elif DT_HAS_COMPAT_STATUS_OKAY(nxp_mcux_dcp) #define CRYPTO_DEV_COMPAT nxp_mcux_dcp +#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_crypto_hse_mu) +#define CRYPTO_DEV_COMPAT nxp_crypto_hse_mu #elif CONFIG_CRYPTO_NRF_ECB #define CRYPTO_DEV_COMPAT nordic_nrf_ecb #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto) diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.conf b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.conf new file mode 100644 index 000000000000000..fe8c96055fb688b --- /dev/null +++ b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.conf @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Only used for test +CONFIG_CRYPTO_NXP_HSE_FORMAT_KEY_CATALOG=y diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay new file mode 100644 index 000000000000000..f2558d71a6b11e7 --- /dev/null +++ b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&mu0_mua { + status = "okay"; +}; diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.conf b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.conf new file mode 100644 index 000000000000000..fe8c96055fb688b --- /dev/null +++ b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.conf @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Only used for test +CONFIG_CRYPTO_NXP_HSE_FORMAT_KEY_CATALOG=y diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay new file mode 100644 index 000000000000000..f2558d71a6b11e7 --- /dev/null +++ b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay @@ -0,0 +1,9 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&mu0_mua { + status = "okay"; +}; diff --git a/tests/crypto/crypto_hash/src/main.c b/tests/crypto/crypto_hash/src/main.c index ea1229dda6df5f3..4471ee727f8dbe5 100644 --- a/tests/crypto/crypto_hash/src/main.c +++ b/tests/crypto/crypto_hash/src/main.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2022 Intel Corporation + * Copyright 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +14,8 @@ #define CRYPTO_DRV_NAME CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto) #define CRYPTO_DEV_COMPAT renesas_smartbond_crypto +#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_crypto_hse_mu) +#define CRYPTO_DEV_COMPAT nxp_crypto_hse_mu #else #error "You need to enable one crypto device" #endif