diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst
index 9cb0972bf8fc7e..786cd8342f3de3 100644
--- a/boards/nxp/s32z2xxdc2/doc/index.rst
+++ b/boards/nxp/s32z2xxdc2/doc/index.rst
@@ -170,6 +170,19 @@ EDMA
 The EDMA modules feature four EDMA3 instances: Instance 0 with 32 channels,
 and instances 1, 4, and 5, each with 16 channels.
 
+CRYPTO
+======
+
+The Hardware Security Engine (HSE) supports cryptographic operations, including hashing and
+symmetric ciphers, with capabilities for ECB, CBC, and CTR modes using RAM-based key catalogs
+with 128-bit or 256-bit key lengths.
+
+.. note::
+   The driver assumes that the HSE Firmware has been installed and configured (i.e the key catalogs
+   has been formatted, used MU instances has been activated, etc). HSE Firmware installation and
+   configuration phase documented in HSE Firmware User Manual. Please contact NXP sales person or
+   NXP distributor in order to have access to that document.
+
 Programming and Debugging
 *************************
 
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
index 070c33e6bfd323..f9899392691106 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
@@ -19,4 +19,5 @@ supported:
   - adc
   - i2c
   - dma
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
index 9d692144a76c21..4f48af57c6d52f 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
@@ -19,4 +19,5 @@ supported:
   - adc
   - i2c
   - dma
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
index 3de95effa80035..3e2fa028c484c5 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
@@ -19,4 +19,5 @@ supported:
   - adc
   - i2c
   - dma
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
index ef45138807edae..0be14d625db604 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
@@ -19,4 +19,5 @@ supported:
   - adc
   - i2c
   - dma
+  - crypto
 vendor: nxp
diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay
new file mode 100644
index 00000000000000..a28a85a5fe4396
--- /dev/null
+++ b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub0 {
+	status = "okay";
+};
diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay
new file mode 100644
index 00000000000000..757d788314269c
--- /dev/null
+++ b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub2 {
+	status = "okay";
+};
diff --git a/samples/drivers/crypto/src/main.c b/samples/drivers/crypto/src/main.c
index ef0d248c365670..400b5877f2bcb4 100644
--- a/samples/drivers/crypto/src/main.c
+++ b/samples/drivers/crypto/src/main.c
@@ -27,6 +27,8 @@ LOG_MODULE_REGISTER(main);
 #define CRYPTO_DEV_COMPAT st_stm32_aes
 #elif DT_HAS_COMPAT_STATUS_OKAY(nxp_mcux_dcp)
 #define CRYPTO_DEV_COMPAT nxp_mcux_dcp
+#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_crypto_hse_mu)
+#define CRYPTO_DEV_COMPAT nxp_s32_crypto_hse_mu
 #elif CONFIG_CRYPTO_NRF_ECB
 #define CRYPTO_DEV_COMPAT nordic_nrf_ecb
 #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)
diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay
new file mode 100644
index 00000000000000..a28a85a5fe4396
--- /dev/null
+++ b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub0 {
+	status = "okay";
+};
diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay
new file mode 100644
index 00000000000000..757d788314269c
--- /dev/null
+++ b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub2 {
+	status = "okay";
+};
diff --git a/tests/crypto/crypto_hash/src/main.c b/tests/crypto/crypto_hash/src/main.c
index ea1229dda6df5f..c32bd543c61dc2 100644
--- a/tests/crypto/crypto_hash/src/main.c
+++ b/tests/crypto/crypto_hash/src/main.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022 Intel Corporation
+ * Copyright 2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +14,8 @@
 #define CRYPTO_DRV_NAME CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME
 #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)
 #define CRYPTO_DEV_COMPAT renesas_smartbond_crypto
+#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_crypto_hse_mu)
+#define CRYPTO_DEV_COMPAT nxp_s32_crypto_hse_mu
 #else
 #error "You need to enable one crypto device"
 #endif