From d638b225db5237c5e6901d837664d9eb3baf9478 Mon Sep 17 00:00:00 2001 From: Camille BAUD Date: Fri, 17 Jan 2025 20:20:40 +0100 Subject: [PATCH] drivers: timer: Harmonize mtime-based RISC-V timers This commit replaces a bunch of ifdefs and bindings with a single extensible binding, and makes all standard mtime system timers consistent. Signed-off-by: Camille BAUD --- boards/intel/niosv_g/niosv_g.dts | 2 +- boards/intel/niosv_m/niosv_m.dts | 2 +- boards/snps/nsim/arc_v/rmx1xx.dtsi | 7 ++ drivers/timer/Kconfig.riscv_machine | 9 +-- drivers/timer/riscv_machine_timer.c | 65 ++----------------- .../sifive,clint0.yaml | 0 .../timer/andestech,machine-timer.yaml | 19 ------ dts/bindings/timer/lowrisc,machine-timer.yaml | 19 ------ dts/bindings/timer/neorv32-machine-timer.yaml | 19 ------ dts/bindings/timer/niosv-machine-timer.yaml | 19 ------ dts/bindings/timer/nuclei,systimer.yaml | 8 +-- dts/bindings/timer/riscv,mtime-timer.yaml | 14 ++++ dts/bindings/timer/starfive,jh7100-clint.yaml | 8 --- dts/bindings/timer/telink,machine-timer.yaml | 19 ------ dts/riscv/andes/andes_v5_ae350.dtsi | 4 +- dts/riscv/efinix/sapphire_soc.dtsi | 7 ++ dts/riscv/gd/gd32vf103.dtsi | 6 +- dts/riscv/lowrisc/opentitan_earlgrey.dtsi | 11 ++-- dts/riscv/microchip/microchip-miv.dtsi | 7 ++ dts/riscv/microchip/mpfs.dtsi | 11 ++++ dts/riscv/neorv32.dtsi | 6 +- dts/riscv/niosv/niosv-g.dtsi | 7 +- dts/riscv/niosv/niosv-m.dtsi | 7 +- dts/riscv/qemu/virt-riscv.dtsi | 14 ++++ dts/riscv/renode_riscv32_virt.dtsi | 7 ++ dts/riscv/sifive/riscv32-fe310.dtsi | 6 ++ dts/riscv/sifive/riscv64-fu540.dtsi | 11 ++++ dts/riscv/sifive/riscv64-fu740.dtsi | 12 +++- dts/riscv/starfive/jh7110-visionfive-v2.dtsi | 15 ++++- .../starfive/starfive_jh7100_beagle_v.dtsi | 9 ++- dts/riscv/telink/telink_b91.dtsi | 8 +-- 31 files changed, 152 insertions(+), 206 deletions(-) rename dts/bindings/{timer => interrupt-controller}/sifive,clint0.yaml (100%) delete mode 100644 dts/bindings/timer/andestech,machine-timer.yaml delete mode 100644 dts/bindings/timer/lowrisc,machine-timer.yaml delete mode 100644 dts/bindings/timer/neorv32-machine-timer.yaml delete mode 100644 dts/bindings/timer/niosv-machine-timer.yaml create mode 100644 dts/bindings/timer/riscv,mtime-timer.yaml delete mode 100644 dts/bindings/timer/starfive,jh7100-clint.yaml delete mode 100644 dts/bindings/timer/telink,machine-timer.yaml diff --git a/boards/intel/niosv_g/niosv_g.dts b/boards/intel/niosv_g/niosv_g.dts index 4ebd9c9721a925..cbaf19ec02d435 100644 --- a/boards/intel/niosv_g/niosv_g.dts +++ b/boards/intel/niosv_g/niosv_g.dts @@ -27,7 +27,7 @@ }; &mtimer { - reg = <0x90000 0x10>; + reg = <0x90000 0x8 0x90008 0x8>; }; &uart0 { diff --git a/boards/intel/niosv_m/niosv_m.dts b/boards/intel/niosv_m/niosv_m.dts index 495594f72dc352..e32edc3c7c22c0 100644 --- a/boards/intel/niosv_m/niosv_m.dts +++ b/boards/intel/niosv_m/niosv_m.dts @@ -27,7 +27,7 @@ }; &mtimer { - reg = <0x90000 0x10>; + reg = <0x90000 0x8 0x90008 0x8>; }; &uart0 { diff --git a/boards/snps/nsim/arc_v/rmx1xx.dtsi b/boards/snps/nsim/arc_v/rmx1xx.dtsi index 9480922e2176d3..43283376648908 100644 --- a/boards/snps/nsim/arc_v/rmx1xx.dtsi +++ b/boards/snps/nsim/arc_v/rmx1xx.dtsi @@ -37,6 +37,13 @@ interrupt-names = "soft0", "timer0"; }; + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&cpu0_intc 7>; + reg = <0x200bff8 0x8 0x2004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + uart0: serial@10000000{ compatible = "ns16550", "snps,dw-apb-uart"; reg = <0x10000000 0x400>; diff --git a/drivers/timer/Kconfig.riscv_machine b/drivers/timer/Kconfig.riscv_machine index efbd4d322f731c..f23477c435bd0b 100644 --- a/drivers/timer/Kconfig.riscv_machine +++ b/drivers/timer/Kconfig.riscv_machine @@ -6,13 +6,8 @@ config RISCV_MACHINE_TIMER bool "RISCV Machine Timer" default y - depends on DT_HAS_ANDESTECH_MACHINE_TIMER_ENABLED || \ - DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \ - DT_HAS_NUCLEI_SYSTIMER_ENABLED || \ - DT_HAS_SIFIVE_CLINT0_ENABLED || \ - DT_HAS_TELINK_MACHINE_TIMER_ENABLED || \ - DT_HAS_LOWRISC_MACHINE_TIMER_ENABLED || \ - DT_HAS_NIOSV_MACHINE_TIMER_ENABLED + depends on DT_HAS_RISCV_MTIME_TIMER_ENABLED || \ + DT_HAS_NUCLEI_SYSTIMER_ENABLED select TICKLESS_CAPABLE select TIMER_HAS_64BIT_CYCLE_COUNTER help diff --git a/drivers/timer/riscv_machine_timer.c b/drivers/timer/riscv_machine_timer.c index 038beddca5c988..a9590a0865eee2 100644 --- a/drivers/timer/riscv_machine_timer.c +++ b/drivers/timer/riscv_machine_timer.c @@ -1,4 +1,5 @@ /* + * Copyright (c) 2024 MASSDRIVER EI (massdriver.space) * Copyright (c) 2018-2023 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 @@ -13,65 +14,11 @@ #include #include -/* andestech,machine-timer */ -#if DT_HAS_COMPAT_STATUS_OKAY(andestech_machine_timer) -#define DT_DRV_COMPAT andestech_machine_timer - -#define MTIME_REG DT_INST_REG_ADDR(0) -#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8) -#define TIMER_IRQN DT_INST_IRQN(0) -/* neorv32-machine-timer */ -#elif DT_HAS_COMPAT_STATUS_OKAY(neorv32_machine_timer) -#define DT_DRV_COMPAT neorv32_machine_timer - -#define MTIME_REG DT_INST_REG_ADDR(0) -#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8) -#define TIMER_IRQN DT_INST_IRQN(0) -/* nuclei,systimer */ -#elif DT_HAS_COMPAT_STATUS_OKAY(nuclei_systimer) -#define DT_DRV_COMPAT nuclei_systimer - -#define MTIME_REG DT_INST_REG_ADDR(0) -#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8) -#define TIMER_IRQN DT_INST_IRQ_BY_IDX(0, 1, irq) -/* sifive,clint0 */ -#elif DT_HAS_COMPAT_STATUS_OKAY(sifive_clint0) -#define DT_DRV_COMPAT sifive_clint0 - -#define MTIME_REG (DT_INST_REG_ADDR(0) + 0xbff8U) -#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x4000U) -#define TIMER_IRQN DT_INST_IRQ_BY_IDX(0, 1, irq) -/* telink,machine-timer */ -#elif DT_HAS_COMPAT_STATUS_OKAY(telink_machine_timer) -#define DT_DRV_COMPAT telink_machine_timer - -#define MTIME_REG DT_INST_REG_ADDR(0) -#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8) -#define TIMER_IRQN DT_INST_IRQN(0) -/* lowrisc,machine-timer */ -#elif DT_HAS_COMPAT_STATUS_OKAY(lowrisc_machine_timer) -#define DT_DRV_COMPAT lowrisc_machine_timer - -#define MTIME_REG (DT_INST_REG_ADDR(0) + 0x110) -#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x118) -#define TIMER_IRQN DT_INST_IRQN(0) -/* niosv-machine-timer */ -#elif DT_HAS_COMPAT_STATUS_OKAY(niosv_machine_timer) -#define DT_DRV_COMPAT niosv_machine_timer - -#define MTIMECMP_REG DT_INST_REG_ADDR(0) -#define MTIME_REG (DT_INST_REG_ADDR(0) + 8) -#define TIMER_IRQN DT_INST_IRQN(0) -/* scr,machine-timer*/ -#elif DT_HAS_COMPAT_STATUS_OKAY(scr_machine_timer) -#define DT_DRV_COMPAT scr_machine_timer -#define MTIMER_HAS_DIVIDER - -#define MTIMEDIV_REG (DT_INST_REG_ADDR_U64(0) + 4) -#define MTIME_REG (DT_INST_REG_ADDR_U64(0) + 8) -#define MTIMECMP_REG (DT_INST_REG_ADDR_U64(0) + 16) -#define TIMER_IRQN DT_INST_IRQN(0) -#endif +#define DT_DRV_COMPAT riscv_mtime_timer + +#define MTIME_REG DT_INST_REG_ADDR_BY_IDX(0, 0) +#define MTIMECMP_REG DT_INST_REG_ADDR_BY_IDX(0, 1) +#define TIMER_IRQN DT_INST_IRQN(0) #define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() \ / CONFIG_SYS_CLOCK_TICKS_PER_SEC) diff --git a/dts/bindings/timer/sifive,clint0.yaml b/dts/bindings/interrupt-controller/sifive,clint0.yaml similarity index 100% rename from dts/bindings/timer/sifive,clint0.yaml rename to dts/bindings/interrupt-controller/sifive,clint0.yaml diff --git a/dts/bindings/timer/andestech,machine-timer.yaml b/dts/bindings/timer/andestech,machine-timer.yaml deleted file mode 100644 index 9a1c4e891d32da..00000000000000 --- a/dts/bindings/timer/andestech,machine-timer.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - Andes Machine Timer - - The Andes machine timer provides RISC-V privileged mtime and mtimecmp - registers. - -compatible: "andestech,machine-timer" - -include: base.yaml - -properties: - reg: - required: true - - interrupts-extended: - required: true diff --git a/dts/bindings/timer/lowrisc,machine-timer.yaml b/dts/bindings/timer/lowrisc,machine-timer.yaml deleted file mode 100644 index 01721e22ed48c8..00000000000000 --- a/dts/bindings/timer/lowrisc,machine-timer.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2023 Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -description: | - OpenTitan Machine Timer - - The OpenTitan machine timer provides RISC-V privileged mtime and mtimecmp - registers. - -compatible: "lowrisc,machine-timer" - -include: base.yaml - -properties: - reg: - required: true - - interrupts: - required: true diff --git a/dts/bindings/timer/neorv32-machine-timer.yaml b/dts/bindings/timer/neorv32-machine-timer.yaml deleted file mode 100644 index 4c72679f6a589d..00000000000000 --- a/dts/bindings/timer/neorv32-machine-timer.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - NEORV32 Machine Timer - - The NEORV32 machine timer provides RISC-V privileged mtime and mtimecmp - registers. - -compatible: "neorv32-machine-timer" - -include: base.yaml - -properties: - reg: - required: true - - interrupts: - required: true diff --git a/dts/bindings/timer/niosv-machine-timer.yaml b/dts/bindings/timer/niosv-machine-timer.yaml deleted file mode 100644 index 4b77d131e6ee16..00000000000000 --- a/dts/bindings/timer/niosv-machine-timer.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -description: | - NIOSV Machine Timer - - The NIOSV machine timer provides RISC-V privileged mtime and mtimecmp - registers. - -compatible: "niosv-machine-timer" - -include: base.yaml - -properties: - reg: - required: true - - interrupts: - required: true diff --git a/dts/bindings/timer/nuclei,systimer.yaml b/dts/bindings/timer/nuclei,systimer.yaml index 5c8f319a7c51d2..b7f6513c9d63fd 100644 --- a/dts/bindings/timer/nuclei,systimer.yaml +++ b/dts/bindings/timer/nuclei,systimer.yaml @@ -9,15 +9,9 @@ description: | compatible: "nuclei,systimer" -include: base.yaml +include: "riscv,mtime-timer.yaml" properties: - reg: - required: true - - interrupts: - required: true - clk-divider: type: int description: | diff --git a/dts/bindings/timer/riscv,mtime-timer.yaml b/dts/bindings/timer/riscv,mtime-timer.yaml new file mode 100644 index 00000000000000..755bf81cb44270 --- /dev/null +++ b/dts/bindings/timer/riscv,mtime-timer.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +description: RISC-V Standard mtime Timer. + +compatible: "riscv,mtime-timer" + +include: base.yaml + +properties: + reg: + required: true + interrupts-extended: + required: true diff --git a/dts/bindings/timer/starfive,jh7100-clint.yaml b/dts/bindings/timer/starfive,jh7100-clint.yaml deleted file mode 100644 index 0120e899308803..00000000000000 --- a/dts/bindings/timer/starfive,jh7100-clint.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: Starfive JH7100 RISC-V Core-Local Interruptor. - -compatible: "starfive,jh7100-clint" - -include: sifive,clint0.yaml diff --git a/dts/bindings/timer/telink,machine-timer.yaml b/dts/bindings/timer/telink,machine-timer.yaml deleted file mode 100644 index 0ee37bd6de711a..00000000000000 --- a/dts/bindings/timer/telink,machine-timer.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -description: | - Telink Machine Timer - - The Telink machine timer provides RISC-V privileged mtime and mtimecmp - registers. - -compatible: "telink,machine-timer" - -include: base.yaml - -properties: - reg: - required: true - - interrupts: - required: true diff --git a/dts/riscv/andes/andes_v5_ae350.dtsi b/dts/riscv/andes/andes_v5_ae350.dtsi index 538de399af94ba..5ad898f59529b7 100644 --- a/dts/riscv/andes/andes_v5_ae350.dtsi +++ b/dts/riscv/andes/andes_v5_ae350.dtsi @@ -215,8 +215,8 @@ }; mtimer: timer@e6000000 { - compatible = "andestech,machine-timer"; - reg = <0xe6000000 0x10>; + compatible = "riscv,mtime-timer"; + reg = <0xe6000000 0x8 0xe6000008 0x8>; interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7 &cpu2_intc 7 &cpu3_intc 7 &cpu4_intc 7 &cpu5_intc 7 diff --git a/dts/riscv/efinix/sapphire_soc.dtsi b/dts/riscv/efinix/sapphire_soc.dtsi index 72092a4bc93008..5ad71f136114d0 100644 --- a/dts/riscv/efinix/sapphire_soc.dtsi +++ b/dts/riscv/efinix/sapphire_soc.dtsi @@ -65,6 +65,13 @@ reg = <0xf8b00000 0x10000>; }; + mtimer: timer@f8b0bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&hlic 7>; + reg = <0xf8b0bff8 0x8 0xf8b04000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + timer0: timer@e0002800 { compatible = "efinix,sapphire-timer0"; reg = <0xe0002800 0x40>; diff --git a/dts/riscv/gd/gd32vf103.dtsi b/dts/riscv/gd/gd32vf103.dtsi index a631cd4ab18ff9..57db103f028e38 100644 --- a/dts/riscv/gd/gd32vf103.dtsi +++ b/dts/riscv/gd/gd32vf103.dtsi @@ -41,9 +41,9 @@ ranges; systimer: timer@d1000000 { - compatible = "nuclei,systimer"; - reg = <0xd1000000 0x10000>; - interrupts = <3 0>, <7 0>; + compatible = "nuclei,systimer", "riscv,mtime-timer"; + reg = <0xd1000000 0x8 0xd1000008 0x8>; + interrupts-extended = <&eclic 7 0>; clk-divider = ; }; diff --git a/dts/riscv/lowrisc/opentitan_earlgrey.dtsi b/dts/riscv/lowrisc/opentitan_earlgrey.dtsi index e3b79bbaf06741..6aaa86b4236433 100644 --- a/dts/riscv/lowrisc/opentitan_earlgrey.dtsi +++ b/dts/riscv/lowrisc/opentitan_earlgrey.dtsi @@ -44,12 +44,11 @@ reg = <0x10000000 0x10000>; }; - mtimer: timer@40100000 { - compatible = "lowrisc,machine-timer"; - reg = <0x40100000 0x200>; - interrupts = <7 0>; - interrupt-parent = <&hlic>; - status = "disabled"; + mtimer: timer@40100110 { + compatible = "riscv,mtime-timer"; + reg = <0x40100110 0x8 0x40100118 0x8>; + reg-names = "mtime", "mtimecmp"; + interrupts-extended = <&hlic 7>; }; aontimer: aontimer@40470000 { diff --git a/dts/riscv/microchip/microchip-miv.dtsi b/dts/riscv/microchip/microchip-miv.dtsi index 305145b7e44f81..b46d5c826698eb 100644 --- a/dts/riscv/microchip/microchip-miv.dtsi +++ b/dts/riscv/microchip/microchip-miv.dtsi @@ -48,6 +48,13 @@ reg = <0x44000000 0x10000>; }; + mtimer: timer@4400bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&hlic 7>; + reg = <0x4400bff8 0x8 0x44004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + plic: interrupt-controller@40000000 { compatible = "sifive,plic-1.0.0"; #address-cells = <0>; diff --git a/dts/riscv/microchip/mpfs.dtsi b/dts/riscv/microchip/mpfs.dtsi index f22c7604bb3a51..d3d0e0200d2b40 100644 --- a/dts/riscv/microchip/mpfs.dtsi +++ b/dts/riscv/microchip/mpfs.dtsi @@ -114,6 +114,17 @@ reg = <0x2000000 0x10000>; }; + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&hlic0 7 + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7>; + reg = <0x200bff8 0x8 0x2004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + plic: interrupt-controller@c000000 { compatible = "sifive,plic-1.0.0"; #interrupt-cells = <2>; diff --git a/dts/riscv/neorv32.dtsi b/dts/riscv/neorv32.dtsi index 31fb06b1c49a5f..502d2314b31e86 100644 --- a/dts/riscv/neorv32.dtsi +++ b/dts/riscv/neorv32.dtsi @@ -65,9 +65,9 @@ ranges; mtimer: timer@ffffff90 { - compatible = "neorv32-machine-timer"; - reg = <0xffffff90 0x10>; - interrupts = <7>; + compatible = "riscv,mtime-timer"; + reg = <0xffffff90 0x8 0xffffff98 0x8>; + interrupts-extended = <&intc 7>; }; uart0: serial@ffffffa0 { diff --git a/dts/riscv/niosv/niosv-g.dtsi b/dts/riscv/niosv/niosv-g.dtsi index 2022e984ff5526..9bda7b00ef7801 100644 --- a/dts/riscv/niosv/niosv-g.dtsi +++ b/dts/riscv/niosv/niosv-g.dtsi @@ -44,9 +44,10 @@ }; mtimer: machine-timer@90000 { - compatible = "niosv-machine-timer"; - reg = <0x90000 0x10>; - interrupts = <7>; + compatible = "riscv,mtime-timer"; + reg = <0x90000 0x8 0x90008 0x8>; + reg-names = "mtime", "mtimecmp"; + interrupts-extended = <&intc 7>; }; uart0: serial@90078 { diff --git a/dts/riscv/niosv/niosv-m.dtsi b/dts/riscv/niosv/niosv-m.dtsi index e6594a2354659d..5a4c411bedf2b1 100644 --- a/dts/riscv/niosv/niosv-m.dtsi +++ b/dts/riscv/niosv/niosv-m.dtsi @@ -44,9 +44,10 @@ }; mtimer: machine-timer@90000 { - compatible = "niosv-machine-timer"; - reg = <0x90000 0x10>; - interrupts = <7>; + compatible = "riscv,mtime-timer"; + reg = <0x90000 0x8 0x90008 0x8>; + reg-names = "mtime", "mtimecmp"; + interrupts-extended = <&intc 7>; }; uart0: serial@90078 { diff --git a/dts/riscv/qemu/virt-riscv.dtsi b/dts/riscv/qemu/virt-riscv.dtsi index b810f9fe7dcba2..1b2926768308f7 100644 --- a/dts/riscv/qemu/virt-riscv.dtsi +++ b/dts/riscv/qemu/virt-riscv.dtsi @@ -193,5 +193,19 @@ &hlic6 0x03 &hlic6 0x07 &hlic7 0x03 &hlic7 0x07>; }; + + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&hlic0 7 + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7 + &hlic5 7 + &hlic6 7 + &hlic7 7>; + reg = <0x200bff8 0x8 0x2004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; }; }; diff --git a/dts/riscv/renode_riscv32_virt.dtsi b/dts/riscv/renode_riscv32_virt.dtsi index a0db375501f7c3..2a0c981b45ceff 100644 --- a/dts/riscv/renode_riscv32_virt.dtsi +++ b/dts/riscv/renode_riscv32_virt.dtsi @@ -50,6 +50,13 @@ reg = <0x2000000 0x10000>; }; + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&hlic 7>; + reg = <0x200bff8 0x8 0x2004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + plic0: interrupt-controller@c000000 { compatible = "sifive,plic-1.0.0"; #address-cells = <0>; diff --git a/dts/riscv/sifive/riscv32-fe310.dtsi b/dts/riscv/sifive/riscv32-fe310.dtsi index f2128e1d37bfb9..44a32eb823ddb4 100644 --- a/dts/riscv/sifive/riscv32-fe310.dtsi +++ b/dts/riscv/sifive/riscv32-fe310.dtsi @@ -65,6 +65,12 @@ interrupts-extended = <&hlic 3 &hlic 7>; reg = <0x2000000 0x10000>; }; + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&hlic 7>; + reg = <0x200bff8 0x8 0x2004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; debug: debug-controller@0 { compatible = "sifive,debug-013", "riscv,debug-013"; interrupts-extended = <&hlic 65535>; diff --git a/dts/riscv/sifive/riscv64-fu540.dtsi b/dts/riscv/sifive/riscv64-fu540.dtsi index 065870fac61bfe..d90dbf7a51cf6d 100644 --- a/dts/riscv/sifive/riscv64-fu540.dtsi +++ b/dts/riscv/sifive/riscv64-fu540.dtsi @@ -182,6 +182,17 @@ reg = <0x2000000 0x10000>; }; + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&hlic0 7 + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7>; + reg = <0x200bff8 0x8 0x2004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + l2lim: l2lim@8000000 { compatible = "sifive,l2lim0"; reg = <0x8000000 0x2000000>; diff --git a/dts/riscv/sifive/riscv64-fu740.dtsi b/dts/riscv/sifive/riscv64-fu740.dtsi index 4b82d6338bc55b..0b1fc21f5bcdad 100644 --- a/dts/riscv/sifive/riscv64-fu740.dtsi +++ b/dts/riscv/sifive/riscv64-fu740.dtsi @@ -137,13 +137,23 @@ reg = <0x0 0x2000000 0x0 0x10000>; }; + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&hlic0 7 + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7>; + reg = <0x200bff8 0x8 0x2004000 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + l2lim: l2lim@8000000 { compatible = "sifive,l2lim0"; reg = <0x0 0x8000000 0x0 0x200000>; reg-names = "mem"; }; - plic: interrupt-controller@c000000 { compatible = "sifive,plic-1.0.0"; #address-cells = <0>; diff --git a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi index c3382bca86f2b0..c9db700459e57d 100644 --- a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi +++ b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi @@ -145,8 +145,8 @@ compatible = "starfive,jh7110", "simple-bus"; ranges; - clint: timer@2000000 { - compatible = "starfive,jh7110-clint", "sifive,clint0"; + clint: clint@2000000 { + compatible = "sifive,clint0"; interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 @@ -155,6 +155,17 @@ reg = <0x0 0x2000000 0x0 0x10000>; }; + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&cpu0_intc 7 + &cpu1_intc 7 + &cpu2_intc 7 + &cpu3_intc 7 + &cpu4_intc 7>; + reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + ccache: cache-controller@2010000 { cache-block-size = <64>; cache-level = <2>; diff --git a/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi b/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi index c36ea625b02fee..e5761dd2954dfc 100644 --- a/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi +++ b/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi @@ -115,12 +115,19 @@ }; clint: clint@2000000 { - compatible = "starfive,jh7100-clint", "sifive,clint0"; + compatible = "sifive,clint0"; interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7>; reg = <0x0 0x2000000 0x0 0x10000>; }; + mtimer: timer@200bff8 { + compatible = "riscv,mtime-timer"; + interrupts-extended = <&cpu0intctrl 7 &cpu1intctrl 7>; + reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>; + reg-names = "mtime", "mtimecmp"; + }; + plic: plic@c000000 { compatible = "sifive,plic-1.0.0"; #address-cells = <0>; diff --git a/dts/riscv/telink/telink_b91.dtsi b/dts/riscv/telink/telink_b91.dtsi index a75929f2814ad2..5b3810af3d98b4 100644 --- a/dts/riscv/telink/telink_b91.dtsi +++ b/dts/riscv/telink/telink_b91.dtsi @@ -48,10 +48,10 @@ }; mtimer: timer@e6000000 { - compatible = "telink,machine-timer"; - reg = <0xe6000000 0x10000>; - interrupts = <7 0>; - interrupt-parent = <&plic0>; + compatible = "riscv,mtime-timer"; + reg = <0xe6000000 0x8 0xe6000008 0x8>; + reg-names = "mtime", "mtimecmp"; + interrupts-extended = <&plic0 7 0>; }; flash_mspi: flash-controller@80140100 {