From db3ae8d74839024473eb63b683743115ba1cf589 Mon Sep 17 00:00:00 2001 From: Mert Ekren Date: Fri, 3 Jan 2025 11:23:10 +0300 Subject: [PATCH 1/7] manifest: hal_adi: Pull sdhc header Pull in support that adds sdhc header from hal_adi Signed-off-by: Mert Ekren --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 515566aefa55f3..bc37b01e537015 100644 --- a/west.yml +++ b/west.yml @@ -142,7 +142,7 @@ manifest: groups: - fs - name: hal_adi - revision: b1a10239e1001502c3089e0cf938e938f99b1f30 + revision: pull/12/head path: modules/hal/adi groups: - hal From 7603b7435c69471f2652da7198e8f3382de91b42 Mon Sep 17 00:00:00 2001 From: Mert Ekren Date: Thu, 12 Sep 2024 08:17:33 +0300 Subject: [PATCH 2/7] drivers: sdhc: Add MAX32666 SDHC driver This commit adds MAX32666 SDHC driver. Co-Authored-By: Anil Kara Co-Authored-By: Tahsin Mutlugun Signed-off-by: Mert Ekren --- drivers/sdhc/CMakeLists.txt | 1 + drivers/sdhc/Kconfig | 1 + drivers/sdhc/Kconfig.max32 | 10 + drivers/sdhc/sdhc_max32.c | 416 ++++++++++++++++++++++++++++++++++++ 4 files changed, 428 insertions(+) create mode 100644 drivers/sdhc/Kconfig.max32 create mode 100644 drivers/sdhc/sdhc_max32.c diff --git a/drivers/sdhc/CMakeLists.txt b/drivers/sdhc/CMakeLists.txt index 269f1a419c08a7..d2f0cf1e11309e 100644 --- a/drivers/sdhc/CMakeLists.txt +++ b/drivers/sdhc/CMakeLists.txt @@ -13,4 +13,5 @@ zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1 ifx_cat1_sdio.c) zephyr_library_sources_ifdef(CONFIG_CDNS_SDHC sdhc_cdns_ll.c sdhc_cdns.c) zephyr_library_sources_ifdef(CONFIG_SDHC_ESP32 sdhc_esp32.c) zephyr_library_sources_ifdef(CONFIG_SDHC_RENESAS_RA sdhc_renesas_ra.c) +zephyr_library_sources_ifdef(CONFIG_SDHC_MAX32 sdhc_max32.c) endif() diff --git a/drivers/sdhc/Kconfig b/drivers/sdhc/Kconfig index 89fa669a5e5226..3c21a6acac9963 100644 --- a/drivers/sdhc/Kconfig +++ b/drivers/sdhc/Kconfig @@ -18,6 +18,7 @@ source "drivers/sdhc/Kconfig.intel" source "drivers/sdhc/Kconfig.sdhc_cdns" source "drivers/sdhc/Kconfig.esp32" source "drivers/sdhc/Kconfig.renesas_ra" +source "drivers/sdhc/Kconfig.max32" config SDHC_INIT_PRIORITY int "SDHC driver init priority" diff --git a/drivers/sdhc/Kconfig.max32 b/drivers/sdhc/Kconfig.max32 new file mode 100644 index 00000000000000..71212042ae137f --- /dev/null +++ b/drivers/sdhc/Kconfig.max32 @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SDHC_MAX32 + bool "Analog Devices MAX32 SDHC driver" + default y + depends on DT_HAS_ADI_MAX32_SDHC_ENABLED + select SDHC_SUPPORTS_NATIVE_MODE + help + sdhc driver for max32 family. diff --git a/drivers/sdhc/sdhc_max32.c b/drivers/sdhc/sdhc_max32.c new file mode 100644 index 00000000000000..407813b7a2ef67 --- /dev/null +++ b/drivers/sdhc/sdhc_max32.c @@ -0,0 +1,416 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT adi_max32_sdhc + +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(sdhc_max32, CONFIG_SDHC_LOG_LEVEL); + +static int cmd_opcode_converter(int opcode, unsigned int *cmd); +static int convert_freq_to_divider(int freq); + +/* **** Definitions **** + * todo: added from sdhc_resp_regs.h cmd51 is mandatory and is missing in msdk. + * SDHC commands and associated cmd register bits which inform hardware to wait for response, etc. + */ +#define MXC_SDHC_LIB_CMD0 0x0000 +#define MXC_SDHC_LIB_CMD1 0x0102 +#define MXC_SDHC_LIB_CMD2 0x0209 +#define MXC_SDHC_LIB_CMD3 0x031A +#define MXC_SDHC_LIB_CMD4 0x0400 +#define MXC_SDHC_LIB_CMD5 0x051A +#define MXC_SDHC_LIB_CMD6 0x060A +#define MXC_SDHC_LIB_CMD7 0x071B +#define MXC_SDHC_LIB_CMD8 0x081A +#define MXC_SDHC_LIB_CMD9 0x0901 +#define MXC_SDHC_LIB_CMD10 0x0A01 +#define MXC_SDHC_LIB_CMD11 0x0B1A +#define MXC_SDHC_LIB_CMD12 0x0C1B +#define MXC_SDHC_LIB_CMD13 0x0D1A +#define MXC_SDHC_LIB_CMD16 0x101A +#define MXC_SDHC_LIB_CMD17 0x113A +#define MXC_SDHC_LIB_CMD18 0x123A +#define MXC_SDHC_LIB_CMD23 0x171A +#define MXC_SDHC_LIB_CMD24 0x183E +#define MXC_SDHC_LIB_CMD25 0x193E +#define MXC_SDHC_LIB_CMD55 0x371A + +/* Application commands (SD Card) which are prefixed by CMD55 */ +#define MXC_SDHC_LIB_ACMD6 0x061B +#define MXC_SDHC_LIB_ACMD41 0x2902 +#define MXC_SDHC_LIB_ACMD51 0x331B + +/* todo: GCR dependent division might be 4 as well. if set to = 1 sdhcfrq. add support in msdk */ +#define SDHC_CLOCK (ADI_MAX32_CLK_IPO_FREQ / 2) + +#define SDHC_SDHC_MAX_DIV_VAL 0x3FF +#define SDHC_SDHC_PCLK_DIV 2 + +/* todo: cmd.arg = SD_IF_COND_VHS_3V3 | check_pattern; + * todo: zephyr always configures response types. msdk needs to support this as well. + * todo: add host io support + */ + +struct sdhc_max32_data { + struct sdhc_host_props props; +}; + +/* SDHC configuration. */ +struct sdhc_max32_config { + void (*irq_func)(void); + const struct pinctrl_dev_config *pcfg; + unsigned int power_delay_ms; + unsigned int bus_volt; + const struct device *clock; + struct max32_perclk perclk; +}; + +static void sdhc_max32_init_props(const struct device *dev) +{ + struct sdhc_max32_data *sdhc_data = dev->data; + const struct sdhc_max32_config *sdhc_config = dev->config; + + memset(sdhc_data, 0, sizeof(struct sdhc_max32_data)); + + sdhc_data->props.f_min = SDHC_CLOCK / (SDHC_SDHC_PCLK_DIV * SDHC_SDHC_MAX_DIV_VAL); + sdhc_data->props.f_max = SDHC_CLOCK; + sdhc_data->props.is_spi = 0; + sdhc_data->props.max_current_180 = 0; + sdhc_data->props.max_current_300 = 0; + sdhc_data->props.max_current_330 = 0; + sdhc_data->props.host_caps.timeout_clk_freq = 0x01; + sdhc_data->props.host_caps.timeout_clk_unit = 1; + sdhc_data->props.host_caps.sd_base_clk = 0x00; + sdhc_data->props.host_caps.max_blk_len = 0b10; + sdhc_data->props.host_caps.bus_8_bit_support = false; + sdhc_data->props.host_caps.bus_4_bit_support = false; + sdhc_data->props.host_caps.adma_2_support = true; + sdhc_data->props.host_caps.high_spd_support = true; + sdhc_data->props.host_caps.sdma_support = true; + sdhc_data->props.host_caps.suspend_res_support = true; + sdhc_data->props.host_caps.vol_330_support = true; + sdhc_data->props.host_caps.vol_300_support = true; + sdhc_data->props.host_caps.vol_180_support = true; + sdhc_data->props.host_caps.address_64_bit_support_v4 = false; + sdhc_data->props.host_caps.address_64_bit_support_v3 = false; + sdhc_data->props.host_caps.sdio_async_interrupt_support = true; + sdhc_data->props.host_caps.slot_type = 00; + sdhc_data->props.host_caps.sdr50_support = true; + sdhc_data->props.host_caps.sdr104_support = true; + sdhc_data->props.host_caps.ddr50_support = true; + sdhc_data->props.host_caps.uhs_2_support = false; + sdhc_data->props.host_caps.drv_type_a_support = true; + sdhc_data->props.host_caps.drv_type_c_support = true; + sdhc_data->props.host_caps.drv_type_d_support = true; + sdhc_data->props.host_caps.retune_timer_count = 0; + sdhc_data->props.host_caps.sdr50_needs_tuning = 0; + sdhc_data->props.host_caps.retuning_mode = 0; + sdhc_data->props.host_caps.clk_multiplier = 0; + sdhc_data->props.host_caps.adma3_support = false; + sdhc_data->props.host_caps.vdd2_180_support = false; + sdhc_data->props.host_caps.hs200_support = false; + sdhc_data->props.host_caps.hs400_support = false; + sdhc_data->props.power_delay = sdhc_config->power_delay_ms; +} + +static int sdhc_max32_init(const struct device *dev) +{ + const struct sdhc_max32_config *sdhc_config = dev->config; + int ret = 0; + mxc_sdhc_cfg_t cfg; + + ret = pinctrl_apply_state(sdhc_config->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + LOG_ERR("Pinctrl apply error:%d", ret); + return ret; + } + + ret = clock_control_on(sdhc_config->clock, (clock_control_subsys_t)&sdhc_config->perclk); + if (ret) { + LOG_ERR("Clock control on error:%d", ret); + return ret; + } + + cfg.bus_voltage = sdhc_config->bus_volt; + cfg.block_gap = 0; + /* Maximum divide ratio, frequency must be 100 - 400 kHz during Card Identification"*/ + cfg.clk_div = SDHC_SDHC_MAX_DIV_VAL; + + ret = MXC_SDHC_Init(&cfg); + if (ret != E_NO_ERROR) { + LOG_ERR("MXC_SDHC_Init error:%d", ret); + return ret; + } + + /* init delay, without it applications fail. 5ms found empirically */ + k_sleep(K_MSEC(5)); + + sdhc_max32_init_props(dev); + + return 0; +} + +static int sdhc_max32_card_busy(const struct device *dev) +{ + int ret = 0; + + ret = MXC_SDHC_Card_Busy(); + + return ret; +} + +static int sdhc_max32_reset(const struct device *dev) +{ + MXC_SDHC_Reset(); + + return 0; +} + +static int sdhc_max32_request(const struct device *dev, struct sdhc_command *cmd, + struct sdhc_data *data) +{ + int ret = 0; + unsigned int mxc_cmd = 0; + mxc_sdhc_cmd_cfg_t sd_cmd_cfg; + bool card_size_workaround = false; + + if (data) { + sd_cmd_cfg.sdma = (unsigned int)data->data; + sd_cmd_cfg.block_size = data->block_size; + sd_cmd_cfg.block_count = data->blocks; + } + + sd_cmd_cfg.arg_1 = cmd->arg; + sd_cmd_cfg.dma = true; /* todo: add config depending on config_dma etc. */ + + switch (cmd->opcode) { + case SD_READ_SINGLE_BLOCK: + case SD_READ_MULTIPLE_BLOCK: + sd_cmd_cfg.direction = MXC_SDHC_DIRECTION_READ; + sd_cmd_cfg.arg_1 = data->block_addr; + break; + case SD_WRITE_SINGLE_BLOCK: + case SD_WRITE_MULTIPLE_BLOCK: + sd_cmd_cfg.direction = MXC_SDHC_DIRECTION_WRITE; + sd_cmd_cfg.arg_1 = data->block_addr; + break; + case SD_SEND_CSD: + card_size_workaround = true; + default: + sd_cmd_cfg.direction = MXC_SDHC_DIRECTION_CFG; + break; + } + + ret = cmd_opcode_converter(cmd->opcode, &mxc_cmd); + if (ret) { + return ret; + } + sd_cmd_cfg.command = mxc_cmd; + sd_cmd_cfg.host_control_1 = MXC_SDHC_Get_Host_Cn_1(); + sd_cmd_cfg.callback = NULL; + + /* + * todo: this was also needed, otherwise applications failed randomly. it would be good to + * remove this with a better solution in future. + */ + k_sleep(K_MSEC(1)); + ret = MXC_SDHC_SendCommand(&sd_cmd_cfg); + if (ret) { + LOG_ERR("MXC_SDHC_SendCommand error:%d, SD opcode: %d", ret, cmd->opcode); + return ret; + } + + MXC_SDHC_Get_Response128((char *)(cmd->response)); + + if (card_size_workaround) { + /* + * this workaround is required for only CMD9. This fixes size problem. Otherwise + * it doesn't give the correct device size information. + */ + cmd->response[1] <<= 8; + cmd->response[3] <<= 8; + } + + return 0; +} + +static int sdhc_max32_get_card_present(const struct device *dev) +{ + return MXC_SDHC_Card_Inserted(); +} + +static int sdhc_max32_get_host_props(const struct device *dev, struct sdhc_host_props *props) +{ + struct sdhc_max32_data *sdhc_data = dev->data; + + memcpy(props, &sdhc_data->props, sizeof(struct sdhc_host_props)); + + return 0; +} + +static int sdhc_max32_execute_tuning(const struct device *dev) +{ + return -ENOTSUP; +} + +static int sdhc_max32_set_io(const struct device *dev, struct sdhc_io *ios) +{ + struct sdhc_max32_data *data = dev->data; + struct sdhc_host_props *props = &data->props; + enum sdhc_clock_speed speed = ios->clock; + unsigned int clk_div = 0; + + MXC_SDHC_PowerDown(); + + if (speed) { + if (speed < props->f_min || speed > props->f_max) { + LOG_ERR("Speed range error %d", speed); + return -ENOTSUP; + } + clk_div = convert_freq_to_divider(speed); + MXC_SDHC_Set_Clock_Config(clk_div); + } + + if (ios->power_mode != SDHC_POWER_OFF) { + MXC_SDHC_PowerUp(); + } + + return 0; +} + +static const struct sdhc_driver_api sdhc_max32_driver_api = { + .reset = sdhc_max32_reset, + .request = sdhc_max32_request, + .set_io = sdhc_max32_set_io, + .get_card_present = sdhc_max32_get_card_present, + .execute_tuning = sdhc_max32_execute_tuning, + .card_busy = sdhc_max32_card_busy, + .get_host_props = sdhc_max32_get_host_props, + .enable_interrupt = NULL, + .disable_interrupt = NULL, +}; + +static int cmd_opcode_converter(int opcode, unsigned int *cmd) +{ + switch (opcode) { + case SD_GO_IDLE_STATE: + *cmd = MXC_SDHC_LIB_CMD0; + break; + case MMC_SEND_OP_COND: + *cmd = MXC_SDHC_LIB_CMD1; + break; + case SD_ALL_SEND_CID: + *cmd = MXC_SDHC_LIB_CMD2; + break; + case SD_SEND_RELATIVE_ADDR: + *cmd = MXC_SDHC_LIB_CMD3; + break; + case SDIO_SEND_OP_COND: + *cmd = MXC_SDHC_LIB_CMD5; + break; + case SD_SWITCH: + *cmd = MXC_SDHC_LIB_CMD6; + break; + case SD_SELECT_CARD: + *cmd = MXC_SDHC_LIB_CMD7; + break; + case SD_SEND_IF_COND: + *cmd = MXC_SDHC_LIB_CMD8; + break; + case SD_SEND_CSD: + *cmd = MXC_SDHC_LIB_CMD9; + break; + case SD_SEND_CID: + *cmd = MXC_SDHC_LIB_CMD10; + break; + case SD_VOL_SWITCH: + *cmd = MXC_SDHC_LIB_CMD11; + break; + case SD_STOP_TRANSMISSION: + *cmd = MXC_SDHC_LIB_CMD12; + break; + case SD_SEND_STATUS: + *cmd = MXC_SDHC_LIB_CMD13; + break; + case SD_SET_BLOCK_SIZE: + *cmd = MXC_SDHC_LIB_CMD16; + break; + case SD_READ_SINGLE_BLOCK: + *cmd = MXC_SDHC_LIB_CMD17; + break; + case SD_READ_MULTIPLE_BLOCK: + *cmd = MXC_SDHC_LIB_CMD18; + break; + case SD_SET_BLOCK_COUNT: + *cmd = MXC_SDHC_LIB_CMD23; + break; + case SD_WRITE_SINGLE_BLOCK: + *cmd = MXC_SDHC_LIB_CMD24; + break; + case SD_WRITE_MULTIPLE_BLOCK: + *cmd = MXC_SDHC_LIB_CMD25; + break; + case SD_APP_CMD: + *cmd = MXC_SDHC_LIB_CMD55; + break; + case SD_APP_SEND_OP_COND: + *cmd = MXC_SDHC_LIB_ACMD41; + break; + case SD_APP_SEND_SCR: + *cmd = MXC_SDHC_LIB_ACMD51; + break; + /* todo: below are not defined in msdk, support might be added later */ + case SD_ERASE_BLOCK_START: + case SD_ERASE_BLOCK_END: + case SD_ERASE_BLOCK_OPERATION: + case SDIO_RW_DIRECT: + case SD_SEND_TUNING_BLOCK: + case SD_GO_INACTIVE_STATE: + case SDIO_RW_EXTENDED: + default: + LOG_ERR("Opcode convert error %d", opcode); + return -EINVAL; + } + + return 0; +} + +static int convert_freq_to_divider(int freq) +{ + if (!freq) { + return 0; + } + + int divider = 0; + /* note: this causes a bit different speed than exact number. */ + divider = SDHC_CLOCK / (2 * freq); + + return divider; +} + +#define DEFINE_SDHC_MAX32(_num) \ + PINCTRL_DT_INST_DEFINE(_num); \ + static struct sdhc_max32_data sdhc_max32_data_##_num; \ + static const struct sdhc_max32_config sdhc_max32_config_##_num = { \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \ + .power_delay_ms = DT_INST_PROP(_num, power_delay_ms), \ + .bus_volt = MXC_SDHC_Bus_Voltage_1_8 + DT_ENUM_IDX_OR(_num, sd_bus_voltage, 0), \ + .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \ + .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \ + .perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \ + }; \ + DEVICE_DT_INST_DEFINE(_num, sdhc_max32_init, NULL, &sdhc_max32_data_##_num, \ + &sdhc_max32_config_##_num, POST_KERNEL, 2, &sdhc_max32_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(DEFINE_SDHC_MAX32) From 7f331d1127f8b848b453334d7bc50e49f1ac3ad7 Mon Sep 17 00:00:00 2001 From: Mert Ekren Date: Thu, 3 Oct 2024 20:50:58 +0300 Subject: [PATCH 3/7] dts: Add MAX32666 SDHC nodes and bindings Include sdhc0 in MAX32666 devicetree and add devicetree bindings for MAX32 SDHC driver Signed-off-by: Mert Ekren --- dts/arm/adi/max32/max32666.dtsi | 15 +++++++++++++++ dts/bindings/sdhc/adi,max32-sdhc.yaml | 24 ++++++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 dts/bindings/sdhc/adi,max32-sdhc.yaml diff --git a/dts/arm/adi/max32/max32666.dtsi b/dts/arm/adi/max32/max32666.dtsi index e697a912b411f9..88b00ea8045227 100644 --- a/dts/arm/adi/max32/max32666.dtsi +++ b/dts/arm/adi/max32/max32666.dtsi @@ -174,5 +174,20 @@ interrupts = <67 0>; status = "disabled"; }; + + sdhc0: sdhc@400b6000 { + compatible = "adi,max32-sdhc"; + reg = <0x400b6000 0x1000>; + interrupts = <66 0>; + status = "disabled"; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "disabled"; + disk-name = "SD"; + }; + power-delay-ms = <1500>; + sd-bus-voltage = "3V3"; + clocks = <&gcr ADI_MAX32_CLOCK_BUS1 10>; + }; }; }; diff --git a/dts/bindings/sdhc/adi,max32-sdhc.yaml b/dts/bindings/sdhc/adi,max32-sdhc.yaml new file mode 100644 index 00000000000000..c56c96125ea0f2 --- /dev/null +++ b/dts/bindings/sdhc/adi,max32-sdhc.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: ADI MAX32 SDHC + +compatible: "adi,max32-sdhc" + +include: [sdhc.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + sd-bus-voltage: + type: string + description: | + - SDHC Bus Voltage Selection + - 1.8V + - 3.0V + - 3.3V + enum: + - 1V8 + - 3V0 + - 3V3 From 00e8c389865b92305c1491e630d5ebbfb55dad43 Mon Sep 17 00:00:00 2001 From: Mert Ekren Date: Thu, 3 Oct 2024 20:53:37 +0300 Subject: [PATCH 4/7] boards: Add SDHC driver for MAX32666FTHR Add SDHC to supported list for MAX32666FTHR Signed-off-by: Mert Ekren --- boards/adi/max32666fthr/doc/index.rst | 2 + .../max32666fthr_max32666_cpu0.dts | 47 +++++++++++++++++++ .../max32666fthr_max32666_cpu0.yaml | 1 + 3 files changed, 50 insertions(+) diff --git a/boards/adi/max32666fthr/doc/index.rst b/boards/adi/max32666fthr/doc/index.rst index 1cd8a999de1c50..49371965775db2 100644 --- a/boards/adi/max32666fthr/doc/index.rst +++ b/boards/adi/max32666fthr/doc/index.rst @@ -126,6 +126,8 @@ Below interfaces are supported by Zephyr on MAX32666FTHR. +-----------+------------+-------------------------------------+ | Flash | on-chip | flash | +-----------+------------+-------------------------------------+ +| SDHC | on-chip | sd host controller | ++-----------+------------+-------------------------------------+ Connections and IOs =================== diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts index 02b45bda3db557..cc8fbf11e07089 100644 --- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts @@ -55,6 +55,7 @@ led2 = &led3; sw0 = &pb1; watchdog0 = &wdt0; + sdhc0 = &sdhc0; }; /* Used for accessing other pins */ @@ -134,3 +135,49 @@ pinctrl-0 = <&owm_io_p0_12>; pinctrl-names = "default"; }; + +&sdhc0 { + pinctrl-0 = <&sdhc_dat3_p1_0 &sdhc_cmd_p1_1 &sdhc_dat0_p1_2 &sdhc_clk_p1_3 + &sdhc_dat1_p1_4 &sdhc_dat2_p1_5 &sdhc_wp_p1_6 &sdhc_cdn_p1_7>; + pinctrl-names = "default"; +}; + +&sdhc_dat3_p1_0 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_cmd_p1_1 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_dat0_p1_2 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_clk_p1_3 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_dat1_p1_4 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_dat2_p1_5 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_wp_p1_6 { + power-source = ; + drive-strength = <1>; +}; + +&sdhc_cdn_p1_7 { + power-source = ; + drive-strength = <1>; +}; diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml index c40294e0ae33c3..773edff93eda0d 100644 --- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml @@ -21,5 +21,6 @@ supported: - pwm - w1 - flash + - sdhc ram: 560 flash: 1024 From e45f3f378408aebc93e9f8a5001b6bfe986ab31f Mon Sep 17 00:00:00 2001 From: Mert Ekren Date: Thu, 12 Sep 2024 08:19:18 +0300 Subject: [PATCH 5/7] samples: drivers: sdhc: fs_sample: Add MAX32666fthr Add MAX32666fthr for fs_sample testing Signed-off-by: Mert Ekren --- .../fs_sample/boards/max32666fthr_max32666_cpu0.conf | 3 +++ .../boards/max32666fthr_max32666_cpu0.overlay | 12 ++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.conf create mode 100644 samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.overlay diff --git a/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.conf b/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.conf new file mode 100644 index 00000000000000..7b52334dee751d --- /dev/null +++ b/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.conf @@ -0,0 +1,3 @@ +CONFIG_SDMMC_SUBSYS=y +CONFIG_SDHC=y +CONFIG_LOG=n diff --git a/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.overlay b/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.overlay new file mode 100644 index 00000000000000..f5d549b24ab01e --- /dev/null +++ b/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&sdhc0 { + status = "okay"; + mmc { + status = "okay"; + }; +}; From adb1f73faf38db1343b19df63c948dea907e18ea Mon Sep 17 00:00:00 2001 From: Mert Ekren Date: Thu, 12 Sep 2024 08:21:17 +0300 Subject: [PATCH 6/7] tests: drivers: sdhc: Add MAX32666fthr Add MAX32666fthr for sdhc api testing Signed-off-by: Mert Ekren --- .../sdhc/boards/max32666fthr_max32666_cpu0.overlay | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 tests/drivers/sdhc/boards/max32666fthr_max32666_cpu0.overlay diff --git a/tests/drivers/sdhc/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/sdhc/boards/max32666fthr_max32666_cpu0.overlay new file mode 100644 index 00000000000000..9a03822fe8c669 --- /dev/null +++ b/tests/drivers/sdhc/boards/max32666fthr_max32666_cpu0.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&sdhc0 { + status = "okay"; + mmc: mmc { + status = "okay"; + }; +}; From 52817278ba401c259e6ca15684c6d6a21e2084cf Mon Sep 17 00:00:00 2001 From: Mert Ekren Date: Thu, 9 Jan 2025 08:15:40 +0300 Subject: [PATCH 7/7] tests: drivers: sdhc: Add MAX32666fthr to disk performance test Add MAX32666fthr sdhc to tests/drivers/disk/disk_performance Signed-off-by: Mert Ekren --- .../boards/max32666fthr_max32666_cpu0.conf | 2 ++ .../boards/max32666fthr_max32666_cpu0.overlay | 12 ++++++++++++ 2 files changed, 14 insertions(+) create mode 100644 tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.conf create mode 100644 tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.overlay diff --git a/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.conf b/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.conf new file mode 100644 index 00000000000000..ecf4f8f9d4b365 --- /dev/null +++ b/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.conf @@ -0,0 +1,2 @@ +CONFIG_SDMMC_SUBSYS=y +CONFIG_SDHC=y diff --git a/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.overlay new file mode 100644 index 00000000000000..9a03822fe8c669 --- /dev/null +++ b/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.overlay @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&sdhc0 { + status = "okay"; + mmc: mmc { + status = "okay"; + }; +};