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Refactor CMSIS Includes #1525

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Refactor CMSIS Includes #1525

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f6307ef
refactor cachel1_armv7.h
Devilbinder Jul 12, 2022
47342ef
updated head
Devilbinder Jul 12, 2022
2deaded
refactor cmsis_armclang_ltm.h
Devilbinder Jul 12, 2022
cff9a9a
refactor cmsis_armclang.h
Devilbinder Jul 12, 2022
ed3ebf6
header
Devilbinder Jul 12, 2022
8e42b5a
refactor cmsis_gcc.h
Devilbinder Jul 12, 2022
97bbbf2
refactor cmsis_iccarm.h
Devilbinder Jul 12, 2022
a0aa510
refactor core_armv8mbl.h
Devilbinder Jul 12, 2022
4247f98
refactor core_armv8mml.h
Devilbinder Jul 12, 2022
c362b9d
header
Devilbinder Jul 12, 2022
90ee434
refactor if statements
Devilbinder Jul 12, 2022
f2a611c
change versions
Devilbinder Jul 12, 2022
433dea1
fix get enable irq
Devilbinder Jul 17, 2022
1150437
update headers
Devilbinder Jul 18, 2022
a9f1ecc
Merge branch 'develop' into refactor
Devilbinder Jul 31, 2022
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119 changes: 65 additions & 54 deletions CMSIS/Core/Include/cachel1_armv7.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.2
* @date 22. June 2022
* @version V1.0.3
* @date 12. July 2022
******************************************************************************/
/*
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -57,8 +57,10 @@
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */

if (SCB->CCR & SCB_CCR_IC_Msk){ /* return if ICache is already enabled */
return;
}

__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
Expand Down Expand Up @@ -115,21 +117,23 @@ __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
if ( isize <= 0 ) {
return;
}

__DSB();
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;

do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();

__DSB();
__ISB();
}
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );

__DSB();
__ISB();
#endif
}

Expand All @@ -145,13 +149,14 @@ __STATIC_FORCEINLINE void SCB_EnableDCache (void)
uint32_t sets;
uint32_t ways;

if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
if (SCB->CCR & SCB_CCR_DC_Msk){ /* return if DCache is already enabled */
return;
}

SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();

ccsidr = SCB->CCSIDR;

/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
Expand Down Expand Up @@ -351,21 +356,23 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
if ( dsize <= 0 ) {
return;
}

__DSB();
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();

__DSB();
__ISB();
}
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );

__DSB();
__ISB();
#endif
}

Expand All @@ -381,21 +388,23 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
if ( dsize <= 0 ) {
return;
}

__DSB();
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();

__DSB();
__ISB();
}
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );

__DSB();
__ISB();
#endif
}

Expand All @@ -411,21 +420,23 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
if ( dsize <= 0 ) {
return;
}

__DSB();
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();

__DSB();
__ISB();
}
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );

__DSB();
__ISB();
#endif
}

Expand Down
48 changes: 24 additions & 24 deletions CMSIS/Core/Include/cmsis_armclang.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
* @version V5.4.4
* @date 30. May 2022
* @version V5.4.5
* @date 12. July 2022
******************************************************************************/
/*
* Copyright (c) 2009-2022 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -427,7 +427,7 @@ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
uint32_t result;

__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
return result;
}


Expand Down Expand Up @@ -472,7 +472,7 @@ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
uint32_t result;

__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
return(result);
return result;
}


Expand Down Expand Up @@ -533,7 +533,7 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
return max;
}
else if (val < min)
if (val < min)
{
return min;
}
Expand All @@ -557,7 +557,7 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
return max;
}
else if (val < 0)
if (val < 0)
{
return 0U;
}
Expand Down Expand Up @@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
uint32_t result;

__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
return(result);
return result;
}


Expand Down Expand Up @@ -764,7 +764,7 @@ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
uint32_t result;

__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -779,7 +779,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
uint32_t result;

__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
return(result);
return result;
}
#endif

Expand Down Expand Up @@ -820,7 +820,7 @@ __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
uint32_t result;

__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -834,7 +834,7 @@ __STATIC_FORCEINLINE uint32_t __get_APSR(void)
uint32_t result;

__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -848,7 +848,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
uint32_t result;

__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -862,7 +862,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
uint32_t result;

__ASM volatile ("MRS %0, psp" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -877,7 +877,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
uint32_t result;

__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return(result);
return result;
}
#endif

Expand Down Expand Up @@ -916,7 +916,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
uint32_t result;

__ASM volatile ("MRS %0, msp" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -931,7 +931,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
uint32_t result;

__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return(result);
return result;
}
#endif

Expand Down Expand Up @@ -971,7 +971,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
uint32_t result;

__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -997,7 +997,7 @@ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
uint32_t result;

__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -1012,7 +1012,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
uint32_t result;

__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
return(result);
return result;
}
#endif

Expand Down Expand Up @@ -1077,7 +1077,7 @@ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
uint32_t result;

__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -1092,7 +1092,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
uint32_t result;

__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
return(result);
return result;
}
#endif

Expand Down Expand Up @@ -1143,7 +1143,7 @@ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
uint32_t result;

__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
return result;
}


Expand All @@ -1158,7 +1158,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
uint32_t result;

__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
return(result);
return result;
}
#endif

Expand Down Expand Up @@ -1493,7 +1493,7 @@ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
int32_t result;

__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
return result;
}

#endif /* (__ARM_FEATURE_DSP == 1) */
Expand Down
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