Fix CodeQL issues

ARM-software · Oct 26, 2023 · fc28c8d · fc28c8d
1 parent b7a15a7
commit fc28c8d
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Showing 12 changed files with 51 additions and 61 deletions.
diff --git a/CMSIS/Core/Include/a-profile/cmsis_cp15.h b/CMSIS/Core/Include/a-profile/cmsis_cp15.h
@@ -22,15 +22,15 @@
  * limitations under the License.
  */
 
+#ifndef __CMSIS_CP15_H
+#define __CMSIS_CP15_H
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
-#ifndef __CMSIS_CP15_H
-#define __CMSIS_CP15_H
-
 /** \brief  Get ACTLR
     \return               Auxiliary Control register value
  */
@@ -253,8 +253,7 @@ __STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
   __set_CP(15, 0, mvbar, 12, 0, 1);
 }
 
-#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
-    defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
     defined(DOXYGEN)
 
 /** \brief  Set CNTFRQ
@@ -432,7 +431,6 @@ __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
  */
 __STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
 {
-//  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
   __set_CP(15, 2, value, 0, 0, 0);
 }
 
@@ -442,27 +440,16 @@ __STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
 __STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
 {
   uint32_t result;
-//  __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
   __get_CP(15, 2, result, 0, 0, 0);
   return result;
 }
 
-/** \brief  Set CCSIDR
-    \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
- */
-CMSIS_DEPRECATED
-__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
-{
-  __set_CSSELR(value);
-}
-
 /** \brief  Get CCSIDR
     \return CCSIDR Register value
  */
 __STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
 {
   uint32_t result;
-//  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
   __get_CP(15, 1, result, 0, 0, 0);
   return result;
 }
@@ -473,7 +460,6 @@ __STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
 __STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
 {
   uint32_t result;
-//  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
   __get_CP(15, 1, result, 0, 0, 1);
   return result;
 }
@@ -482,23 +468,20 @@ __STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
  */
 __STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
 {
-//  __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
   __set_CP(15, 0, value, 7, 6, 2);
 }
 
 /** \brief  Set DCCSW
  */
 __STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
 {
-//  __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
   __set_CP(15, 0, value, 7, 10, 2);
 }
 
 /** \brief  Set DCCISW
  */
 __STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
 {
-//  __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
   __set_CP(15, 0, value, 7, 14, 2);
 }
 

diff --git a/CMSIS/Core/Include/a-profile/irq_ctrl.h b/CMSIS/Core/Include/a-profile/irq_ctrl.h
@@ -22,15 +22,15 @@
  * limitations under the License.
  */
 
+#ifndef IRQ_CTRL_H_
+#define IRQ_CTRL_H_
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
-#ifndef IRQ_CTRL_H_
-#define IRQ_CTRL_H_
-
 #include <stdint.h>
 
 #ifndef IRQHANDLER_T

diff --git a/CMSIS/Core/Include/core_ca.h b/CMSIS/Core/Include/core_ca.h
@@ -22,15 +22,15 @@
  * limitations under the License.
  */
 
+#ifndef __CORE_CA_H_GENERIC
+#define __CORE_CA_H_GENERIC
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header   /* treat file as system include file */
 #endif
 
-#ifndef __CORE_CA_H_GENERIC
-#define __CORE_CA_H_GENERIC
-
 #ifdef __cplusplus
  extern "C" {
 #endif
@@ -131,6 +131,12 @@
 #ifndef __CORE_CA_H_DEPENDANT
 #define __CORE_CA_H_DEPENDANT
 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
 #ifdef __cplusplus
  extern "C" {
 #endif
@@ -675,7 +681,8 @@ typedef union
 /**
  \brief  Union type to access the L2C_310 Cache Controller.
 */
-#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+#if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \
+     defined(DOXYGEN)
 typedef struct
 {
   __IM  uint32_t CACHE_ID;                   /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register               */
@@ -738,7 +745,8 @@ typedef struct
 #define L2C_310           ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
 #endif
 
-#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+#if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \
+    defined(DOXYGEN)
 
 /** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
 */
@@ -1078,7 +1086,8 @@ typedef struct
 #define GICInterface_DIR_INTID(x)           (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk)
 #endif /*  (__GIC_PRESENT == 1U) || defined(DOXYGEN) */
 
-#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+     defined(DOXYGEN)
 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
 /** \brief Structure type to access the Private Timer
 */
@@ -1280,7 +1289,7 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma
   uint32_t num_ways;
   uint32_t shift_way;
   uint32_t log2_linesize;
-   int32_t log2_num_ways;
+   uint8_t log2_num_ways;
 
   Dummy = level << 1U;
   /* set csselr, select ccsidr register */
@@ -1291,10 +1300,10 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma
   num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
   log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
   log2_num_ways = __log2_up(num_ways);
-  if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
+  if (log2_num_ways > 32U) {
     return; // FATAL ERROR
   }
-  shift_way = 32U - (uint32_t)log2_num_ways;
+  shift_way = 32U - log2_num_ways;
   for(int32_t way = num_ways-1; way >= 0; way--)
   {
     for(int32_t set = num_sets-1; set >= 0; set--)
@@ -1358,7 +1367,8 @@ __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
 }
 
 /* ##########################  L2 Cache functions  ################################# */
-#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
+#if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \
+     defined(DOXYGEN)
 /** \brief Cache Sync operation by writing CACHE_SYNC register.
 */
 __STATIC_INLINE void L2C_Sync(void)
@@ -1468,7 +1478,8 @@ __STATIC_INLINE void L2C_CleanInvPa (void *pa)
 #endif
 
 /* ##########################  GIC functions  ###################################### */
-#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
+#if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \
+     defined(DOXYGEN)
 
 /** \brief  Enable the interrupt distributor using the GIC's CTLR register.
 */
@@ -1854,7 +1865,8 @@ __STATIC_INLINE void GIC_Enable(void)
 #endif
 
 /* ##########################  Generic Timer functions  ############################ */
-#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
+#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+    defined(DOXYGEN)
 
 /* PL1 Physical Timer */
 #if (__CORTEX_A == 7U) || defined(DOXYGEN)

diff --git a/CMSIS/Core/Include/core_cm0.h b/CMSIS/Core/Include/core_cm0.h
@@ -581,7 +581,7 @@ typedef struct
   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+/*        NVIC_GetActive              not available for Cortex-M0 */
   #define NVIC_SetPriority            __NVIC_SetPriority
   #define NVIC_GetPriority            __NVIC_GetPriority
   #define NVIC_SystemReset            __NVIC_SystemReset

diff --git a/CMSIS/Core/Include/core_cm0plus.h b/CMSIS/Core/Include/core_cm0plus.h
@@ -699,7 +699,7 @@ typedef struct
   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+/*        NVIC_GetActive              not available for Cortex-M0+ */
   #define NVIC_SetPriority            __NVIC_SetPriority
   #define NVIC_GetPriority            __NVIC_GetPriority
   #define NVIC_SystemReset            __NVIC_SystemReset

diff --git a/CMSIS/Core/Include/core_cm23.h b/CMSIS/Core/Include/core_cm23.h
@@ -1458,8 +1458,8 @@ typedef struct
   #endif
   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 #else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+/*        NVIC_SetPriorityGrouping    not available for Cortex-M23 */
+/*        NVIC_GetPriorityGrouping    not available for Cortex-M23 */
   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
   #define NVIC_DisableIRQ             __NVIC_DisableIRQ

diff --git a/CMSIS/Core/Include/m-profile/armv7m_cachel1.h b/CMSIS/Core/Include/m-profile/armv7m_cachel1.h
@@ -22,15 +22,15 @@
  * limitations under the License.
  */
 
+#ifndef ARM_ARMV7M_CACHEL1_H
+#define ARM_ARMV7M_CACHEL1_H
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header    /* treat file as system include file */
 #endif
 
-#ifndef ARM_ARMV7M_CACHEL1_H
-#define ARM_ARMV7M_CACHEL1_H
-
 /**
   \ingroup  CMSIS_Core_FunctionInterface
   \defgroup CMSIS_Core_CacheFunctions Cache Functions

diff --git a/CMSIS/Core/Include/m-profile/armv7m_mpu.h b/CMSIS/Core/Include/m-profile/armv7m_mpu.h
@@ -22,15 +22,15 @@
  * limitations under the License.
  */
 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header    /* treat file as system include file */
 #endif
 
-#ifndef ARM_MPU_ARMV7_H
-#define ARM_MPU_ARMV7_H
-
 #define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
 #define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
 #define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes

diff --git a/CMSIS/Core/Include/m-profile/armv81m_pac.h b/CMSIS/Core/Include/m-profile/armv81m_pac.h
@@ -22,16 +22,15 @@
  * limitations under the License.
  */
 
+#ifndef PAC_ARMV81_H
+#define PAC_ARMV81_H
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header    /* treat file as system include file */
 #endif
 
-#ifndef PAC_ARMV81_H
-#define PAC_ARMV81_H
-
-
 /* ###################  PAC Key functions  ########################### */
 /**
   \ingroup  CMSIS_Core_FunctionInterface

diff --git a/CMSIS/Core/Include/m-profile/armv8m_mpu.h b/CMSIS/Core/Include/m-profile/armv8m_mpu.h
@@ -22,15 +22,15 @@
  * limitations under the License.
  */
 
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header    /* treat file as system include file */
 #endif
 
-#ifndef ARM_MPU_ARMV8_H
-#define ARM_MPU_ARMV8_H
-
 /** \brief Attribute for device memory (outer only) */
 #define ARM_MPU_ATTR_DEVICE                           ( 0U )
 

diff --git a/CMSIS/Core/Include/m-profile/armv8m_pmu.h b/CMSIS/Core/Include/m-profile/armv8m_pmu.h
@@ -22,15 +22,15 @@
  * limitations under the License.
  */
 
+#ifndef ARM_PMU_ARMV8_H
+#define ARM_PMU_ARMV8_H
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header    /* treat file as system include file */
 #endif
 
-#ifndef ARM_PMU_ARMV8_H
-#define ARM_PMU_ARMV8_H
-
 /**
  * \brief PMU Events
  * \note  See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.

diff --git a/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h b/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h
@@ -31,11 +31,7 @@
 #pragma GCC diagnostic ignored "-Wconversion"
 #pragma GCC diagnostic ignored "-Wunused-parameter"
 
-//#if (__ARM_ACLE >= 200)
-  #include <arm_acle.h>
-//#else
-//  #error Compiler must support ACLE V2.0
-//#endif /* (__ARM_ACLE >= 200) */
+#include <arm_acle.h>
 
 /* Fallback for __has_builtin */
 #ifndef __has_builtin