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HIP implementation #43

Merged
merged 38 commits into from
Jan 4, 2024
Merged

HIP implementation #43

merged 38 commits into from
Jan 4, 2024

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rcarson3
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@rcarson3 rcarson3 commented Feb 8, 2022

The current implementation now runs on AMD hardware successfully. I'm currently playing around with different ways to gain more performance which will probably require a few more small changes out of LLNL/ExaCMech#5 and LLNL/SNLS#3 . However, the initial HIP implementation is more or less now complete.

It compiles but the test suite does not work as expected at least when
trying to run on the GPU.
@rcarson3 rcarson3 self-assigned this Feb 8, 2022
@rcarson3 rcarson3 marked this pull request as draft February 8, 2022 01:12
@rcarson3 rcarson3 linked an issue Feb 11, 2022 that may be closed by this pull request
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Should pull this in after #42 -> #50 -> #45 are all merged in

@rcarson3 rcarson3 marked this pull request as ready for review June 1, 2022 21:07
@rcarson3 rcarson3 changed the title [WIP] HIP implementation HIP implementation Apr 17, 2023
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Note: this branch works quite well as of right now and we're getting decent speed-ups on Frontier with it. I just need to do some clean-up in the associated SNLS and ExaCMech PRs as well as within this PR before merging. Mainly, I just want to simplify some logic here and there so things are done a bit cleaner.

Tons of trials to get the dependencies correctly updated

Found out that 1 specific test was failing on the github CI. I have not been able to reproduce this on my local mac nor any of the various HPC systems I have access to at LLNL. So, I just disabled it only when running on the github CI. I'm not pleased with this solution but hey it gets the rest passing...
@rcarson3 rcarson3 merged commit 49d4045 into exaconstit-dev Jan 4, 2024
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Add HIP backened to run on AMD hardware
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