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Add tricore tc1.8 instructions #73

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@Changqing-JING Changqing-JING commented Jan 6, 2025

Add tricore tc1.8 instructions:

add.df
sub.df
madd.df
msub.df
mul.df
div.df
cmp.df
max.df
min.df
min.f
max.f
dftoi
dftoiz
dftoin
ftoin
dftou
dftouz
dftol
dftoul
dftoulz
abs.f
abs.df
dftolz
neg.df
neg.f
qseed.df
itodf
utodf
ltodf
ultodf
dftof
ftodf
div64
div64.u
rem64
rem64.u

A major change in tc18 instruction encoding is:
The n field can indicate mnemonics for instruction variant with 64bit register operand.
For example 6b 00 21 00 is add.f %d0,%d0,%d0.
6b 00 22 00 is add.df %e0,%e0,%e0

@XVilka
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XVilka commented Jan 6, 2025

@imbillow could you please take a look?

@Rot127 Rot127 changed the base branch from auto-sync to auto-sync-18 January 6, 2025 19:06
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Looks good to me. Let's wait for @imbillow review.

Also, please rebase your commit onto the latest auto-sync branch. I just updated it.

add.df
sub.df
madd.df
msub.df
mul.df
div.df
cmp.df
max.df
min.df
min.f
max.f
dftoi
dftoiz
dftoin
ftoin
dftou
dftouz
dftol
dftoul
dftoulz
abs.f
abs.df
dftolz
neg.df
neg.f
qseed.df
itodf
utodf
ltodf
ultodf
dftof
ftodf
@Changqing-JING
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Rebased to new auto-sync

div64
div64.u
rem64
rem64.u
@Changqing-JING
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Added a bit more instructions

div64
div64.u
rem64
rem64.u

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3 participants