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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 834 222

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 734 177

Repositories

Showing 10 of 110 repositories
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 257 Apache-2.0 76 21 13 Updated Jan 10, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 125 Apache-2.0 23 17 24 Updated Jan 10, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,084 Apache-2.0 610 316 (1 issue needs help) 164 Updated Jan 10, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 8 Apache-2.0 3 13 2 Updated Jan 10, 2025
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 11 Apache-2.0 3 7 0 Updated Jan 10, 2025
  • synlig Public

    SystemVerilog synthesis tool

    chipsalliance/synlig’s past year of commit activity
    Verilog 176 Apache-2.0 23 69 10 Updated Jan 10, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 35 LGPL-3.0 636 0 0 Updated Jan 10, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 99 Apache-2.0 46 110 56 Updated Jan 10, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 79 Apache-2.0 42 78 17 Updated Jan 10, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Jan 10, 2025
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