Doc: Update CMSIS-Core toolchain versions. Plus various clean ups.

CMSIS/Documentation/Doxygen/Core/src/mainpage.md

@@ -1,6 +1,6 @@
 # Overview {#mainpage}
 
-CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals.
+The **CMSIS-Core (Cortex-M)** component implements the basic run-time system for Arm Cortex-M devices and gives the user access to the processor core and the device peripherals.
 
 In detail it defines:
 
@@ -20,12 +20,12 @@ The following sections provide details about the CMSIS-Core (Cortex-M):
 \endif
  - \ref cmsis_core_files describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
  - \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
- - [API Reference](modules.html) describes the features and functions of the \ref device_h_pg in detail.
- - [Data Structures](annotated.html) describe the data structures of the \ref device_h_pg in detail.
+ - [**API Reference**](modules.html) describes the features and functions of the \ref device_h_pg in detail.
+ - [**Data Structures**](annotated.html) describe the data structures of the \ref device_h_pg in detail.
 
 ## Access to CMSIS-Core (Cortex-M)
 
-CMSIS-Core is actively maintained in [CMSIS 6 GitHub repository](https://github.com/ARM-software/CMSIS_6) and released as part of the [CMSIS Software Pack](../General/cmsis_pack.html).
+CMSIS-Core is actively maintained in the [**CMSIS 6 GitHub repository**](https://github.com/ARM-software/CMSIS_6) and released as part of the [**CMSIS Software Pack**](../General/cmsis_pack.html).
 
 The following directories and files relevant to CMSIS-Core (Cortex-M) are present in the **ARM::CMSIS** Pack:
 
@@ -46,6 +46,7 @@ CMSIS-Core supports the complete range of [Cortex-M processors](https://www.arm.
 **Cortex-M Generic User Guides**
 
 Following Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals:
+
  - [Cortex-M0 Devices Generic User Guide (Armv6-M architecture)](https://developer.arm.com/documentation/dui0497/latest/)
  - [Cortex-M0+ Devices Generic User Guide (Armv6-M architecture)](https://developer.arm.com/documentation/dui0662/latest/)
  - [Cortex-M3 Devices Generic User Guide (Armv7-M architecture)](https://developer.arm.com/documentation/dui0552/latest/)
@@ -57,11 +58,12 @@ Following Cortex-M Device Generic User Guides contain the programmers model and
  - [Cortex-M85 Devices Generic User Guide (Armv8.1-M architecture)](https://developer.arm.com/documentation/101928/latest/)
 
 CMSIS-Core also supports the following Cortex-M processor variants:
-- [Cortex-M1](https://developer.arm.com/Processors/Cortex-M1) is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).
-- [SecurCore SC000](https://developer.arm.com/Processors/SecurCore%20SC000) is designed specifically for smartcard and security applications (Armv6-M architecture).
-- [SecurCore SC300](https://developer.arm.com/Processors/SecurCore%20SC300) is designed specifically for smartcard and security applications (Armv7-M architecture).
-- [Cortex-M35P](https://developer.arm.com/Processors/Cortex-M35P) is a tamper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.
-- [STAR-MC1](https://www.armchina.com/mountain?infoId=160) is a variant of Armv8-M with TrustZone designed by Arm China.
+
+ - [Cortex-M1](https://developer.arm.com/Processors/Cortex-M1) is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).
+ - [SecurCore SC000](https://developer.arm.com/Processors/SecurCore%20SC000) is designed specifically for smartcard and security applications (Armv6-M architecture).
+ - [SecurCore SC300](https://developer.arm.com/Processors/SecurCore%20SC300) is designed specifically for smartcard and security applications (Armv7-M architecture).
+ - [Cortex-M35P](https://developer.arm.com/Processors/Cortex-M35P) is a tamper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.
+ - [STAR-MC1](https://www.armchina.com/mountain?infoId=160) is a variant of Armv8-M with TrustZone designed by Arm China.
 
 \anchor ARMv8M
 **Armv8-M and Armv8.1-M Architecture**
@@ -76,10 +78,9 @@ More information about Armv8.1-M architecture is available under [Arm Helium tec
 
 ##  Tested and Verified Toolchains {#tested_tools_sec}
 
-The \ref cmsis_core_files supplied by Arm have been tested and verified with the following toolchains:
+The \ref cmsis_core_files delivered with this CMSIS-Core release have been tested and verified with the following toolchains:
 
- - Arm: Arm Compiler 5.06 update 7 (not for Cortex-M23/33/35P/55/85, Armv8-M, Armv8.1-M)
- - Arm: Arm Compiler 6.16
- - Arm: Arm Compiler 6.6.4 (not for Cortex-M0/23/33/35P/55/85, Armv8-M, Armv8.1-M)
- - GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)
- - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
+ - Arm Compiler for Embedded 6.20
+ - IAR C/C++ Compiler for Arm 9.40
+ - GNU Arm Embedded Toolchain 12.2.1
+ - LLVM/Clang 17.0.1

CMSIS/Documentation/Doxygen/Core_A/src/mainpage.md

@@ -1,7 +1,8 @@
 # Overview {#mainpage}
 
-CMSIS-Core (Cortex-A) implements the basic run-time system for a Cortex-A device and gives the user access to the processor core and the device peripherals.
+The **CMSIS-Core (Cortex-A)** component implements the basic run-time system for a Cortex-A device and gives the user access to the processor core and the device peripherals.
 In detail it defines:
+
  - **Hardware Abstraction Layer (HAL)** for Cortex-A processor registers with standardized  definitions for the GIC, FPU, MMU, Cache, and core access functions.
  - **System exception names** to interface to system exceptions without having compatibility issues.
  - **Methods to organize header files** that makes it easy to learn new Cortex-A microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
@@ -10,15 +11,16 @@ In detail it defines:
  - A variable to determine the **system clock frequency** which simplifies the setup of the system timers.
 
 The following sections provide details about the CMSIS-Core (Cortex-A):
+
  - \ref using_pg describes the project setup and shows a simple program example.
  - \ref templates_pg describes the files of the CMSIS-Core (Cortex-A) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
  - \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
- - [API Reference](modules.html) describes the features and functions of the \ref device_h_pg in detail.
- - [Data Structures](annotated.html) describe the data structures of the \ref device_h_pg in detail.
+ - [**API Reference**](modules.html) describes the features and functions of the \ref device_h_pg in detail.
+ - [**Data Structures**](annotated.html) describe the data structures of the \ref device_h_pg in detail.
 
 ## Access to CMSIS-Core (Cortex-A)
 
-CMSIS-Core is actively maintained in [CMSIS 6 GitHub repository](https://github.com/ARM-software/CMSIS_6) and released as part of the [CMSIS Software Pack](../General/cmsis_pack.html).
+CMSIS-Core is actively maintained in the [**CMSIS 6 GitHub repository**](https://github.com/ARM-software/CMSIS_6) and released as part of the [**CMSIS Software Pack**](../General/cmsis_pack.html).
 
 The following directories and files relevant to CMSIS-Core (Cortex-A) are present in the **ARM::CMSIS** Pack:
 
@@ -30,7 +32,7 @@ Directory                         | Content
     ┣ 📂 Include        | \ref CMSIS_Processor_files.
      ┗ 📂 a-profile| Header files specific for Arm A-Profile.
     ┗ 📂 Template       | \ref template_files_sec
- 
+
 ## Processor Support {#ref_v7A}
 
 CMSIS supports a selected subset of [Cortex-A processors](https://www.arm.com/products/silicon-ip-cpu?families=cortex-m&showall=true).
@@ -39,15 +41,16 @@ CMSIS supports a selected subset of [Cortex-A processors](https://www.arm.com/pr
 **Cortex-A Technical Reference Manuals**
 
 The following Technical Reference Manuals describe the various Arm Cortex-A processors:
+
  - [Cortex-A5](https://developer.arm.com/documentation/ddi0433) (Armv7-A architecture)
  - [Cortex-A7](https://developer.arm.com/documentation/ddi0464) (Armv7-A architecture)
  - [Cortex-A9](https://developer.arm.com/documentation/100511) (Armv7-A architecture)
 
 ## Tested and Verified Toolchains {#tested_tools_sec}
 
-The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
- - Arm: Arm Compiler 5.06 update 7
- - Arm: Arm Compiler 6.16
- - Arm: Arm Compiler 6.6.4
- - GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)
- - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
+The \ref templates_pg delivered with this CMSIS-Core release have been tested and verified with the following toolchains:
+
+ - Arm Compiler for Embedded 6.20
+ - IAR C/C++ Compiler for Arm 9.40
+ - GNU Arm Embedded Toolchain 12.2.1
+ - LLVM/Clang 17.0.1

CMSIS/Documentation/Doxygen/Driver/src/mainpage.md

@@ -1,8 +1,8 @@
 # Overview {#mainpage}
 
-The **CMSIS-Driver** specifies generic driver interfaces for peripherals commonly used in embedded systems with Arm® Cortex® processors.
+**CMSIS-Driver** specifies generic driver interfaces for peripherals commonly used in embedded systems with Arm® Cortex® processors.
 
-User applications and middleware components can control such peripherals using the [CMSIS-Driver API](modules.html) and so achieve better code reuse and simpler integration in various ecosystems. The API is designed to be generic and independent of a specific RTOS making it reusable across a wide range of supported microcontroller devices.
+User applications and middleware components can control such peripherals using the [**CMSIS-Driver API**](modules.html) and so achieve better code reuse and simpler integration in various ecosystems. The API is designed to be generic and independent of a specific RTOS making it reusable across a wide range of supported microcontroller devices.
 
 The following block diagram shows an exemplary set up for various drivers.
 
@@ -14,36 +14,36 @@ The standard CMSIS-Driver interfaces connect microcontroller peripherals with mi
 
 Using CMSIS-Driver provides great benefits to the embedded developers and software vendors:
 
-- The CMSIS-Driver API covers \ref cmsis_drv_interfaces "many common peripherals" present in modern embedded systems for sensor interaction, data storage, communication and graphics.
-- The unified API follows the similar design principles across all peripherals. This reduces learning efforts and increases developers' productivity. See \ref theoryOperation for details.
-- Driver templates files provide code sceletons that help to get started with implementations for specific peripherals. See \ref cmsis_driver_files.
-- Support for multiple driver instances with \ref AccessStruct.
-- \ref driverValidation "Driver-Validation Suite" provides a set of tests to verify compatibility to CMSIS-Driver API definitions.
+ - The CMSIS-Driver API covers \ref cmsis_drv_interfaces "many common peripherals" present in modern embedded systems for sensor interaction, data storage, communication and graphics.
+ - The unified API follows the similar design principles across all peripherals. This reduces learning efforts and increases developers' productivity. See \ref theoryOperation for details.
+ - Driver templates files provide code sceletons that help to get started with implementations for specific peripherals. See \ref cmsis_driver_files.
+ - Support for multiple driver instances with \ref AccessStruct.
+ - \ref driverValidation "Driver-Validation Suite" provides a set of tests to verify compatibility to CMSIS-Driver API definitions.
 
 ## Covered Interfaces {#cmsis_drv_interfaces}
 
 CMSIS-Driver APIs are defined for the following driver interfaces:
 
-  - \ref can_interface_gr "CAN": Interface to CAN bus peripheral.
-  - \ref eth_interface_gr "Ethernet": Interface to Ethernet MAC and PHY peripheral.
-  - \ref i2c_interface_gr "I2C": Multi-master Serial Single-Ended Bus interface driver.
-  - \ref mci_interface_gr "MCI": Memory Card Interface for SD/MMC memory.
-  - \ref nand_interface_gr "NAND": NAND Flash Memory interface driver.
-  - \ref flash_interface_gr "Flash": Flash Memory interface driver.
-  - \ref sai_interface_gr "SAI": Serial audio interface driver (I2s, PCM, AC'97, TDM, MSB/LSB Justified).
-  - \ref spi_interface_gr "SPI": Serial Peripheral Interface Bus driver.
-  - \ref storage_interface_gr "Storage": Storage device interface driver.
-  - \ref usart_interface_gr "USART": Universal Synchronous and Asynchronous Receiver/Transmitter interface driver.
-  - \ref usb_interface_gr "USB": Interface driver for USB Host and USB Device communication.
-  - \ref gpio_interface_gr "GPIO": General-purpose Input/Output driver.
-  - \ref vio_interface_gr "VIO": API for virtual I/Os (VIO).
-  - \ref wifi_interface_gr "WiFi": Interface driver for wireless communication.
+ - \ref can_interface_gr "CAN": Interface to CAN bus peripheral.
+ - \ref eth_interface_gr "Ethernet": Interface to Ethernet MAC and PHY peripheral.
+ - \ref i2c_interface_gr "I2C": Multi-master Serial Single-Ended Bus interface driver.
+ - \ref mci_interface_gr "MCI": Memory Card Interface for SD/MMC memory.
+ - \ref nand_interface_gr "NAND": NAND Flash Memory interface driver.
+ - \ref flash_interface_gr "Flash": Flash Memory interface driver.
+ - \ref sai_interface_gr "SAI": Serial audio interface driver (I2s, PCM, AC'97, TDM, MSB/LSB Justified).
+ - \ref spi_interface_gr "SPI": Serial Peripheral Interface Bus driver.
+ - \ref storage_interface_gr "Storage": Storage device interface driver.
+ - \ref usart_interface_gr "USART": Universal Synchronous and Asynchronous Receiver/Transmitter interface driver.
+ - \ref usb_interface_gr "USB": Interface driver for USB Host and USB Device communication.
+ - \ref gpio_interface_gr "GPIO": General-purpose Input/Output driver.
+ - \ref vio_interface_gr "VIO": API for virtual I/Os (VIO).
+ - \ref wifi_interface_gr "WiFi": Interface driver for wireless communication.
 
 A list of current CMSIS-Driver implementations is available \ref listOfImplementations "here".
 
 ## Access to CMSIS-Driver {#cmsis_driver_pack}
 
-CMSIS-Driver intefaces are actively maintained in [CMSIS 6 GitHub repository](https://github.com/ARM-software/CMSIS_6) and released as part of the [CMSIS Software Pack](../General/cmsis_pack.html).
+CMSIS-Driver intefaces are actively maintained in the [**CMSIS 6 GitHub repository**](https://github.com/ARM-software/CMSIS_6) and released as part of the [**CMSIS Software Pack**](../General/cmsis_pack.html).
 
 The CMSIS Software Pack publishes the API Interface under the Component Class **CMSIS Driver** with header files and a documentation. These header files are the reference for the implementation of the standardized peripheral driver interfaces.
 

CMSIS/Documentation/Doxygen/General/src/cmsis_sw_pack.md

@@ -14,3 +14,5 @@ File/Directory        | Content
    ┗ 📂 RTOS2          | API header files and OS tick implementations for the [CMSIS-RTOS2](../RTOS2/index.html)
 📄 ARM.CMSIS.pdsc      | Package description file in CMSIS-Pack format
 📄 LICENSE             | CMSIS License Agreement (Apache 2.0)
+
+Section \ref cmsis_components provides links to CMSIS packs and repositories of other CMSIS components that are delivered separately and are not part of ARM::CMSIS pack.

CMSIS/Documentation/Doxygen/General/src/mainpage.md

@@ -54,7 +54,7 @@ CMSIS has been created to help the industry in standardization. It enables consi
     <span class="tileh h2">CMSIS-Toolbox</span><span class="tiletxt">A set of command-line tools to work with software packs</span><span class="tilelinks"><a href="https://github.com/Open-CMSIS-Pack/cmsis-toolbox/blob/main/README.md">Guide</a> | <a href="https://github.com/Open-CMSIS-Pack/cmsis-toolbox">GitHub</a></span>
   </div>
   <div class="tile" onclick="document.location='../Stream/index.html'">
-    <span class="tileh h2">CMSIS-Stream</span><span class="tiletxt">Peripheral description of a device for debug view</span><span class="tilelinks"><a href="https://github.com/ARM-software/CMSIS-Stream/blob/main/README.md">Guide</a> | <a href="https://github.com/ARM-software/cmsis-stream">GitHub</a></span>
+    <span class="tileh h2">CMSIS-Stream</span><span class="tiletxt">Tools and methods for optimizing DSP/ML block data streams</span><span class="tilelinks"><a href="https://github.com/ARM-software/CMSIS-Stream/blob/main/README.md">Guide</a> | <a href="https://github.com/ARM-software/cmsis-stream">GitHub</a></span>
   </div>
   <div class="tile" onclick="document.location='../DAP/index.html'">
     <span class="tileh h2">CMSIS-DAP</span><span class="tiletxt">Firmware for debug units interfacing to CoreSight Debug Access Port</span><span class="tilelinks"><a href="https://arm-software.github.io/CMSIS-DAP/latest/">Guide</a> | <a href="https://github.com/ARM-software/CMSIS-DAP">GitHub</a></span>

CMSIS/Documentation/Doxygen/RTOS2/src/mainpage.md

@@ -2,7 +2,7 @@
 
 Modern embedded applications often need to concurrently execute multiple activities such as sensor readings, connectivity, machine-learning algorithms, graphics display and others. A real-time operating system (RTOS) equips users with necessary mechanisms that simplify implementation of complex programs and ensure their reliable operation with deterministic timing.
 
-The **CMSIS-RTOS2** specifies a generic RTOS interface over real-time OS kernels running on Arm® Cortex® processor-based devices. Applications and middleware components can \ref usingOS2 "use CMSIS_RTOS2 API" for better code reuse and simpler integration in various software ecosystems.
+**CMSIS-RTOS2** specifies a generic RTOS interface over real-time OS kernels running on Arm® Cortex® processor-based devices. Applications and middleware components can \ref usingOS2 "use CMSIS_RTOS2 API" for better code reuse and simpler integration in various software ecosystems.
 
 CMSIS-RTOS2 also specifies a standard \ref CMSIS_RTOS_TickAPI "OS Tick interface" for use by RTOS kernels. It provides several OS tick implementations for simple kernel porting to different Cortex-M and Cortex-A processors.
 
@@ -58,7 +58,7 @@ Many popular RTOS kernels include support for CMSIS-RTOS2 API:
 
 ## Access to CMSIS-RTOS2 {#rtos2_access}
 
-CMSIS-RTOS2 and OS Tick intefaces are actively maintained in [**CMSIS 6 GitHub repository**](https://github.com/ARM-software/CMSIS_6) and provided as part of the [CMSIS Software Pack](../General/cmsis_pack.html).
+CMSIS-RTOS2 and OS Tick intefaces are actively maintained in the [**CMSIS 6 GitHub repository**](https://github.com/ARM-software/CMSIS_6) and provided as part of the [**CMSIS Software Pack**](../General/cmsis_pack.html).
 
 The following files and directories relevant to CMSIS-RTOS2 are present in the **ARM::CMSIS** Pack:
 

CMSIS/Documentation/Doxygen/RTOS2/src/validation.md

@@ -1,5 +1,5 @@
 # RTOS Validation {#rtosValidation}
 
-[CMSIS-RTOS2 Validation](https://github.com/ARM-software/CMSIS-RTOS2_Validation) framework is available to verify operation of CMSIS-RTOS2 implementations. The test cases validate the functional behavior, test invalid parameters and call management functions from Interrupt Service Routines (ISRs). The test projects are provided based on the [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools) and integrate well into CI workflows.
+The [**CMSIS-RTOS2 Validation**](https://github.com/ARM-software/CMSIS-RTOS2_Validation) framework is available to verify operation of CMSIS-RTOS2 implementations. The test cases validate the functional behavior, test invalid parameters and call management functions from Interrupt Service Routines (ISRs). The test projects are provided based on the [**CMSIS-Toolbox**](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools) and integrate well into CI workflows.
 
-For details about the scope and usage, please, refer to the [CMSIS-RTOS2 Validation manual](https://arm-software.github.io/CMSIS-RTOS2_Validation/main/index.html).
+For details about the scope and usage, please, refer to the [**CMSIS-RTOS2 Validation manual**](https://arm-software.github.io/CMSIS-RTOS2_Validation/main/index.html).