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CMake/Formatting work
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dashodanger committed Sep 9, 2024
1 parent f7493da commit e81111e
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22 changes: 2 additions & 20 deletions CMakeLists.txt
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Expand Up @@ -10,6 +10,8 @@ project(
VERSION 0.1.0
)

set(CMAKE_C_STANDARD 11)
set(CMAKE_C_STANDARD_REQUIRED True)
set(CMAKE_CXX_STANDARD 17)
set(CMAKE_CXX_STANDARD_REQUIRED True)

Expand Down Expand Up @@ -126,25 +128,5 @@ else()
add_definitions(-DEDGE_GL_ES2)
endif()

# Profiling
if (EDGE_PROFILING)
add_definitions("-DEDGE_PROFILING" "-DTRACY_ENABLE")
include(FetchContent)
FetchContent_Declare (
tracy
GIT_REPOSITORY https://github.com/wolfpld/tracy.git
GIT_TAG master
GIT_SHALLOW TRUE
GIT_PROGRESS TRUE
)
option (TRACY_ON_DEMAND "" OFF)
option (TRACY_CALLSTACK "" ON)
FetchContent_MakeAvailable (tracy)
endif()

include_directories(libraries/hmm)
include_directories(libraries/sokol)
include_directories(libraries/tracy)

add_subdirectory(libraries)
add_subdirectory(source_files)
3 changes: 0 additions & 3 deletions docs/licenses/License Attribution.txt
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Expand Up @@ -121,9 +121,6 @@ PL_MPEG library - Copyright(c) 2019 Dominic Szablewski

PNPOLY algorithm - Copyright (c) 1970-2003 Wm. Randolph Franklin

utf8proc library - Copyright (c) 2014-2021 Steven G. Johnson, Jiahao Chen, Tony Kelman,
Jonas Fonseca, et al

===========================================================================================
Public Domain
===========================================================================================
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17 changes: 13 additions & 4 deletions libraries/CMakeLists.txt
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@@ -1,13 +1,22 @@
add_subdirectory(almostequals)
add_subdirectory(crsid)
add_subdirectory(dr_libs)
add_subdirectory(fmmidi)
add_subdirectory(fluidlite)
if (NOT EDGE_GL_ES2)
add_subdirectory(glad)
else()
add_subdirectory(gl4es)
endif()
add_subdirectory(fmmidi)
add_subdirectory(fluidlite)
add_subdirectory(hmm)
add_subdirectory(libRAD)
add_subdirectory(libvwad)
add_subdirectory(lua)
add_subdirectory(m4p)
add_subdirectory(minivorbis)
add_subdirectory(miniz)
add_subdirectory(lua)
add_subdirectory(libvwad)
add_subdirectory(pl_mpeg)
add_subdirectory(sokol)
add_subdirectory(stb)
add_subdirectory(superfasthash)
add_subdirectory(tracy)
8 changes: 8 additions & 0 deletions libraries/almostequals/CMakeLists.txt
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@@ -0,0 +1,8 @@
##########################################
# AlmostEquals
##########################################

add_library(almostequals INTERFACE)

target_include_directories(almostequals INTERFACE
${CMAKE_CURRENT_SOURCE_DIR})
221 changes: 140 additions & 81 deletions libraries/crsid/C64/CIA.c
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@@ -1,93 +1,152 @@

//cRSID CIA emulation


void cRSID_createCIAchip (cRSID_C64instance* C64, cRSID_CIAinstance* CIA, unsigned short baseaddress) {
CIA->C64 = C64;
CIA->ChipModel = 0;
CIA->BaseAddress = baseaddress;
CIA->BasePtrWR = &C64->IObankWR[baseaddress]; CIA->BasePtrRD = &C64->IObankRD[baseaddress];
cRSID_initCIAchip(CIA);
// cRSID CIA emulation

void cRSID_createCIAchip(cRSID_C64instance *C64, cRSID_CIAinstance *CIA, unsigned short baseaddress)
{
CIA->C64 = C64;
CIA->ChipModel = 0;
CIA->BaseAddress = baseaddress;
CIA->BasePtrWR = &C64->IObankWR[baseaddress];
CIA->BasePtrRD = &C64->IObankRD[baseaddress];
cRSID_initCIAchip(CIA);
}


void cRSID_initCIAchip (cRSID_CIAinstance* CIA) {
unsigned char i;
for (i=0; i<0x10; ++i) CIA->BasePtrWR[i] = CIA->BasePtrRD[i] = 0x00;
void cRSID_initCIAchip(cRSID_CIAinstance *CIA)
{
unsigned char i;
for (i = 0; i < 0x10; ++i)
CIA->BasePtrWR[i] = CIA->BasePtrRD[i] = 0x00;
}


static inline char cRSID_emulateCIA (cRSID_CIAinstance* CIA, char cycles) {
static int Tmp;

enum CIAregisters { PORTA=0, PORTB=1, DDRA=2, DDRB=3,
TIMERAL=4, TIMERAH=5, TIMERBL=6, TIMERBH=7, //Write:Set Timer-latch, Read: read Timer
TOD_TENTHSECONDS=8, TOD_SECONDS=9, TOD_MINUTES=0xA, TOD_HOURS=0xB,
SERIAL_DATA=0xC, INTERRUPTS=0xD, CONTROLA=0xE, CONTROLB=0xF };

enum InterruptBitVal { INTERRUPT_HAPPENED=0x80, SET_OR_CLEAR_FLAGS=0x80, //(Read or Write operation determines which one:)
FLAGn=0x10, SERIALPORT=0x08, ALARM=0x04, TIMERB=0x02, TIMERA=0x01 }; //flags/masks of interrupt-sources

enum ControlAbitVal { ENABLE_TIMERA=0x01, PORTB6_TIMERA=0x02, TOGGLED_PORTB6=0x04, ONESHOT_TIMERA=0x08,
FORCELOADA_STROBE=0x10, TIMERA_FROM_CNT=0x20, SERIALPORT_IS_OUTPUT=0x40, TIMEOFDAY_50Hz=0x80 };

enum ControlBbitVal { ENABLE_TIMERB=0x01, PORTB7_TIMERB=0x02, TOGGLED_PORTB7=0x04, ONESHOT_TIMERB=0x08,
FORCELOADB_STROBE=0x10, TIMERB_FROM_CPUCLK=0x00, TIMERB_FROM_CNT=0x20, TIMERB_FROM_TIMERA=0x40,
TIMERB_FROM_TIMERA_AND_CNT = 0x60, TIMEOFDAY_WRITE_SETS_ALARM = 0x80 };

//TimerA
if (CIA->BasePtrWR[CONTROLA] & FORCELOADA_STROBE) { //force latch into counter (strobe-input)
CIA->BasePtrRD[TIMERAH] = CIA->BasePtrWR[TIMERAH]; CIA->BasePtrRD[TIMERAL] = CIA->BasePtrWR[TIMERAL];
}
else if ( (CIA->BasePtrWR[CONTROLA] & (ENABLE_TIMERA|TIMERA_FROM_CNT)) == ENABLE_TIMERA ) { //Enabled, counts Phi2
Tmp = ( (CIA->BasePtrRD[TIMERAH]<<8) + CIA->BasePtrRD[TIMERAL] ) - cycles; //count timer
if (Tmp <= 0) { //Timer counted down
Tmp += (CIA->BasePtrWR[TIMERAH]<<8) + CIA->BasePtrWR[TIMERAL]; //reload timer
if (CIA->BasePtrWR[CONTROLA] & ONESHOT_TIMERA) CIA->BasePtrWR[CONTROLA] &= ~ENABLE_TIMERA; //disable if one-shot
CIA->BasePtrRD[INTERRUPTS] |= TIMERA;
if (CIA->BasePtrWR[INTERRUPTS] & TIMERA) { //generate interrupt if mask allows
CIA->BasePtrRD[INTERRUPTS] |= INTERRUPT_HAPPENED;
}
}
CIA->BasePtrRD[TIMERAH] = (Tmp >> 8); CIA->BasePtrRD[TIMERAL] = Tmp & 0xFF;
}
CIA->BasePtrWR[CONTROLA] &= ~FORCELOADA_STROBE; //strobe is edge-sensitive
CIA->BasePtrRD[CONTROLA] = CIA->BasePtrWR[CONTROLA]; //control-registers are readable

//TimerB
if (CIA->BasePtrWR[CONTROLB] & FORCELOADB_STROBE) { //force latch into counter (strobe-input)
CIA->BasePtrRD[TIMERBH] = CIA->BasePtrWR[TIMERBH]; CIA->BasePtrRD[TIMERBL] = CIA->BasePtrWR[TIMERBL];
} //what about clocking TimerB by TimerA? (maybe not used in any music)
else if ( (CIA->BasePtrWR[CONTROLB] & (ENABLE_TIMERB|TIMERB_FROM_TIMERA)) == ENABLE_TIMERB ) { //Enabled, counts Phi2
Tmp = ( (CIA->BasePtrRD[TIMERBH]<<8) + CIA->BasePtrRD[TIMERBL] ) - cycles;//count timer
if (Tmp <= 0) { //Timer counted down
Tmp += (CIA->BasePtrWR[TIMERBH]<<8) + CIA->BasePtrWR[TIMERBL]; //reload timer
if (CIA->BasePtrWR[CONTROLB] & ONESHOT_TIMERB) CIA->BasePtrWR[CONTROLB] &= ~ENABLE_TIMERB; //disable if one-shot
CIA->BasePtrRD[INTERRUPTS] |= TIMERB;
if (CIA->BasePtrWR[INTERRUPTS] & TIMERB) { //generate interrupt if mask allows
CIA->BasePtrRD[INTERRUPTS] |= INTERRUPT_HAPPENED;
}
}
CIA->BasePtrRD[TIMERBH] = (Tmp >> 8); CIA->BasePtrRD[TIMERBL] = Tmp & 0xFF;
}
CIA->BasePtrWR[CONTROLB] &= ~FORCELOADB_STROBE; //strobe is edge-sensitive
CIA->BasePtrRD[CONTROLB] = CIA->BasePtrWR[CONTROLB]; //control-registers are readable

return (CIA->BasePtrRD[INTERRUPTS] & INTERRUPT_HAPPENED);
static inline char cRSID_emulateCIA(cRSID_CIAinstance *CIA, char cycles)
{
static int Tmp;

enum CIAregisters
{
PORTA = 0,
PORTB = 1,
DDRA = 2,
DDRB = 3,
TIMERAL = 4,
TIMERAH = 5,
TIMERBL = 6,
TIMERBH = 7, // Write:Set Timer-latch, Read: read Timer
TOD_TENTHSECONDS = 8,
TOD_SECONDS = 9,
TOD_MINUTES = 0xA,
TOD_HOURS = 0xB,
SERIAL_DATA = 0xC,
INTERRUPTS = 0xD,
CONTROLA = 0xE,
CONTROLB = 0xF
};

enum InterruptBitVal
{
INTERRUPT_HAPPENED = 0x80,
SET_OR_CLEAR_FLAGS = 0x80, //(Read or Write operation determines which one:)
FLAGn = 0x10,
SERIALPORT = 0x08,
ALARM = 0x04,
TIMERB = 0x02,
TIMERA = 0x01
}; // flags/masks of interrupt-sources

enum ControlAbitVal
{
ENABLE_TIMERA = 0x01,
PORTB6_TIMERA = 0x02,
TOGGLED_PORTB6 = 0x04,
ONESHOT_TIMERA = 0x08,
FORCELOADA_STROBE = 0x10,
TIMERA_FROM_CNT = 0x20,
SERIALPORT_IS_OUTPUT = 0x40,
TIMEOFDAY_50Hz = 0x80
};

enum ControlBbitVal
{
ENABLE_TIMERB = 0x01,
PORTB7_TIMERB = 0x02,
TOGGLED_PORTB7 = 0x04,
ONESHOT_TIMERB = 0x08,
FORCELOADB_STROBE = 0x10,
TIMERB_FROM_CPUCLK = 0x00,
TIMERB_FROM_CNT = 0x20,
TIMERB_FROM_TIMERA = 0x40,
TIMERB_FROM_TIMERA_AND_CNT = 0x60,
TIMEOFDAY_WRITE_SETS_ALARM = 0x80
};

// TimerA
if (CIA->BasePtrWR[CONTROLA] & FORCELOADA_STROBE)
{ // force latch into counter (strobe-input)
CIA->BasePtrRD[TIMERAH] = CIA->BasePtrWR[TIMERAH];
CIA->BasePtrRD[TIMERAL] = CIA->BasePtrWR[TIMERAL];
}
else if ((CIA->BasePtrWR[CONTROLA] & (ENABLE_TIMERA | TIMERA_FROM_CNT)) == ENABLE_TIMERA)
{ // Enabled, counts Phi2
Tmp = ((CIA->BasePtrRD[TIMERAH] << 8) + CIA->BasePtrRD[TIMERAL]) - cycles; // count timer
if (Tmp <= 0)
{ // Timer counted down
Tmp += (CIA->BasePtrWR[TIMERAH] << 8) + CIA->BasePtrWR[TIMERAL]; // reload timer
if (CIA->BasePtrWR[CONTROLA] & ONESHOT_TIMERA)
CIA->BasePtrWR[CONTROLA] &= ~ENABLE_TIMERA; // disable if one-shot
CIA->BasePtrRD[INTERRUPTS] |= TIMERA;
if (CIA->BasePtrWR[INTERRUPTS] & TIMERA)
{ // generate interrupt if mask allows
CIA->BasePtrRD[INTERRUPTS] |= INTERRUPT_HAPPENED;
}
}
CIA->BasePtrRD[TIMERAH] = (Tmp >> 8);
CIA->BasePtrRD[TIMERAL] = Tmp & 0xFF;
}
CIA->BasePtrWR[CONTROLA] &= ~FORCELOADA_STROBE; // strobe is edge-sensitive
CIA->BasePtrRD[CONTROLA] = CIA->BasePtrWR[CONTROLA]; // control-registers are readable

// TimerB
if (CIA->BasePtrWR[CONTROLB] & FORCELOADB_STROBE)
{ // force latch into counter (strobe-input)
CIA->BasePtrRD[TIMERBH] = CIA->BasePtrWR[TIMERBH];
CIA->BasePtrRD[TIMERBL] = CIA->BasePtrWR[TIMERBL];
} // what about clocking TimerB by TimerA? (maybe not used in any music)
else if ((CIA->BasePtrWR[CONTROLB] & (ENABLE_TIMERB | TIMERB_FROM_TIMERA)) == ENABLE_TIMERB)
{ // Enabled, counts Phi2
Tmp = ((CIA->BasePtrRD[TIMERBH] << 8) + CIA->BasePtrRD[TIMERBL]) - cycles; // count timer
if (Tmp <= 0)
{ // Timer counted down
Tmp += (CIA->BasePtrWR[TIMERBH] << 8) + CIA->BasePtrWR[TIMERBL]; // reload timer
if (CIA->BasePtrWR[CONTROLB] & ONESHOT_TIMERB)
CIA->BasePtrWR[CONTROLB] &= ~ENABLE_TIMERB; // disable if one-shot
CIA->BasePtrRD[INTERRUPTS] |= TIMERB;
if (CIA->BasePtrWR[INTERRUPTS] & TIMERB)
{ // generate interrupt if mask allows
CIA->BasePtrRD[INTERRUPTS] |= INTERRUPT_HAPPENED;
}
}
CIA->BasePtrRD[TIMERBH] = (Tmp >> 8);
CIA->BasePtrRD[TIMERBL] = Tmp & 0xFF;
}
CIA->BasePtrWR[CONTROLB] &= ~FORCELOADB_STROBE; // strobe is edge-sensitive
CIA->BasePtrRD[CONTROLB] = CIA->BasePtrWR[CONTROLB]; // control-registers are readable

return (CIA->BasePtrRD[INTERRUPTS] & INTERRUPT_HAPPENED);
}


static inline void cRSID_writeCIAIRQmask (cRSID_CIAinstance* CIA, unsigned char value) {
if (value&0x80) CIA->BasePtrWR[0xD] |= (value&0x1F);
else CIA->BasePtrWR[0xD] &= ~(value&0x1F);
static inline void cRSID_writeCIAIRQmask(cRSID_CIAinstance *CIA, unsigned char value)
{
if (value & 0x80)
CIA->BasePtrWR[0xD] |= (value & 0x1F);
else
CIA->BasePtrWR[0xD] &= ~(value & 0x1F);
}


static inline void cRSID_acknowledgeCIAIRQ (cRSID_CIAinstance* CIA) {
CIA->BasePtrRD[0xD] = 0x00; //reading a CIA interrupt-register clears its read-part and IRQ-flag
static inline void cRSID_acknowledgeCIAIRQ(cRSID_CIAinstance *CIA)
{
CIA->BasePtrRD[0xD] = 0x00; // reading a CIA interrupt-register clears its read-part and IRQ-flag
}


//static inline void cRSID_writeCIARWreg () {
//mirroring write-latch to read-latch for Readable-Writeable registers?
// static inline void cRSID_writeCIARWreg () {
// mirroring write-latch to read-latch for Readable-Writeable registers?
//}
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