Initial import.

.gitignore

@@ -0,0 +1,2 @@
+*.swp
+*.bak

README.rst

@@ -0,0 +1,47 @@
+============================
+ Altera Quartus II Makefile
+============================
+
+This can be used to compile your altera projects on the commandline,
+i.e. without the GUI.
+
+Directory Layout
+~~~~~~~~~~~~~~~~~
+
+As Quartus II will throw a lot of garbage into its project dir,
+a directory layout as follows was picked::
+  
+  fpga/
+  nios/
+  quartus/
+
+Your HDL code (and also the stuff that you might generate by using QSys)
+goes into *fpga/*.
+The quartus directory will contain all the stuff that gets generated by quartus.
+
+Usage
+~~~~~~
+
+In order to use this to build your project, drop all your HDL code into fpga.
+Edit *quartus/Makefile* to suit your needs, most interesting variables there
+should be:
+
+* SRCS (your HDL code)
+* PROJECT (your projects name?)
+* TOP_LEVEL_ENTITY (your projects top level entity)
+* FAMILY, PART and BOARDFILE (for pin assignments, and part selection)
+
+Now you can create and build your project by::
+
+  user$: make -C quartus
+ 
+In order to program the FPGA device use::
+
+  user$: make program
+
+Known problems
+~~~~~~~~~~~~~~~
+
+* If you generated some components using QSys check the paths in the
+  corresponding _hw.tcl file and make sure the _hw.tcl file is 
+  *inside* (for now ...) the *quartus/* directory.

fpga/top_level.v

@@ -0,0 +1,5 @@
+module top_level (input CLOCK_50);
+
+// This is a template
+
+endmodule