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feat: rework entry point and add some input format data models
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- Switch to typer for cli
- Use pydantic for data models
- Add data model for build specification (ex. csrconfig)
- Update pre-commit hook with more checks
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esynr3z committed Oct 22, 2024
1 parent c1e707c commit 477c946
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Showing 13 changed files with 656 additions and 332 deletions.
126 changes: 82 additions & 44 deletions .pre-commit-config.yaml
Original file line number Diff line number Diff line change
@@ -1,46 +1,84 @@
fail_fast: true
repos:
- repo: local
hooks:
- id: ruff_format
name: Python format check
entry: poetry run ruff format --check --diff
language: system
types: [file, python]
stages: [pre-commit]
- id: ruff_lint
name: Python lint check
entry: poetry run ruff check
language: system
types: [file, python]
stages: [pre-commit]
- id: pyright
name: Python type check
entry: poetry run pyright
language: system
types: [file, python]
stages: [pre-commit]
- id: check-yaml
name: YAML check
entry: poetry run check-yaml
language: python
types: [yaml]
stages: [pre-commit]
- id: check-toml
name: TOML check
entry: poetry run check-toml
language: python
types: [toml]
stages: [pre-commit]
- id: check-json
name: JSON check
entry: poetry run check-json
language: python
types: [json]
stages: [pre-commit]
- id: commitizen
name: Commit style check
stages: [commit-msg]
entry: cz check --commit-msg-file .git/COMMIT_EDITMSG
pass_filenames: false
language: system
- repo: local
hooks:
- id: ruff-format
name: Python format
description: Run Python code formatting with ruff
entry: poetry run ruff format
language: system
types: [file, python]
stages: [pre-commit]

- id: ruff-lint
name: Python lint check
description: Run Python code linting with ruff
entry: poetry run ruff check --fix
language: system
types: [file, python]
stages: [pre-commit]

- id: pyright
name: Python type check
description: Run Python code type checking with pyright
entry: poetry run pyright
language: system
types: [file, python]
stages: [pre-commit]

- id: check-yaml
name: YAML check
description: Validate all changed YAML files
entry: poetry run check-yaml
language: python
types: [yaml]
stages: [pre-commit]

- id: check-toml
name: TOML check
description: Validate all changed TOML files
entry: poetry run check-toml
language: python
types: [toml]
stages: [pre-commit]

- id: check-json
name: JSON check
description: Validate all changed JSON files
entry: poetry run check-json
language: python
types: [json]
stages: [pre-commit]

- id: commitizen
name: Commit style check
description: Run commitizen to validate commit message
stages: [commit-msg]
entry: cz check --commit-msg-file .git/COMMIT_EDITMSG
pass_filenames: false
language: system

- id: poetry-check
name: Poetry configuration check
description: Run poetry check to validate config
entry: poetry check
language: python
pass_filenames: false
files: ^(.*/)?(poetry\.lock|pyproject\.toml)$

- id: poetry-lock
name: Poetry lock update
description: Run poetry lock to update lock file
entry: poetry lock
language: python
pass_filenames: false
files: ^(.*/)?(poetry\.lock|pyproject\.toml)$

- id: poetry-install
name: poetry-install
description: Run poetry install to install dependencies from the lock file
entry: poetry install
language: python
pass_filenames: false
stages: [post-checkout, post-merge]
always_run: true
47 changes: 34 additions & 13 deletions corsair/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -10,19 +10,40 @@
__title__ = "corsair"
__description__ = "Control and status register (CSR) map generator for HDL projects."

from . import config, generators
from .bitfield import BitField
from .enum import EnumValue
from .reg import Register
from .regmap import RegisterMap

from .input import (
AnyTarget,
BaseTarget,
BuildSpecification,
CustomTarget,
ForceNameCase,
GlobalConfig,
MapCHeaderTarget,
MapMarkdownTarget,
MapSvPackageTarget,
MapVerilogHeaderTarget,
MapVerilogTarget,
MapVhdlTarget,
RegisterReset,
)
from .version import __version__

__all__ = [
__all__ = (
"__version__",
"RegisterMap",
"Register",
"EnumValue",
"BitField",
"config",
"generators",
]
# specification
"BuildSpecification",
# targets
"AnyTarget",
"BaseTarget",
"CustomTarget",
"MapVerilogTarget",
"MapVhdlTarget",
"MapSvPackageTarget",
"MapVerilogHeaderTarget",
"MapMarkdownTarget",
"MapCHeaderTarget",
# configuration
"ForceNameCase",
"RegisterReset",
"GlobalConfig",
)
4 changes: 2 additions & 2 deletions corsair/__main__.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@

from __future__ import annotations

from . import app
from . import cli

if __name__ == "__main__":
app.main()
cli.app()
66 changes: 0 additions & 66 deletions corsair/app.py

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