Eric Walker & Derek Reitz
[email protected] [email protected]
CSF Homework #3

Problem 1

1. See PDF for diagram.

2. Microprograms:

Fetch cycle:
t0 MAR <-- PC  , x4  = 1, x10 = 00
t1 MBR <-- M   , x2  = 1, x5  = 0 , x7 = 0
   PC  <-- PC+1, x13 = 1
t2 IR  <-- MBR , x1  = 1

LDA:
q1t3 MAR <-- IR(0), x4  = 1, x10 = 01 
q1t4 MBR <-- M    , x2  = 1, x5  = 0 , x7 = 0 
q1t5  AC <-- MBR  , x11 = 0, x12 = 1
q1t6 reset time   , x6  = 1

LDI:
q2t3 MAR <-- IR(0), x4  = 1, x10 = 01
q2t4 MBR <-- M    , x2  = 1, x5  = 0 , x7 = 0
q2t5 MAR <-- MBR  , x4  = 1, x10 = 10
q2t6 MBR <-- M    , x2  = 1, x5  = 0 , x7 = 0
q2t7 AC  <-- MBR  , x11 = 0, x12 = 1
q2t8 reset time   , x6  = 1

STA:
q3t3 MAR <-- IR(0), x4 = 1, x10 = 01
q3t4 MBR <-- AC   , x2 = 1, x7  = 1
q3t5 M   <-- MBR  , x5 = 1
q3t6 reset time   , x6 = 1

STI:
q4t3 MAR <-- IR(0), x4 = 1, x10 = 01
q4t4 MBR <-- M    , x2 = 1, x5  = 0, x7 = 0
q4t5 MAR <-- MBR  , x4 = 1, x10 = 10
q4t6 MBR <-- AC   , x2 = 1, x7  = 1
q4t7 M   <-- MBR  , x5 = 1
q4t8 reset time   , x6 = 1

ADD:
q5t3 MAR <-- IR(0)   , x4  = 1 , x10 = 01
q5t4 MBR <-- M       , x2  = 1 , x5  = 0 , x7  = 0
q5t5 ALU <-- AC + MBR, x8  = 00, x14 = 0
q5t6 RS  <-- ALU     , x9  = 1
q5t7 AC  <-- RS      , x11 = 1, x12 = 1
q5t8 reset time      , x6  = 1

SUB:
q5t3 MAR <-- IR(0)   , x4  = 1 , x10 = 01
q5t4 MBR <-- M       , x2  = 1 , x5  = 0 , x7  = 0
q5t5 ALU <-- AC + MBR, x8  = 00, x14 = 1
q5t6 RS  <-- ALU     , x9  = 1
q5t7 AC  <-- RS      , x11 = 1, x12 = 1
q5t8 reset time      , x6  = 1

JMP:
q7t3 PC <-- IR(0), x3 = 1
q7t4 reset time  , x6 = 1

JMZ:
q8t3 PC <-- IR(0), x3 = NOR(AC)
q8t4 reset time  , x6 = 1

3. Narrative:
Corrected Bugs:
Removed PC and IR(O) inputs into the MUX that selects the input for the
accumalator. These are unnecessary because they were used in the faulty JMP
and have no other purpose. 
Removed the MUX input into the ALU. This is because the ALU needs two 4-bit
inputs: 4 bits for each sequence that is operated upon.
Also we specified that the MUX for the MAR takes the lower 4 bits when
inputting from the MBR.

Added Circuitry:
To account for the SUB operation, we knew we could not alter the accumalator.
Therefore, we needed to invert and add 1 to the data we were subtracting.
To add 1, we include a new x-signal, called x14, which is turned on to 1 for
a subtraction operation, but is 0 for the normal add operation. This is the
carry-in. To invert, we needed to use the carry-in option as a way to invert.
Our requirements were that with a 0 the input remains the same, and with a 1
the input is inverted. This is the truth table for a XOR. The solution is to
run each bit of the second input through a XOR with the first carry-in. This
becomes a part of our ALU.  This is the simplest solution because it only
requires one extra x-signal and the rest can be included in the 
circuitry of the CLU. The x8 signal now decides which operator from the ALU
to output (add, and, or, not). The RS register is loaded via the x9 signal
and is there to ensure that the ALU does not loop through multiple additions
on a single edge.

To account for the JPZ operation, we needed a way to check if the data in the
accumlator contains all zeros. This can be accomplished by running the bits
through four parallel NOR gates. If the bits are 0, a 1 is output from the 
gate. If the bits are anything else (0,1), (1,0), (1,1), a 0 is output from
the gate. The outputs of these are then put through two AND gates, and the
output of these are then put through a final AND gate, which is sent as the
x3 signal, which determines whether the PC loads input from the IR(O) or not.
This is the simplest solution because it makes use of a pre-existing x-signal,
and requires only one gate per bit to determine if it is equal to zero. The x8
signal was changed to be input to the ALU as a selector for the  operator to
be applied.

Problem 2