ARCv3: Workaround for llock/scond livelock with exponential backoff #173
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Add an option ARC_LLSC_BACKOFF which enables delayed retries for failed SCOND instructions. This implementation reads the core ID and applies different delays before retrying LLSC for each core. Signed-off-by: Pavel Kozlov <[email protected]>
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xxkent
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Aug 9, 2024
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I've reviewed it and think we can merge this. |
Add a delay before the next read in the spinlock cycle to prevent the data cache line from getting dirty and to give other cores time to complete the conditional store instruction (scond). This is a workaround for livelock issues when the spinlock and another atomic operation are on the same cache line. Signed-off-by: Pavel Kozlov <[email protected]>
Add missed memory clobber to avoid unwanted gcc optimizations. This change is based on upstream commit 42f51fb (ARC: atomics: Add compiler barrier to atomic operations...) Signed-off-by: Pavel Kozlov <[email protected]>
Restore the dependency of HAS_ATLD on HAS_LLSC. This commit reverts the Kconfig changes introduced by commit bc57bd4 ("ARCv3: add new version of 32-bit arch_atomic_* with atld.<op> instrs"). The implementation of 32-bit atomic functions with atld.<op> instructions cannot fully replace the LLSC version and cannot be used as a workaround for the llock/scond livelock issue. Use the ARC_LLSC_BACKOFF option as a workaround for the llock/scond livelock issue. The HAS_ATLD option can only be used for efficient fetch-and-operate atomic functions implementation. Signed-off-by: Pavel Kozlov <[email protected]>
Update HS5x defconfigs to disable ATLD instructions by default for UP systems, and disable ATLD while enabling LLSC for SMP systems. This commit reverts part of the changes introduced by commit da7891b ("ARCv3: HS5x: update defconfigs for HS5x and enable ATLD"). Signed-off-by: Pavel Kozlov <[email protected]>
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Thank you for your review. Merged. |
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Add option ARC_LLSC_BACKOFF which enables delayed retry for failed SCOND instruction, read core id and provide different delays before LLSC retry for each core.
Also add extra delay in spinlock wait loop before next read to prevent the data cache line from getting dirty and to give the other core time to complete the conditional store instruction (scond).