Added ROMDualPort's Verilog export template

src/main/java/de/neemann/digital/hdl/hgs/Context.java

@@ -171,6 +171,8 @@ public void setVar(String name, Object val) throws HGSEvalException {
         if (v != null) {
             if (v.getClass().isAssignableFrom(val.getClass()))
                 map.put(name, val);
+            else if (v instanceof Integer && val instanceof Long)
+                map.put(name, Math.toIntExact((Long) val));
             else
                 throw new HGSEvalException("Variable '" + name + "' has wrong type. Needs to be "
                         + v.getClass().getSimpleName() + ", is " + val.getClass().getSimpleName());

src/main/resources/verilog/DIG_ROM.v

@@ -8,6 +8,9 @@
         data=loadHex(elem.lastDataFile, elem.Bits);
     }
     romSize := sizeOf(data);
+    if (romSize = 0) {
+        romSize = 1;
+    }
     moduleName = format("%s_%dX%d_%s", moduleName, romMaxSize, elem.Bits, identifier(elem.Label));
     dBitRange := format("[%d:0]", elem.Bits - 1);
     aBitRange := format("[%d:0]", elem.AddrBits - 1);
@@ -32,9 +35,13 @@
     end
 
     initial begin<?
-
-    for (i := 0; i < romSize; i++) { ?>
+    if( sizeOf(data) = 0) { ?>
+        my_rom[0]=0;<?
+    }
+    else {
+        for (i := 0; i < romSize; i++) { ?>
         my_rom[<?= i ?>] = <?= format("%d'h%x", elem.Bits, data[i]) ?>;<?
+        }
     } ?>
     end
 endmodule

src/main/resources/verilog/DIG_ROMDualPort.v

@@ -0,0 +1,62 @@
+<?
+    if (elem.Label="")
+        panic("err_romNeedsALabelToBeExported");
+
+    romMaxSize := 1 << elem.AddrBits;
+    data:=elem.Data;
+    if (elem.autoReload) {
+        data=loadHex(elem.lastDataFile, elem.Bits);
+    }
+    romSize := sizeOf(data);
+    if (romSize = 0) {
+        romSize = 1;
+    }
+    moduleName = format("%s_%dX%d_%s", moduleName, romMaxSize, elem.Bits, identifier(elem.Label));
+    dBitRange := format("[%d:0]", elem.Bits - 1);
+    aBitRange := format("[%d:0]", elem.AddrBits - 1);
+
+?>module <?= moduleName ?> (
+    input <?= aBitRange ?> A1,
+    input <?= aBitRange ?> A2,
+    input s1,
+    input s2,
+    output reg <?= dBitRange ?> D1,
+    output reg <?= dBitRange ?> D2
+);
+    reg <?= dBitRange ?> my_rom [0:<?= (romSize - 1) ?>];
+
+    always @ (*) begin
+        if (~s1)
+            D1 = <?= elem.Bits ?>'hz;<?
+        if (romSize < romMaxSize) {
+            lastAddr := format("%d'h%x", elem.AddrBits, romSize - 1); ?>
+        else if (A1 > <?= lastAddr ?>)
+            D1 = <?= elem.Bits ?>'h0;<?
+        } ?>
+        else
+            D1 = my_rom[A1];
+    end
+
+    always @ (*) begin
+        if (~s2)
+            D2 = <?= elem.Bits ?>'hz;<?
+        if (romSize < romMaxSize) {
+            lastAddr := format("%d'h%x", elem.AddrBits, romSize - 1); ?>
+        else if (A2 > <?= lastAddr ?>)
+            D2 = <?= elem.Bits ?>'h0;<?
+        } ?>
+        else
+            D2 = my_rom[A2];
+    end
+
+    initial begin<?
+    if( sizeOf(data) = 0) { ?>
+        my_rom[0]=0;<?
+    }
+    else {
+        for (i := 0; i < romSize; i++) { ?>
+        my_rom[<?= i ?>] = <?= format("%d'h%x", elem.Bits, data[i]) ?>;<?
+        }
+    } ?>
+    end
+endmodule