Merge pull request #1 from chryse-hdl/bb-wider

Support a wider range of elements in blackboxes.
kivikakk · May 18, 2024 · 8f80147 · 8f80147
2 parents 9c11343 + b972840
commit 8f80147
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Showing 3 changed files with 46 additions and 16 deletions.
diff --git a/.github/workflows/unit-tests.yml b/.github/workflows/unit-tests.yml
@@ -10,7 +10,7 @@ permissions:
   contents: read
 
 jobs:
-  build:
+  unit-tests:
     runs-on: ubuntu-latest
     steps:
     - uses: actions/checkout@v4

diff --git a/src/main/scala/ee/hrzn/chryse/platform/cxxrtl/BlackBoxGenerator.scala b/src/main/scala/ee/hrzn/chryse/platform/cxxrtl/BlackBoxGenerator.scala
@@ -24,25 +24,21 @@ class BlackBoxGenerator(private val wr: Writer) {
           ((name, dat)) <-
             io.elements.toSeq.reverseIterator
         } {
-          if (elIx > 0) wr.write("\n")
           val dir =
-            dat
-              .getClass()
-              .getMethod("specifiedDirection")
+            classOf[Data]
+              .getMethod("specifiedDirection") // chisel private :<
               .invoke(dat)
               .asInstanceOf[SpecifiedDirection]
-
-          if (dat.isInstanceOf[Vec[_]]) {
-            val vec = dat.asInstanceOf[Vec[_]]
-            for { i <- 0 until vec.length } {
-              emitWire(s"${name}_$i", dat, dir, elIx)
+          dat match {
+            case vec: Vec[_] =>
+              for { (vecEl, vecElIx) <- vec.getElements.zipWithIndex } {
+                emitWire(s"${name}_$vecElIx", vecEl, dir, vecEl.getWidth, elIx)
+                elIx += 1
+              }
+            case _ =>
+              emitWire(name, dat, dir, dat.getWidth, elIx)
               elIx += 1
-            }
-          } else {
-            emitWire(name, dat, dir, elIx)
-            elIx += 1
           }
-
         }
         throw UnwindException
       }
@@ -57,14 +53,21 @@ class BlackBoxGenerator(private val wr: Writer) {
       name: String,
       dat: Data,
       dir: SpecifiedDirection,
+      width: Int,
       elIx: Integer,
   ): Unit = {
+    if (elIx > 0) wr.write("\n")
     if (dir == SpecifiedDirection.Input && dat.isInstanceOf[Clock]) {
       wr.write("  attribute \\cxxrtl_edge \"p\"\n")
     } else if (dir == SpecifiedDirection.Output) {
+      // XXX: We're assuming this is a synchronous output, but who says it is?
       wr.write("  attribute \\cxxrtl_sync 1\n")
     }
-    wr.write(s"  wire ${dir.toString().toLowerCase()} ${elIx + 1} \\$name\n")
+    wr.write(s"  wire ${dir.toString().toLowerCase()} ${elIx + 1}")
+    if (width != 1) {
+      wr.write(s" width $width")
+    }
+    wr.write(s" \\$name\n")
   }
 }
 

diff --git a/src/test/scala/ee/hrzn/chryse/platform/cxxrtl/BlackBoxGeneratorSpec.scala b/src/test/scala/ee/hrzn/chryse/platform/cxxrtl/BlackBoxGeneratorSpec.scala
@@ -33,14 +33,34 @@ class BlackBoxGeneratorSpec extends AnyFlatSpec with Matchers {
                               |attribute \blackbox 1
                               |module \VecOfBoolBB
                               |  wire input 1 \d_in_0
+                              |
                               |  wire input 2 \d_in_1
+                              |
                               |  wire input 3 \d_in_2
                               |
                               |  attribute \cxxrtl_sync 1
                               |  wire output 4 \d_out_0
+                              |
                               |  attribute \cxxrtl_sync 1
                               |  wire output 5 \d_out_1
                               |end
+""".stripMargin)
+  }
+
+  it should "expand wider elements correctly" in {
+    val sw = new StringWriter
+    BlackBoxGenerator(sw, classOf[WiderElementsBB])
+    sw.toString() should be("""attribute \cxxrtl_blackbox 1
+                              |attribute \blackbox 1
+                              |module \WiderElementsBB
+                              |  wire input 1 width 64 \d_in
+                              |
+                              |  attribute \cxxrtl_sync 1
+                              |  wire output 2 width 8 \d_out_0
+                              |
+                              |  attribute \cxxrtl_sync 1
+                              |  wire output 3 width 8 \d_out_1
+                              |end
 """.stripMargin)
   }
 }
@@ -60,3 +80,10 @@ private class VecOfBoolBB extends BlackBox {
     val d_out = Output(Vec(2, Bool()))
   })
 }
+
+private class WiderElementsBB extends BlackBox {
+  val io = IO(new Bundle {
+    val d_in  = Input(UInt(64.W))
+    val d_out = Output(Vec(2, SInt(8.W)))
+  })
+}