Bump pythondata_cpu_picorv32/verilog subtree to 87c89ac

Updated using 0.0.post148 from https://github.com/litex-hub/litex-data-auto
litex-hub · Jan 10, 2025 · 84808b2 · 84808b2
2 parents 98ebd26 + 87c89ac
commit 84808b2
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diff --git a/pythondata_cpu_picorv32/verilog/.github/workflows/ci.yml b/pythondata_cpu_picorv32/verilog/.github/workflows/ci.yml
@@ -0,0 +1,37 @@
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+
+jobs:
+  riscv-formal:
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Checkout picorv32.v
+        uses: actions/checkout@v4
+        with:
+          sparse-checkout: |
+            picorv32.v
+          sparse-checkout-cone-mode: false
+      - name: Checkout riscv-formal
+        uses: actions/checkout@v4
+        with:
+          repository: YosysHQ/riscv-formal
+          path: riscv-formal
+      - name: cp picorv32.v
+        run: |
+          cp picorv32.v -t riscv-formal/cores/picorv32
+
+      - uses: YosysHQ/setup-oss-cad-suite@v3
+        with:
+          github-token: ${{ secrets.GITHUB_TOKEN }}
+
+      - name: make checks
+        run: |
+          cd riscv-formal/cores/picorv32
+          make checks -j$(nproc)
+      - name: make check
+        run: |
+          cd riscv-formal/cores/picorv32
+          make check
diff --git a/pythondata_cpu_picorv32/verilog/README.md b/pythondata_cpu_picorv32/verilog/README.md
@@ -1,3 +1,4 @@
+[![.github/workflows/ci.yml](https://github.com/YosysHQ/picorv32/actions/workflows/ci.yml/badge.svg)](https://github.com/YosysHQ/picorv32/actions/workflows/ci.yml)
 
 PicoRV32 - A Size-Optimized RISC-V CPU
 ======================================
@@ -237,7 +238,9 @@ triggering an interrupt.
 
 #### ENABLE_PCPI (default = 0)
 
-Set this to 1 to enable the Pico Co-Processor Interface (PCPI).
+Set this to 1 to enable the _external_ Pico Co-Processor Interface (PCPI).
+The external interface is not required for the internal PCPI cores, such as
+`picorv32_pcpi_mul`.
 
 #### ENABLE_MUL (default = 0)
 
@@ -284,7 +287,7 @@ Support for the timer is always disabled when ENABLE_IRQ is set to 0.
 #### ENABLE_TRACE (default = 0)
 
 Produce an execution trace using the `trace_valid` and `trace_data` output ports.
-For a demontration of this feature run `make test_vcd` to create a trace file
+For a demonstration of this feature run `make test_vcd` to create a trace file
 and then run `python3 showtrace.py testbench.trace firmware/firmware.elf` to decode
 it.
 
@@ -735,4 +738,3 @@ See `make area` in [scripts/vivado/](scripts/vivado/).
 | PicoRV32 (small)   |        761 |             48 |             442 |
 | PicoRV32 (regular) |        917 |             48 |             583 |
 | PicoRV32 (large)   |       2019 |             88 |            1085 |
-
diff --git a/pythondata_cpu_picorv32/verilog/firmware/start.S b/pythondata_cpu_picorv32/verilog/firmware/start.S
@@ -327,9 +327,7 @@ irq_vec:
 
 	picorv32_retirq_insn()
 
-#ifndef ENABLE_QREGS
 .balign 0x200
-#endif
 irq_regs:
 	// registers are saved to this memory region during interrupt handling
 	// the program counter is saved as register 0

diff --git a/pythondata_cpu_picorv32/verilog/picorv32.v b/pythondata_cpu_picorv32/verilog/picorv32.v
@@ -648,11 +648,12 @@ module picorv32 #(
 	reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
 	reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
 	reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
-	reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
+	reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak, instr_fence;
 	reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
 	wire instr_trap;
 
-	reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
+	reg [regindex_bits-1:0] decoded_rd, decoded_rs1;
+	reg [4:0] decoded_rs2;
 	reg [31:0] decoded_imm, decoded_imm_j;
 	reg decoder_trigger;
 	reg decoder_trigger_q;
@@ -680,7 +681,7 @@ module picorv32 #(
 			instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
 			instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
 			instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
-			instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
+			instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_fence,
 			instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
 
 	wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
@@ -746,6 +747,7 @@ module picorv32 #(
 		if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
 		if (instr_rdinstr)  new_ascii_instr = "rdinstr";
 		if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
+		if (instr_fence)    new_ascii_instr = "fence";
 
 		if (instr_getq)     new_ascii_instr = "getq";
 		if (instr_setq)     new_ascii_instr = "setq";
@@ -1083,6 +1085,7 @@ module picorv32 #(
 
 			instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
 					(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
+			instr_fence <= (mem_rdata_q[6:0] == 7'b0001111 && !mem_rdata_q[14:12]);
 
 			instr_getq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
 			instr_setq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
@@ -1158,6 +1161,8 @@ module picorv32 #(
 			instr_sra   <= 0;
 			instr_or    <= 0;
 			instr_and   <= 0;
+
+			instr_fence <= 0;
 		end
 	end
 

diff --git a/pythondata_cpu_picorv32/verilog/picosoc/Makefile b/pythondata_cpu_picorv32/verilog/picosoc/Makefile
@@ -113,7 +113,7 @@ clean:
 	rm -f testbench.vvp testbench.vcd spiflash_tb.vvp spiflash_tb.vcd
 	rm -f hx8kdemo_fw.elf hx8kdemo_fw.hex hx8kdemo_fw.bin cmos.log
 	rm -f icebreaker_fw.elf icebreaker_fw.hex icebreaker_fw.bin
-	rm -f hx8kdemo.blif hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
+	rm -f hx8kdemo.json hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
 	rm -f hx8kdemo_syn.v hx8kdemo_syn_tb.vvp hx8kdemo_tb.vvp
 	rm -f icebreaker.json icebreaker.log icebreaker.asc icebreaker.rpt icebreaker.bin
 	rm -f icebreaker_syn.v icebreaker_syn_tb.vvp icebreaker_tb.vvp

diff --git a/pythondata_cpu_picorv32/verilog/scripts/cxxdemo/Makefile b/pythondata_cpu_picorv32/verilog/scripts/cxxdemo/Makefile
@@ -3,7 +3,7 @@ CXX = $(RISCV_TOOLS_PREFIX)g++
 CC = $(RISCV_TOOLS_PREFIX)gcc
 AS = $(RISCV_TOOLS_PREFIX)gcc
 CXXFLAGS = -MD -Os -Wall -std=c++11
-CCFLAGS = -MD -Os -Wall -std=c++11
+CFLAGS = -MD -Os -Wall -std=c++11
 LDFLAGS = -Wl,--gc-sections
 LDLIBS = -lstdc++