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Using this module, we implement a feature to automatically reset the relevant devices (ISLA216p ADCs and FPGA MMCM) when there is a transition from the device clocks being "not_locked" to "locked". This situation can happen during board startup, when the ADCs receive no clock signal, and can only be properly reset after they start receiving it; and during operation, if the clock reference is lost, making it necessary to reset the ADC and MMCM in order to guarantee stable behavior from them.
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record(bo, "$(P)$(R)ADCRst-Cmd"){ | ||
field(DTYP, "asynInt32") | ||
field(DESC, "Reset ADCs") | ||
field(OUT, "@asyn($(PORT))RST_ADCS") | ||
field(MASK, "1") | ||
field(HIGH, "1") | ||
field(ZNAM, "nothing") | ||
field(ONAM, "reset") | ||
} | ||
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||
record(bo, "$(P)$(R)ADCDivRst-Cmd"){ | ||
field(DTYP, "asynInt32") | ||
field(DESC, "Reset ADC divisors") | ||
field(OUT, "@asyn($(PORT))RST_DIV_ADCS") | ||
field(MASK, "1") | ||
field(HIGH, "1") | ||
field(ZNAM, "nothing") | ||
field(ONAM, "reset") | ||
} | ||
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||
record(calcout, "$(P)$(R)ADCRstCalc") { | ||
field(INPA, "$(P)$(R)ClksLocked-Mon CP") | ||
field(CALC, "A") | ||
field(OOPT, "Transition To Non-zero") | ||
field(OUT, "$(P)$(R)ADCRstSeq PP") | ||
} | ||
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||
record(seq, "$(P)$(R)ADCRstSeq") { | ||
field(SELM, "All") | ||
field(LNK0, "$(P)$(R)ADCRst-Cmd PP") | ||
field(DOL0, "1") | ||
field(LNK1, "$(P)$(R)ADCDivRst-Cmd PP") | ||
field(DOL1, "1") | ||
field(DLY2, ".5") # guarantee time for ADCs to be reset | ||
field(LNK2, "$(P)$(R)MMCMRst-Cmd PP") | ||
field(DOL2, "1") | ||
} |