[hmac,dv] Disable S&R for stress_reset test

- The stress_reset test is currently failing when a reset is happening when the Save and Restore is in a particular state. This should be removed later when the reset will be handled properly in the env. Signed-off-by: Martin Velay <[email protected]>
lowRISC · Jan 16, 2025 · 4f55782 · 4f55782
1 parent 5f89d80
commit 4f55782
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_reset_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_reset_vseq.sv
@@ -9,6 +9,7 @@ class hmac_stress_reset_vseq extends hmac_base_vseq;
 
   // Standard SV/UVM methods
   extern function new(string name="");
+  extern task pre_body();
   extern task body();
 endclass : hmac_stress_reset_vseq
 
@@ -17,6 +18,12 @@ function hmac_stress_reset_vseq::new(string name="");
   super.new(name);
 endfunction : new
 
+task hmac_stress_reset_vseq::pre_body();
+  // TODO (#25809) - The S&R is causing troubles with this test, this flag will be removed later
+  // when reset is handled properly.
+  cfg.save_and_restore_pct = 0;
+  super.pre_body();
+endtask : pre_body
 
 task hmac_stress_reset_vseq::body();
   for (int i = 1; i <= num_trans; i++) begin