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[rom_ctrl,dv] Stress sequence tidyup #25864

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merged 6 commits into from
Jan 21, 2025

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rswarbrick
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There are several commits in this PR, with detailed individual commit messages. The original motivation was actually a hole in toggle coverage, but this has ended up tidying up a couple of other items

This sequence sends an error message from KMAC and checks that it does
indeed get reflected as an alert from rom_ctrl. This works fine, but
the sequence followed up with a dut_init call, which is a bit strange!

I suspect this was to avoid getting to cip_base_vseq::post_start with
an alert in progress. This was a problem because
rom_ctrl_kmac_err_chk_vseq didn't set the expect_fatal_alerts flag.

Do so, and drop the extra reset.

Signed-off-by: Rupert Swarbrick <[email protected]>
rom_ctrl is a little unusual and it doesn't really make sense to run a
vseq without a reset. Change things so that we don't do so.

Signed-off-by: Rupert Swarbrick <[email protected]>
This is a problem if the last child vseq causes a fatal alert, which
won't have been cleared by the end of the stress_all sequence.

Signed-off-by: Rupert Swarbrick <[email protected]>
We don't actually have an intr_test register, so this code (copied
from other blocks, it seems) didn't do anything. Drop it.

Signed-off-by: Rupert Swarbrick <[email protected]>
This is just changing the vseq slightly so that the body task exits
quickly if it sees a reset.

Signed-off-by: Rupert Swarbrick <[email protected]>
The motivation is a bit silly: it covers a toggle coverage point,
where we'd like to see the KMAC response signal go between 0 and 1.
Running this sequence in the middle of some smoke sequences covers it
appropriately.

Signed-off-by: Rupert Swarbrick <[email protected]>
@rswarbrick rswarbrick added Component:DV DV issue: testbench, test case, etc. IP:rom_ctrl labels Jan 14, 2025
@rswarbrick rswarbrick requested a review from a team as a code owner January 14, 2025 13:32
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@alees24 alees24 left a comment

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As discussed, I think it'd be safer to separate the final commit to avoid potentially having a negative impact on other blocks. The rest looks fine, thanks.

@rswarbrick rswarbrick force-pushed the rom-ctrl-stress-seq-tidyup branch from 60a38f2 to dcefc49 Compare January 21, 2025 13:55
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I've just pushed a version with all but the last commit and will merge that :-)

@rswarbrick rswarbrick merged commit 7240b02 into lowRISC:master Jan 21, 2025
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@rswarbrick rswarbrick deleted the rom-ctrl-stress-seq-tidyup branch January 21, 2025 13:56
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2 participants