mainboard/google: add initial rambi mainboard support

BUG=chrome-os-partner:23121
BRANCH=None
TEST=None

Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb
Signed-off-by: Aaron Durbin <[email protected]>
Reviewed-on: https://chromium-review.googlesource.com/171940
Reviewed-by: Bernie Thompson <[email protected]>
Reviewed-on: http://review.coreboot.org/4865
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <[email protected]>

src/mainboard/google/Kconfig

@@ -40,6 +40,8 @@ config BOARD_GOOGLE_PEPPY
 	bool "Peppy"
 config BOARD_GOOGLE_PIT
 	bool "Pit"
+config BOARD_GOOGLE_RAMBI
+	bool "Rambi"
 config BOARD_GOOGLE_SLIPPY
 	bool "Slippy"
 config BOARD_GOOGLE_SNOW
@@ -56,6 +58,7 @@ source "src/mainboard/google/link/Kconfig"
 source "src/mainboard/google/parrot/Kconfig"
 source "src/mainboard/google/peppy/Kconfig"
 source "src/mainboard/google/pit/Kconfig"
+source "src/mainboard/google/rambi/Kconfig"
 source "src/mainboard/google/slippy/Kconfig"
 source "src/mainboard/google/snow/Kconfig"
 source "src/mainboard/google/stout/Kconfig"

src/mainboard/google/rambi/Kconfig

@@ -0,0 +1,36 @@
+if BOARD_GOOGLE_RAMBI
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_X86
+	select SOC_INTEL_BAYTRAIL
+	select ENABLE_BUILTIN_COM1
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select MAINBOARD_HAS_CHROMEOS
+	select CHROMEOS
+	select MARK_GRAPHICS_MEM_WRCOMB
+
+config MAINBOARD_DIR
+	string
+	default google/rambi
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "RAMBI"
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0166.rom"
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config HAVE_ME_BIN
+	bool
+	default n
+
+endif # BOARD_INTEL_BAYLEYBAY

src/mainboard/google/rambi/Makefile.inc

@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += gpio.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c

src/mainboard/google/rambi/acpi/chromeos.asl

@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Name(OIPG, Package() {
+	Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery
+	Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer
+	Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect
+})

src/mainboard/google/rambi/acpi/ec.asl

@@ -0,0 +1,37 @@
+Device (EC0)
+{
+	Name (_HID, EISAID ("PNP0C09"))
+	Name (_UID, 1)
+	Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N
+
+	OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+	Field (ERAM, ByteAcc, Lock, Preserve)
+	{
+		Offset (0x03),
+		ACPR, 1,	// AC Power (1=present)
+		    , 2,
+		CFAN, 1,	// CPU Fan (1=on)
+		    , 2,
+		LIDS, 1,	// Lid State (1=open)
+		    , 1,
+		SPTR, 8,	// SMBUS Protocol Register
+		SSTS, 8,	// SMBUS Status Register
+		SADR, 8,	// SMBUS Address Register
+		SCMD, 8,	// SMBUS Command Register
+		SBFR, 256,	// SMBUS Block Buffer
+		SCNT, 8,	// SMBUS Block Count
+
+		Offset (0x3a),
+		ECMD, 8,	// EC Command Register
+
+		Offset (0x82),
+		PECL, 8,	// PECI fractional (1/64 Celsius)
+		PECH, 8,	// PECI integer (Celsius)
+	}
+
+	Name (_CRS, ResourceTemplate()
+	{
+		IO (Decode16, 0x62, 0x62, 0, 1)
+		IO (Decode16, 0x66, 0x66, 0, 1)
+	})
+}

src/mainboard/google/rambi/acpi/mainboard.asl

@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+
+	// Wake from deep sleep via GPIO27
+	Name(_PRW, Package(){27, 4})
+}

src/mainboard/google/rambi/acpi/platform.asl

@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+

src/mainboard/google/rambi/acpi/superio.asl

@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Values should match those defined in devicetree.cb */