Skip to content

RISC‐V ACPI ECR Process

Sunil V L edited this page Jun 18, 2024 · 2 revisions

1) ECR must be created first in DRAFT folder in google drive and sent for review from the RISCV community with a PoC. Create a github issue with "CodeFirst_ECR" label.

2) After the RISCV community review, the ECR should be sent for the UEFI ASWG review by a promoter/contributor member of UEFI.

3) After incorporating feedback and once ASWG finally approves the ECR, it should be moved to the ASWG_APPROVED folder in PDF format for future reference.

Below Table should be updated whenever a new ECR needs to be created and taken through the review process.

Name of the ECR Status Description Submitter github issue ID

ACPI_MADT_RINTC_ECR

ASWG_APPROVED

INTC Interrupt Controller info in MADT

Sunil V L

15

ACPI_RHCT_ECR

ASWG_APPROVED

Add RHCT Table

Sunil V L

16

ACPI_MADT_AIA_PLIC

ASWG_APPROVED

Add AIA/PLIC interrupt controller structures in MADT

Sunil V L/ Andrei Warkentin

17

ACPI_RHCT_CMO_MMU

ASWG_APPROVED

Add CMO and MMU nodes in RHCT

Sunil V L

18

ACPI_SRAT_RINTC_AFFINITY

ASWG_APPROVED

Add RINTC affinity structure in SRAT

Haibo Xu

25

Possible Status for ECR

  • DRAFT : ECR under RISCV Community review

  • ASWG_REVIEW : ECR approved by RISCV community and sent for the UEFI ASWG review.

  • ASWG_APPROVED : ECR approved by the ACPI ASWG, the final version

  • REJECTED : Rejected / cancelled

UEFI_ASWG_ECR_PROCESS
Clone this wiki locally