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[Experiment] new zkVM design #91
[Experiment] new zkVM design #91
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circuit witness: direct witness on mle devirgo style on phase1_output
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This is a worth direction of trying. First attempt PR to aggregate all degree=1 MLEs then times selector Based on benchmark result it cause 5% throughtput drop on 2^20 add instance benchmark. From the first glance, there are pros/cons for this change. Therefore I just raise a separate PR for future effort. |
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Finished review of verifier part. This PR looks good to me.
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feat/optimize_witness_cloning
* optimize sumcheck algo circuit witness: direct witness on mle devirgo style on phase1_output * temporarily exclude singer-pro from default workspace members * fux build error in mpcs * [Experiment] new zkVM design (#91) * optimize sumcheck algo circuit witness: direct witness on mle devirgo style on phase1_output * initial version for new zkVM design * riscv add prototype implementation * add new zkVM prover * new package ceno_zkvm * record witness generation * add transcript * add verifier * code cleanup * rename expression * prover record_r/record_w sumcheck * main sel sumcheck proof/verify * tower product witness inference * tower product sumcheck prove/verify * chores: fix tower sumcheck witness length error and clean up * verify record and zero expression * tower sumcheck prove/verify pass * WIP test main sel prove/verify * add benchmark * chores: interleaving with default value * main constraint sumcheck prove/verify pass * chores: mock witness * main constraint sumcheck verify final claim assertion pass * restructure ceno_zkvm package * refine expression format * wip lookup * lookup in logup implemetation with integration test pass * chores: code cosmetics * optimize with 2-stage sumcheck #103 * chores: refine virtual polys naming * fix proper ts and pc counting * try sumcheck bench * refine global state in riscv * degree > 1 main constraint sumcheck implementation #107 (#108) * monomial expression to virtual poly * degree > 1 sumcheck batched with main constraint * succint selector evaluation * refine succint selector evaluation formula and documentation * wip fix interleaving edge case * deal with interleaving_mles instance = 1 case * chores: code cosmetics and address review comments * fix logup padding with chip record challenge * riscv opcode type & combine add/sub opcode & dependency trim * ci whitelist ceno_zkvm lint/clippy * address review comments and naming cosmetics * remove unnessesary to_vec operation * tower verifier logup p(x) constant check * cleanup and hide thread-based logic * soundness fix: derive new sumcheck batched challenge for each round * fix sel evaluation point and add TODO check * fix sumcheck batched challenge deriving order * chore: rename pc step size & fine tune project structure * fix lint error
* optimize sumcheck algo circuit witness: direct witness on mle devirgo style on phase1_output * temporarily exclude singer-pro from default workspace members * fux build error in mpcs * [Experiment] new zkVM design (#91) * optimize sumcheck algo circuit witness: direct witness on mle devirgo style on phase1_output * initial version for new zkVM design * riscv add prototype implementation * add new zkVM prover * new package ceno_zkvm * record witness generation * add transcript * add verifier * code cleanup * rename expression * prover record_r/record_w sumcheck * main sel sumcheck proof/verify * tower product witness inference * tower product sumcheck prove/verify * chores: fix tower sumcheck witness length error and clean up * verify record and zero expression * tower sumcheck prove/verify pass * WIP test main sel prove/verify * add benchmark * chores: interleaving with default value * main constraint sumcheck prove/verify pass * chores: mock witness * main constraint sumcheck verify final claim assertion pass * restructure ceno_zkvm package * refine expression format * wip lookup * lookup in logup implemetation with integration test pass * chores: code cosmetics * optimize with 2-stage sumcheck #103 * chores: refine virtual polys naming * fix proper ts and pc counting * try sumcheck bench * refine global state in riscv * degree > 1 main constraint sumcheck implementation #107 (#108) * monomial expression to virtual poly * degree > 1 sumcheck batched with main constraint * succint selector evaluation * refine succint selector evaluation formula and documentation * wip fix interleaving edge case * deal with interleaving_mles instance = 1 case * chores: code cosmetics and address review comments * fix logup padding with chip record challenge * riscv opcode type & combine add/sub opcode & dependency trim * ci whitelist ceno_zkvm lint/clippy * address review comments and naming cosmetics * remove unnessesary to_vec operation * tower verifier logup p(x) constant check * cleanup and hide thread-based logic * soundness fix: derive new sumcheck batched challenge for each round * fix sel evaluation point and add TODO check * fix sumcheck batched challenge deriving order * chore: rename pc step size & fine tune project structure * fix lint error
Issue link:
#102
An attempt to implemenet new zkVM based on proposed design https://hackmd.io/@P4deJs5uRSyvHnXF8yyQJQ/B1DpOQDOA
Design Rationales
The concept of representing a computation DAG in main constraints is based on
Expression
, inspired significantly by the Halo2 expression design. While it may be less expressive than the GKR graph, it is sufficiently capable of covering the required syntax for implementing opcode constraints in zkVM.The new codebase is initially mixed with the existing singer and singer-util frameworks to maximize reuse. Later, we can transition the new logic into a standalone package.
Tasks breakdown
Footnotes
AMD EPYC 9R14 (16 phy cores) + 32GB memory ↩