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fix upgrade
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lightsing committed Jun 14, 2024
1 parent 003227d commit 8821135
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Showing 4 changed files with 31 additions and 16 deletions.
1 change: 0 additions & 1 deletion core/src/runtime/record.rs
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@ use crate::syscall::precompiles::uint256::Uint256MulEvent;
use crate::syscall::precompiles::ECDecompressEvent;
use crate::syscall::precompiles::{ECAddEvent, ECDoubleEvent};
use crate::syscall::MemCopyEvent;
use crate::utils::env;
use crate::utils::SP1CoreOpts;

/// A record of the execution of a program. Contains event data for everything that happened during
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4 changes: 2 additions & 2 deletions core/src/runtime/syscall.rs
Original file line number Diff line number Diff line change
Expand Up @@ -376,11 +376,11 @@ pub fn default_syscall_map() -> HashMap<SyscallCode, Arc<dyn Syscall>> {

syscall_map.insert(
SyscallCode::MEMCPY_32,
Rc::new(MemCopyChip::<U8, U32>::new()),
Arc::new(MemCopyChip::<U8, U32>::new()),
);
syscall_map.insert(
SyscallCode::MEMCPY_64,
Rc::new(MemCopyChip::<U16, U64>::new()),
Arc::new(MemCopyChip::<U16, U64>::new()),
);

syscall_map
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1 change: 1 addition & 0 deletions core/src/stark/air.rs
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ use crate::StarkGenericConfig;
use p3_field::PrimeField32;
pub use riscv_chips::*;
use tracing::instrument;
use typenum::{U16, U32, U64, U8};

/// A module for importing all the different RISC-V chips.
pub(crate) mod riscv_chips {
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41 changes: 28 additions & 13 deletions core/src/syscall/memcpy.rs
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ use p3_matrix::{dense::RowMajorMatrix, Matrix};
use serde::{Deserialize, Serialize};
use sp1_derive::AlignedBorrow;

use crate::bytes::event::ByteRecord;
use crate::operations::field::params::Limbs;
use crate::utils::{limbs_from_access, limbs_from_prev_access};
use crate::{
Expand All @@ -23,30 +24,32 @@ use crate::{
#[derive(Clone, Debug, Serialize, Deserialize)]
pub struct MemCopyEvent {
pub shard: u32,
pub channel: u32,
pub clk: u32,
pub src_ptr: u32,
pub dst_ptr: u32,
pub src_access: Vec<MemoryReadRecord>,
pub dst_access: Vec<MemoryWriteRecord>,
pub read_records: Vec<MemoryReadRecord>,
pub write_records: Vec<MemoryWriteRecord>,
}

#[derive(Debug, Clone, AlignedBorrow)]
#[repr(C)]
pub struct MemCopyCols<T, NumWords: ArrayLength + Sync> {
pub struct MemCopyCols<T, NumWords: ArrayLength> {
is_real: T,
shard: T,
channel: T,
clk: T,
src_ptr: T,
dst_ptr: T,
src_access: GenericArray<MemoryReadCols<T>, NumWords>,
dst_access: GenericArray<MemoryWriteCols<T>, NumWords>,
}

pub struct MemCopyChip<NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sync> {
pub struct MemCopyChip<NumWords: ArrayLength, NumBytes: ArrayLength> {
_marker: PhantomData<(NumWords, NumBytes)>,
}

impl<NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sync> MemCopyChip<NumWords, NumBytes> {
impl<NumWords: ArrayLength, NumBytes: ArrayLength> MemCopyChip<NumWords, NumBytes> {
const NUM_COLS: usize = core::mem::size_of::<MemCopyCols<u8, NumWords>>();

pub fn new() -> Self {
Expand All @@ -70,7 +73,7 @@ impl<NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sync> MemCopyChip<Num
}
}

impl<NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sync> Syscall
impl<NumWords: ArrayLength + Send + Sync, NumBytes: ArrayLength + Send + Sync> Syscall
for MemCopyChip<NumWords, NumBytes>
{
fn execute(&self, ctx: &mut crate::runtime::SyscallContext, src: u32, dst: u32) -> Option<u32> {
Expand All @@ -79,11 +82,12 @@ impl<NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sync> Syscall

let event = MemCopyEvent {
shard: ctx.current_shard(),
channel: ctx.current_channel(),
clk: ctx.clk,
src_ptr: src,
dst_ptr: dst,
src_access: read,
dst_access: write,
read_records: read,
write_records: write,
};
ctx.record_mut()
.memcpy_events
Expand All @@ -97,8 +101,6 @@ impl<NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sync> Syscall

impl<F: PrimeField32, NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sync> MachineAir<F>
for MemCopyChip<NumWords, NumBytes>
where
[(); Self::NUM_COLS]:,
{
type Record = ExecutionRecord;

Expand All @@ -113,20 +115,30 @@ where
let mut new_byte_lookup_events = vec![];

for event in input.memcpy_events.get(&NumWords::USIZE).unwrap_or(&vec![]) {
let mut row = [F::zero(); Self::NUM_COLS];
let mut row = Vec::with_capacity(Self::NUM_COLS);
row.resize(Self::NUM_COLS, F::zero());
let cols: &mut MemCopyCols<F, NumWords> = row.as_mut_slice().borrow_mut();

cols.is_real = F::one();
cols.shard = F::from_canonical_u32(event.shard);
cols.channel = F::from_canonical_u32(event.channel);
cols.clk = F::from_canonical_u32(event.clk);
cols.src_ptr = F::from_canonical_u32(event.src_ptr);
cols.dst_ptr = F::from_canonical_u32(event.dst_ptr);

for i in 0..NumWords::USIZE {
cols.src_access[i].populate(event.src_access[i], &mut new_byte_lookup_events);
cols.src_access[i].populate(
event.channel,
event.read_records[i],
&mut new_byte_lookup_events,
);
}
for i in 0..NumWords::USIZE {
cols.dst_access[i].populate(event.dst_access[i], &mut new_byte_lookup_events);
cols.dst_access[i].populate(
event.channel,
event.write_records[i],
&mut new_byte_lookup_events,
);
}

rows.push(row);
Expand Down Expand Up @@ -171,13 +183,15 @@ impl<AB: SP1AirBuilder, NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sy

builder.eval_memory_access_slice(
row.shard,
row.channel,
row.clk.into(),
row.src_ptr,
&row.src_access,
row.is_real,
);
builder.eval_memory_access_slice(
row.shard,
row.channel,
row.clk.into(),
row.dst_ptr,
&row.dst_access,
Expand All @@ -186,6 +200,7 @@ impl<AB: SP1AirBuilder, NumWords: ArrayLength + Sync, NumBytes: ArrayLength + Sy

builder.receive_syscall(
row.shard,
row.channel,
row.clk,
AB::F::from_canonical_u32(Self::syscall_id()),
row.src_ptr,
Expand Down

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