AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Jan 7, 2025 - SystemVerilog
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axi
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Code generation tool for control and status registers
asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents
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Dec 31, 2024 - Ruby
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface
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Jan 4, 2025 - Verilog
Network on Chip Implementation written in SytemVerilog
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Aug 27, 2022 - SystemVerilog
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
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Dec 20, 2024 - Python
OPAE porting to Xilinx FPGA devices.
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Aug 5, 2020 - Coq
Simple single-port AXI memory interface
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Jun 7, 2024 - SystemVerilog
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches
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Nov 20, 2024 - VHDL
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-interface fpga spi altera verilog-hdl xilinx-fpga xilinx-vivado verilog-components axi verilog-snippets spi-hdl spi-ip-core spi-pld spi-fpga verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi
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Nov 21, 2017 - Verilog
Implementation of the Advanced Encryption Standard in Chisel
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Apr 18, 2022 - Scala
XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
fpga vivado pcie axi ddr4 xdma innova2 xcku15p mnv303212a innova-2-flex mnv303212a-adlt 4xc7a16683 01pg974 pcie-xdma
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Mar 7, 2024 - Tcl
Hardware and Software Co-design implementations
sdk gpio fsm ddr zedboard dma bram axi zynq-7000 vivado-ip-integrator arm-cortex-a9 zynq7-ps high-performance-port
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Dec 5, 2019
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
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Mar 24, 2017 - VHDL
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