[AMD] Support fp16 upcast in scaled dot #5543
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AMD gfx9 architectures do not have native bf16 VALU instructions so doing bf16 scaling can be expensive. This commit prototypes upcasting to fp16 for computation. It would mean relaxing to support fp16 in dot_scaled frontend and upcast_mxfp op definitions. Right now the fp16 path is turned on if one input is fp16 for prototyping. A more proper way might be introducing a `math_dtype` to explicitly control.
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lezcano
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| RankedTensorType | ||
| UpcastMXFPOp::deduceOutputType(TypedValue<RankedTensorType> inputTensor, | ||
| ScaleDotElemType inputElemType, | ||
| Type outputElemType) { |
| Software emulation enables targeting hardware architectures without native microscaling | ||
| operation support. Right now for such case, microscaled lhs/rhs are upcasted to | ||
| :code:`bf16` element type beforehand for dot computation, with one exception: | ||
| for AMD CDNA3 specifically, if one of the inputs is of normal :code:`fp16` element type, |
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nit.
Suggested change
| for AMD CDNA3 specifically, if one of the inputs is of normal :code:`fp16` element type, | |
| for AMD CDNA3 specifically, if one of the inputs is of :code:`fp16` element type, |
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AMD gfx9 architectures do not have native bf16 VALU instructions so doing bf16 scaling can be expensive.
This commit prototypes upcasting to fp16 for computation. It would mean relaxing to support fp16 in dot_scaled frontend and upcast_mxfp op definitions.
Right now the fp16 path is turned on if one input is fp16 for prototyping. A more proper way might be introducing a
math_dtypeto explicitly control.