Could you please help me check my prototype for zcu102?

.github/ISSUE_TEMPLATE/config.yml

@@ -1,4 +1,4 @@
-blank_issues_enabled: false
+blank_issues_enabled: true
 contact_links:
   - name: Chipyard Mailing List
     url: https://groups.google.com/forum/#!forum/chipyard

.gitignore

@@ -30,3 +30,4 @@ project/project/
 .classpath_cache/
 .vscode/
 tests/build/
+fpga/generated-src/*

.gitmodules

@@ -1,6 +1,7 @@
 [submodule "fpga/fpga-shells"]
 	path = fpga/fpga-shells
-	url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
+	url = https://github.com/Jerryy959/rocket-chip-fpga-shells.git
+	branch = zcu102
 [submodule "generators/bar-fetchers"]
 	path = generators/bar-fetchers
 	url = https://github.com/ucb-bar/bar-fetchers.git

HowToUse.md

@@ -0,0 +1,31 @@
+How to use this branch?
+=======================
+
+This branch just for zcu102 fpga.
+
+Follow the steps below to use this branch:
+
+```bash
+# 1. Install the docker engine on your ubuntu host.
+# 2. Docker pull the docker image, which has all the necessary tools and dependencies installed.
+docker pull jerryy959/chipyard-zcu:v1.13.0
+# 3. Run the docker container with one shared directory for building the vivado project on your host.
+docker run -itd -v /workspace:/jerry jeffery959/chipyard-zcu:v1.13.0 /bin/bash
+# 4. Create the working directory.
+mkdir -p /workspace
+# 5. Attach to the running container.
+docker attach <container_id>
+# 6. Pull the newest code from the chipyard repo in the container.
+cd /workspace/chipyard && git checkout . && git remote set-url origin [email protected]:Jerryy959/chipyard.git && git pull origin zcu102
+# 7. Build the chipyard project in the container.
+cd /workspace/chipyard/fpga && source ../env.sh && make clean && make SUB_PROJECT=zcu102 verilog
+# 8. Copy the whole project to the shared directory which is </jerry>.
+cp -rf /workspace/chipyard /jerry
+# 9. Open a new terminal on your host and rebuild the project, just for test.
+cd /workapce/chipyard/fpga && source ../env.sh && make clean && make SUB_PROJECT=zcu102 vivado
+# 10. Source the vivado settings64.sh.
+source /tools/Xilinx/Vivado/2022.2/settings64.sh
+# 11. Rebuild the project to generate the bitstream.
+cd /workapce/chipyard/fpga && source ../env.sh && make clean && make SUB_PROJECT=zcu102 bitstream
+# 12. Then flash the bitstream to the zcu102 board.
+```

chipyard

@@ -0,0 +1 @@
+/media/parallels/SSD/workspace/chipyard

fpga/.Xil/Vivado-123488-ubuntu-linux-22-04-02-desktop/.lpr

@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0">
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>

fpga/.Xil/Vivado-1398501-ubuntu-linux-22-04-02-desktop/.lpr

@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0">
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>

fpga/.Xil/Vivado-78320-ubuntu-linux-22-04-02-desktop/.lpr

@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0">
+  <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>

fpga/Makefile

@@ -14,7 +14,7 @@ sim_name := none
 #########################################################################################
 # include shared variables
 #########################################################################################
-SUB_PROJECT ?= vcu118
+SUB_PROJECT ?= zcu102
 
 ifeq ($(SUB_PROJECT),vc707)
 	SBT_PROJECT       ?= chipyard_fpga
@@ -87,6 +87,34 @@ ifeq ($(SUB_PROJECT),arty100t)
 	FPGA_BRAND        ?= xilinx
 endif
 
+ifeq ($(SUB_PROJECT),zcu102)
+	SBT_PROJECT	      ?= chipyard_fpga
+	MODEL             ?= ZCU102FPGATestHarness
+	VLOG_MODEL        ?= ZCU102FPGATestHarness
+	MODEL_PACKAGE     ?= chipyard.fpga.zcu102
+	CONFIG            ?= RocketZCU102Config
+	CONFIG_PACKAGE    ?= chipyard.fpga.zcu102
+	GENERATOR_PACKAGE ?= chipyard
+	TB                ?= none # unused
+	TOP               ?= ChipTop
+	BOARD             ?= zcu102
+	FPGA_BRAND        ?= xilinx
+endif
+
+ifeq ($(SUB_PROJECT),zcu106)
+	SBT_PROJECT	      ?= chipyard_fpga
+	MODEL             ?= ZCU106FPGATestHarness
+	VLOG_MODEL        ?= ZCU106FPGATestHarness
+	MODEL_PACKAGE     ?= chipyard.fpga.zcu106
+	CONFIG            ?= RocketZCU106Config
+	CONFIG_PACKAGE    ?= chipyard.fpga.zcu106
+	GENERATOR_PACKAGE ?= chipyard
+	TB                ?= none # unused
+	TOP               ?= ChipTop
+	BOARD             ?= zcu106
+	FPGA_BRAND        ?= xilinx
+endif
+
 export USE_CHISEL6=1
 
 include $(base_dir)/variables.mk