Merge pull request #286 from chipsalliance/main

Reintegrate main -> dev-msft
chipsalliance · Nov 10, 2023 · b0a25ba · b0a25ba
2 parents 92876e1 + 020d315
commit b0a25ba
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diff --git a/Release_Notes.md b/Release_Notes.md
@@ -14,11 +14,11 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Release Notes** #
-_*Last Update: 2023/09/13*_
+_*Last Update: 2023/11/02*_
 
-## Rev 1p0 ##
+## Rev 1p0-rc1 ##
 
-### Rev 1p0 release date: (pending ROM release for official declaration) ###
+### Rev 1p0-rc1 release date: 2023/11/03 (1p0 version pending ROM release for official declaration) ###
 - Caliptra IP Specification: see docs/ folder
 - Caliptra Integration Specification: see docs/ folder
 - Caliptra testplan: see docs/ folder

diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md
diff --git a/docs/images/Caliptra_CDC_JTAG_code_snippet.png b/docs/images/Caliptra_CDC_JTAG_code_snippet.png
diff --git a/docs/images/Caliptra_HW_diagram.png b/docs/images/Caliptra_HW_diagram.png
diff --git a/docs/images/Caliptra_SRAM_interface_timing.png b/docs/images/Caliptra_SRAM_interface_timing.png
diff --git a/docs/images/Caliptra_machine_reliability.png b/docs/images/Caliptra_machine_reliability.png
diff --git a/docs/images/Caliptra_mbox-sender.png b/docs/images/Caliptra_mbox-sender.png
diff --git a/docs/images/Caliptra_mbox_boot_FSM.png b/docs/images/Caliptra_mbox_boot_FSM.png
diff --git a/docs/images/Caliptra_mbox_receiver.png b/docs/images/Caliptra_mbox_receiver.png
diff --git a/docs/images/Caliptra_reset_timing.png b/docs/images/Caliptra_reset_timing.png
diff --git a/docs/images/Caliptra_schematic_jtag.png b/docs/images/Caliptra_schematic_jtag.png
diff --git a/docs/images/Caliptra_soc_interface_block.png b/docs/images/Caliptra_soc_interface_block.png
diff --git a/docs/images/OCP_logo.png b/docs/images/OCP_logo.png
diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl
@@ -264,11 +264,13 @@ reg {
 reg {
     name = "DEBUG & MANUF SERVICE REG";
     desc = "JTAG in debug/manuf mode or SOC can write to this register for ROM/FW defined skips or services; ROM/FW maintains the defintion of these bits.
+            [br]
             [br]Field decode:
-            [br] [0]     MFG_FLAG_GEN_IDEV_CSR: Enable bit for Caliptra to generate an IDEV CSR
-            [br] [15:1]  MFG_FLAG_RSVD
-            [br] [30:16] FAKE_ROM_RSVD
-            [br] [31]    FAKE_ROM_IMAGE_VERIFY_EN: Enable bit to perform image verification within the fake-rom feature
+            [br] [lb]0[rb]     MFG_FLAG_GEN_IDEV_CSR: Enable bit for Caliptra to generate an IDEV CSR
+            [br] [lb]1[rb]     MFG_FLAG_RNG_UNAVAIL: Random Number Generator Unavailable
+            [br] [lb]15:2[rb]  MFG_FLAG_RSVD
+            [br] [lb]30:16[rb] FAKE_ROM_RSVD
+            [br] [lb]31[rb]    FAKE_ROM_IMAGE_VERIFY_EN: Enable bit to perform image verification within the fake-rom feature
             [br]
             [br]Caliptra Access: RW
             [br]SOC Access:      RW