Merge dev-integrate -> main

src/doe/rtl/doe_reg.rdl

@@ -204,8 +204,10 @@ addrmap doe_reg {
     reg error_intr_trig_t {
         name = "Interrupt Trigger Register type definition";
         desc = "Single bit for each interrupt event allows SW to manually
-                trigger occurrence of that event. Upon SW write, the bit
-                will pulse for 1 cycle then clear to 0.";
+                trigger occurrence of that event. Upon SW write, the trigger bit
+                will pulse for 1 cycle then clear to 0. The pulse on the
+                trigger register bit results in the corresponding interrupt
+                status bit being set to 1.";
 
         default hw = na;
         default sw = rw;
@@ -223,8 +225,10 @@ addrmap doe_reg {
     reg notif_intr_trig_t {
         name = "Interrupt Trigger Register type definition";
         desc = "Single bit for each interrupt event allows SW to manually
-                trigger occurrence of that event. Upon SW write, the bit
-                will pulse for 1 cycle then clear to 0.";
+                trigger occurrence of that event. Upon SW write, the trigger bit
+                will pulse for 1 cycle then clear to 0. The pulse on the
+                trigger register bit results in the corresponding interrupt
+                status bit being set to 1.";
 
         default hw = na;
         default sw = rw;

src/ecc/rtl/ecc_reg.rdl

@@ -455,8 +455,10 @@ addrmap ecc_reg {
         reg error_intr_trig_t {
             name = "Interrupt Trigger Register type definition";
             desc = "Single bit for each interrupt event allows SW to manually
-                    trigger occurrence of that event. Upon SW write, the bit
-                    will pulse for 1 cycle then clear to 0.";
+                    trigger occurrence of that event. Upon SW write, the trigger bit
+                    will pulse for 1 cycle then clear to 0. The pulse on the
+                    trigger register bit results in the corresponding interrupt
+                    status bit being set to 1.";
 
             default hw = na;
             default sw = rw;
@@ -471,8 +473,10 @@ addrmap ecc_reg {
         reg notif_intr_trig_t {
             name = "Interrupt Trigger Register type definition";
             desc = "Single bit for each interrupt event allows SW to manually
-                    trigger occurrence of that event. Upon SW write, the bit
-                    will pulse for 1 cycle then clear to 0.";
+                    trigger occurrence of that event. Upon SW write, the trigger bit
+                    will pulse for 1 cycle then clear to 0. The pulse on the
+                    trigger register bit results in the corresponding interrupt
+                    status bit being set to 1.";
 
             default hw = na;
             default sw = rw;

src/hmac/rtl/hmac_reg.rdl

@@ -281,8 +281,10 @@ addrmap hmac_reg {
     reg error_intr_trig_t {
         name = "Interrupt Trigger Register type definition";
         desc = "Single bit for each interrupt event allows SW to manually
-                trigger occurrence of that event. Upon SW write, the bit
-                will pulse for 1 cycle then clear to 0.";
+                trigger occurrence of that event. Upon SW write, the trigger bit
+                will pulse for 1 cycle then clear to 0. The pulse on the
+                trigger register bit results in the corresponding interrupt
+                status bit being set to 1.";
 
         default hw = na;
         default sw = rw;
@@ -300,8 +302,10 @@ addrmap hmac_reg {
     reg notif_intr_trig_t {
         name = "Interrupt Trigger Register type definition";
         desc = "Single bit for each interrupt event allows SW to manually
-                trigger occurrence of that event. Upon SW write, the bit
-                will pulse for 1 cycle then clear to 0.";
+                trigger occurrence of that event. Upon SW write, the trigger bit
+                will pulse for 1 cycle then clear to 0. The pulse on the
+                trigger register bit results in the corresponding interrupt
+                status bit being set to 1.";
 
         default hw = na;
         default sw = rw;
@@ -469,4 +473,4 @@ addrmap hmac_reg {
      * ----------------------- */
     intr_block_t intr_block_rf @0x800;
 
-};
+};

src/integration/asserts/caliptra_top_sva.sv

@@ -430,53 +430,65 @@ module caliptra_top_sva
 
   //WDT checks:
   cascade_wdt_t1_pet: assert property (
-    @(posedge `WDT_PATH.clk)
-    (`WDT_PATH.timer1_restart && !`WDT_PATH.timer2_en) |=> (`WDT_PATH.timer1_count == 'h0)
+    @(posedge `SVA_RDC_CLK)
+    (`WDT_PATH.timer1_restart && !`WDT_PATH.timer2_en && !`WDT_PATH.t1_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
   )
   else $display("SVA ERROR: [Cascade] WDT Timer1 did not restart on pet");
 
   cascade_wdt_t2_pet: assert property (
-    @(posedge `WDT_PATH.clk)
-    (`WDT_PATH.timer2_restart && !`WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
+    @(posedge `SVA_RDC_CLK)
+    (`WDT_PATH.timer2_restart && !`WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer2_count == 'h0)
   )
   else $display("SVA ERROR: [Cascade] WDT Timer2 did not restart on pet");
 
   cascade_wdt_t1_service: assert property (
-    @(posedge `WDT_PATH.clk)
+    @(posedge `SVA_RDC_CLK)
     (`WDT_PATH.wdt_timer1_timeout_serviced && !`WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
   )
   else $display("SVA ERROR: [Cascade] WDT Timer1 did not restart after interrupt service");
 
   cascade_wdt_t2_service: assert property (
-    @(posedge `WDT_PATH.clk)
+    @(posedge `SVA_RDC_CLK)
     (`WDT_PATH.wdt_timer2_timeout_serviced && !`WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
   )
   else $display("SVA ERROR: [Cascade] WDT Timer2 did not restart after interrupt service");
 
   independent_wdt_t1_pet: assert property (
-    @(posedge `WDT_PATH.clk)
+    @(posedge `SVA_RDC_CLK)
     (`WDT_PATH.timer1_restart && `WDT_PATH.timer2_en) |=> (`WDT_PATH.timer1_count == 'h0)
   )
   else $display("SVA ERROR: [Independent] WDT Timer1 did not restart on pet");
 
   independent_wdt_t2_pet: assert property (
-    @(posedge `WDT_PATH.clk)
+    @(posedge `SVA_RDC_CLK)
     (`WDT_PATH.timer2_restart && `WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
   )
   else $display("SVA ERROR: [Independent] WDT Timer2 did not restart on pet");
 
   independent_wdt_t1_service: assert property (
-    @(posedge `WDT_PATH.clk)
+    @(posedge `SVA_RDC_CLK)
     (`WDT_PATH.wdt_timer1_timeout_serviced && `WDT_PATH.timer2_en && !`WDT_PATH.t2_timeout) |=> (`WDT_PATH.timer1_count == 'h0)
   )
   else $display("SVA ERROR: [Independent] WDT Timer1 did not restart after interrupt service");
 
   independent_wdt_t2_service: assert property (
-    @(posedge `WDT_PATH.clk)
+    @(posedge `SVA_RDC_CLK)
     (`WDT_PATH.wdt_timer2_timeout_serviced && `WDT_PATH.timer2_en) |=> (`WDT_PATH.timer2_count == 'h0)
   )
   else $display("SVA ERROR: [Independent] WDT Timer2 did not restart after interrupt service");
 
+  wdt_status_t1_check: assert property (
+    @(posedge `SVA_RDC_CLK)
+    $rose(`WDT_PATH.t1_timeout) |=> $rose(`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_WDT_STATUS.t1_timeout.value)
+  )
+  else $display("SVA ERROR: WDT Status bit not set on t1 expiry!");
+
+  wdt_status_t2_check: assert property (
+    @(posedge `SVA_RDC_CLK)
+    $rose(`WDT_PATH.t2_timeout) |=> $rose(`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_WDT_STATUS.t2_timeout.value)
+  )
+  else $display("SVA ERROR: WDT Status bit not set on t2 expiry!");
+
 
 
   //VALID flag SVA

src/integration/config/caliptra_top_tb.vf

@@ -103,6 +103,7 @@ ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv
 ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_if.sv
+${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_props.sv
 ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_bind.sv
 ${CALIPTRA_ROOT}/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb.sv

src/integration/config/caliptra_top_trng_tb.vf

@@ -103,6 +103,7 @@ ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_pkg.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_veer_sram_export.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb_services.sv
 ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_if.sv
+${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_props.sv
 ${CALIPTRA_ROOT}/src/integration/coverage/caliptra_top_cov_bind.sv
 ${CALIPTRA_ROOT}/src/integration/test_suites/libs/jtagdpi/jtagdpi.sv
 ${CALIPTRA_ROOT}/src/integration/tb/caliptra_top_tb.sv

src/integration/config/compile.yml

@@ -103,6 +103,7 @@ targets:
       - $COMPILE_ROOT/tb/caliptra_veer_sram_export.sv
       - $COMPILE_ROOT/tb/caliptra_top_tb_services.sv
       - $COMPILE_ROOT/coverage/caliptra_top_cov_if.sv
+      - $COMPILE_ROOT/coverage/caliptra_top_cov_props.sv
       - $COMPILE_ROOT/coverage/caliptra_top_cov_bind.sv
       - $COMPILE_ROOT/test_suites/libs/jtagdpi/jtagdpi.sv
       - $COMPILE_ROOT/tb/caliptra_top_tb.sv

src/integration/coverage/caliptra_top_cov_bind.sv

@@ -16,5 +16,6 @@
 module caliptra_top_cov_bind;
     `ifdef FCOV
     bind caliptra_top caliptra_top_cov_if i_caliptra_top_cov_if(.*);
+    bind caliptra_top caliptra_top_cov_props i_caliptra_top_cov_props(.*);
     `endif
 endmodule

src/integration/coverage/caliptra_top_cov_if.sv

@@ -49,8 +49,8 @@ interface caliptra_top_cov_if
         wdt_t1: coverpoint wdt_timer1_en;
         wdt_t2: coverpoint wdt_timer2_en;
         wdt_t1Xt2: cross wdt_t1, wdt_t2;
-        wdt_t1t2Xwarmrst: cross wdt_t1Xt2, cptra_rst_b;
-        wdt_t1t2Xcoldrst: cross wdt_t1Xt2, cptra_pwrgood;
+        // wdt_t1t2Xwarmrst: cross wdt_t1Xt2, cptra_rst_b;
+        // wdt_t1t2Xcoldrst: cross wdt_t1Xt2, cptra_pwrgood;
 
         //-----------------------------------------
         //CLK GATING coverpoints

src/integration/coverage/caliptra_top_cov_props.sv

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+// This file contains properties that define various sequences of events in KV
+
+module caliptra_top_cov_props();
+
+    `ifndef VERILATOR
+
+            //------------------------------------------------------------------------------
+            //Check that WDT was enabled before issuing warm reset
+            //------------------------------------------------------------------------------
+            property cover_prop_wdt_t1_warmrst;
+                @(posedge soc_ifc_top1.i_wdt.clk)
+                ($rose(soc_ifc_top1.i_wdt.timer1_en) |-> ##[0:$] !soc_ifc_top1.i_wdt.cptra_rst_b);
+            endproperty
+            covprop_wdt_t1_warmrst: cover property(cover_prop_wdt_t1_warmrst);
+
+            property cover_prop_wdt_t2_warmrst;
+                @(posedge soc_ifc_top1.i_wdt.clk)
+                ($rose(soc_ifc_top1.i_wdt.timer2_en) |-> ##[0:$] !soc_ifc_top1.i_wdt.cptra_rst_b);
+            endproperty
+            covprop_wdt_t2_warmrst: cover property(cover_prop_wdt_t2_warmrst);
+
+            //------------------------------------------------------------------------------
+            //Check that locks/clear were set before issuing cold reset
+            //------------------------------------------------------------------------------
+            property cover_prop_wdt_t1_coldrst;
+                @(posedge soc_ifc_top1.clk)
+                ($rose(soc_ifc_top1.i_wdt.timer1_en) |=> ##[0:$] !soc_ifc_top1.cptra_pwrgood);
+            endproperty
+            covprop_wdt_t1_coldrst: cover property(cover_prop_wdt_t1_coldrst);
+
+            property cover_prop_wdt_t2_coldrst;
+                @(posedge soc_ifc_top1.clk)
+                ($rose(soc_ifc_top1.i_wdt.timer2_en) |=> ##[0:$] !soc_ifc_top1.cptra_pwrgood);
+            endproperty
+            covprop_wdt_t2_coldrst: cover property(cover_prop_wdt_t2_coldrst);
+
+    `endif
+
+endmodule

src/integration/stimulus/L0_regression.yml

@@ -58,6 +58,7 @@ contents:
         #smoke test interrupt handling
         #smoke test wd timer expiry and nmi generation
         - ../test_suites/smoke_test_wdt/smoke_test_wdt.yml
+        - ../test_suites/smoke_test_wdt_rst/smoke_test_wdt_rst.yml
         - ../test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml
         #smoke test jtag
         #smoke test generic input wire to fw interrupt

src/integration/stimulus/testsuites/caliptra_top_nightly_directed_regression.yml

@@ -48,6 +48,7 @@ contents:
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_datavault_reset/smoke_test_datavault_reset.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_datavault_lock/smoke_test_datavault_lock.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_wdt/smoke_test_wdt.yml
+        - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_wdt_rst/smoke_test_wdt_rst.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.yml
         - ${CALIPTRA_ROOT}/src/integration/test_suites/smoke_test_iccm_reset/smoke_test_iccm_reset.yml

src/integration/test_suites/caliptra_rt/caliptra_rt.c

@@ -155,8 +155,8 @@ void caliptra_rt() {
     lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R, SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK);
 
     //Generate constrained random WDT timer periods
-    wdt_rand_t1_val = rand() % 0xfff;
-    wdt_rand_t2_val = rand() % 0xfff;
+    wdt_rand_t1_val = rand() % 0xfff + 0x5;
+    wdt_rand_t2_val = rand() % 0xfff + 0x5;
 
     while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK));
     if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_CASCADE) { //rand() % 2; //0 - independent mode, 1 - cascade mode
@@ -325,6 +325,9 @@ void caliptra_rt() {
             VPRINTF(LOW, "Intr received: soc_ifc_notif\n");
             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {
                 CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)
+                // Always check mbox FSM state at new command entry to detect
+                // previously-handled error scenarios (FSM is IDLE) or new error
+                // injection (FSM is in ERROR)
                 fsm_chk = soc_ifc_chk_execute_uc();
                 if (fsm_chk != 0) {
                     if (fsm_chk == 0xF) {
@@ -357,6 +360,11 @@ void caliptra_rt() {
                     CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK &
                                                                          ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK &
                                                                          ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_INV_DEV_STS_MASK)
+                    // Run the FSM check once more for late-arrival of errors
+                    // that may correlate with the observed error interrupt
+                    if (soc_ifc_chk_execute_uc()) {
+                        continue;
+                    }
                 }
                 // Any other errors that are flagged at this point are unexpected and should cause a test failure
                 if (cptra_intr_rcv.soc_ifc_error) {
@@ -427,6 +435,35 @@ void caliptra_rt() {
                         }
                         soc_ifc_sha_accel_clr_lock();
                     }
+                    else if ((op.cmd == MBOX_CMD_SHA384_STREAM_REQ) | (op.cmd == MBOX_CMD_SHA512_STREAM_REQ)) {
+                        enum sha_accel_mode_e mode;
+                        mode = (op.cmd == MBOX_CMD_SHA384_STREAM_REQ) ? SHA_STREAM_384 : SHA_STREAM_512;
+                        //First dword contains the start address
+                        temp = soc_ifc_mbox_read_dataout_single();
+                        //ignore the bytes used for start address
+                        op.dlen = op.dlen - 4;
+                        //Acquire SHA Accel lock
+                        soc_ifc_sha_accel_acquire_lock();
+                        soc_ifc_sha_accel_wr_mode(mode);
+                        //write dlen in bytes
+                        lsu_write_32((uintptr_t) (CLP_SHA512_ACC_CSR_DLEN), op.dlen);
+                        //Stream the KAT to the sha accelerator
+                        for (loop_iter = 0; loop_iter<op.dlen; loop_iter+=4) {
+                            read_data = soc_ifc_mbox_read_dataout_single();
+                            lsu_write_32((uintptr_t) (CLP_SHA512_ACC_CSR_DATAIN), read_data);
+                        }
+                        soc_ifc_sha_accel_execute();
+                        soc_ifc_sha_accel_poll_status();
+                        lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DLEN), (mode == SHA_MBOX_384) ? 48 : 64);
+                        //read the digest and write it back to the mailbox
+                        reg_addr = CLP_SHA512_ACC_CSR_DIGEST_0;
+                        while (reg_addr <= ((mode == SHA_MBOX_384) ? CLP_SHA512_ACC_CSR_DIGEST_11 : CLP_SHA512_ACC_CSR_DIGEST_15)) {
+                            read_data = lsu_read_32(reg_addr);
+                            lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DATAIN), read_data);
+                            reg_addr = reg_addr + 4;
+                        }
+                        soc_ifc_sha_accel_clr_lock();
+                    }
                     else {
                         // Read provided data
                         read_data = soc_ifc_mbox_read_dataout_single();

src/integration/test_suites/libs/soc_ifc/soc_ifc.c

@@ -257,7 +257,10 @@ void soc_ifc_sha_accel_wr_mode(enum sha_accel_mode_e mode) {
 }
 
 void soc_ifc_sha_accel_poll_status() {
-    while((lsu_read_32(CLP_SHA512_ACC_CSR_STATUS) & SHA512_ACC_CSR_STATUS_VALID_MASK) == 0);
+    while((lsu_read_32(CLP_SHA512_ACC_CSR_STATUS) & SHA512_ACC_CSR_STATUS_VALID_MASK) == 0) {
+        //poke at the mailbox direct read path to create stall scenario
+        lsu_read_32(0x30000000);
+    };
 }
 
 void soc_ifc_sha_accel_clr_lock() {

src/integration/test_suites/libs/soc_ifc/soc_ifc.h

@@ -66,7 +66,9 @@ enum mbox_cmd_e {
     MBOX_CMD_FMC_UPDATE = 0xba5eba11,
     MBOX_CMD_RT_UPDATE  = 0xbabecafe,
     MBOX_CMD_SHA384_REQ = 0x40C0FFEE,
-    MBOX_CMD_SHA512_REQ = 0x41C0FFEE
+    MBOX_CMD_SHA512_REQ = 0x41C0FFEE,
+    MBOX_CMD_SHA384_STREAM_REQ = 0x42C0FFEE,
+    MBOX_CMD_SHA512_STREAM_REQ = 0x43C0FFEE
 };
 
 // Boundaries against which the incoming remote FW images are aligned

src/integration/test_suites/libs/wdt/wdt.h

@@ -14,7 +14,7 @@
 //
 
 #ifndef WDT_H
-    #define WDT_H_H
+    #define WDT_H
 
 #include "caliptra_defines.h"
 #include "caliptra_reg.h"